2
* Tiny Code Generator for QEMU
4
* Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5
* Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6
* Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
8
* Permission is hereby granted, free of charge, to any person obtaining a copy
9
* of this software and associated documentation files (the "Software"), to deal
10
* in the Software without restriction, including without limitation the rights
11
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12
* copies of the Software, and to permit persons to whom the Software is
13
* furnished to do so, subject to the following conditions:
15
* The above copyright notice and this permission notice shall be included in
16
* all copies or substantial portions of the Software.
18
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27
#include "../tcg-ldst.c.inc"
28
#include "../tcg-pool.c.inc"
30
#if TCG_TARGET_REG_BITS == 32
31
# define LO_OFF (HOST_BIG_ENDIAN * 4)
32
# define HI_OFF (4 - LO_OFF)
34
/* Assert at compile-time that these values are never used for 64-bit. */
35
# define LO_OFF ({ qemu_build_not_reached(); 0; })36
# define HI_OFF ({ qemu_build_not_reached(); 0; })39
#ifdef CONFIG_DEBUG_TCG
40
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {76
#define TCG_TMP0 TCG_REG_AT
77
#define TCG_TMP1 TCG_REG_T9
78
#define TCG_TMP2 TCG_REG_T8
79
#define TCG_TMP3 TCG_REG_T7
81
#define TCG_GUEST_BASE_REG TCG_REG_S7
82
#if TCG_TARGET_REG_BITS == 64
83
#define TCG_REG_TB TCG_REG_S6
85
#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; })88
/* check if we really need so many registers :P */
89
static const int tcg_target_reg_alloc_order[] = {90
/* Call saved registers. */
101
/* Call clobbered registers. */
111
/* Argument registers, opposite order of allocation. */
122
static const TCGReg tcg_target_call_iarg_regs[] = {127
#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
135
static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
137
tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
138
tcg_debug_assert(slot >= 0 && slot <= 1);
139
return TCG_REG_V0 + slot;
142
static const tcg_insn_unit *tb_ret_addr;
143
static const tcg_insn_unit *bswap32_addr;
144
static const tcg_insn_unit *bswap32u_addr;
145
static const tcg_insn_unit *bswap64_addr;
147
static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
149
/* Let the compiler perform the right-shift as part of the arithmetic. */
150
const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
151
ptrdiff_t disp = target - (src_rx + 1);
152
if (disp == (int16_t)disp) {153
*src_rw = deposit32(*src_rw, 0, 16, disp);
159
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
160
intptr_t value, intptr_t addend)
165
return reloc_pc16(code_ptr, (const tcg_insn_unit *)value);
167
if (value != (int16_t)value) {170
*code_ptr = deposit32(*code_ptr, 0, 16, value);
173
g_assert_not_reached();
176
#define TCG_CT_CONST_ZERO 0x100
177
#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */
178
#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */
179
#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */
180
#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */
181
#define TCG_CT_CONST_WSZ 0x2000 /* word size */
183
#define ALL_GENERAL_REGS 0xffffffffu
185
static bool is_p2m1(tcg_target_long val)
187
return val && ((val + 1) & val) == 0;
190
/* test if a constant matches the constraint */
191
static bool tcg_target_const_match(int64_t val, int ct,
192
TCGType type, TCGCond cond, int vece)
194
if (ct & TCG_CT_CONST) {196
} else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {198
} else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {200
} else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {202
} else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) {204
} else if ((ct & TCG_CT_CONST_P2M1)
205
&& use_mips32r2_instructions && is_p2m1(val)) {207
} else if ((ct & TCG_CT_CONST_WSZ)
208
&& val == (type == TCG_TYPE_I32 ? 32 : 64)) {214
/* instruction opcodes */
220
OPC_BLEZ = 006 << 26,
221
OPC_BGTZ = 007 << 26,
222
OPC_ADDIU = 011 << 26,
223
OPC_SLTI = 012 << 26,
224
OPC_SLTIU = 013 << 26,
225
OPC_ANDI = 014 << 26,
227
OPC_XORI = 016 << 26,
229
OPC_BNEL = 025 << 26,
230
OPC_BNEZALC_R6 = 030 << 26,
231
OPC_DADDIU = 031 << 26,
252
OPC_SPECIAL = 000 << 26,
253
OPC_SLL = OPC_SPECIAL | 000,
254
OPC_SRL = OPC_SPECIAL | 002,
255
OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21),
256
OPC_SRA = OPC_SPECIAL | 003,
257
OPC_SLLV = OPC_SPECIAL | 004,
258
OPC_SRLV = OPC_SPECIAL | 006,
259
OPC_ROTRV = OPC_SPECIAL | 006 | 0100,
260
OPC_SRAV = OPC_SPECIAL | 007,
261
OPC_JR_R5 = OPC_SPECIAL | 010,
262
OPC_JALR = OPC_SPECIAL | 011,
263
OPC_MOVZ = OPC_SPECIAL | 012,
264
OPC_MOVN = OPC_SPECIAL | 013,
265
OPC_SYNC = OPC_SPECIAL | 017,
266
OPC_MFHI = OPC_SPECIAL | 020,
267
OPC_MFLO = OPC_SPECIAL | 022,
268
OPC_DSLLV = OPC_SPECIAL | 024,
269
OPC_DSRLV = OPC_SPECIAL | 026,
270
OPC_DROTRV = OPC_SPECIAL | 026 | 0100,
271
OPC_DSRAV = OPC_SPECIAL | 027,
272
OPC_MULT = OPC_SPECIAL | 030,
273
OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200,
274
OPC_MUH = OPC_SPECIAL | 030 | 0300,
275
OPC_MULTU = OPC_SPECIAL | 031,
276
OPC_MULU = OPC_SPECIAL | 031 | 0200,
277
OPC_MUHU = OPC_SPECIAL | 031 | 0300,
278
OPC_DIV = OPC_SPECIAL | 032,
279
OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200,
280
OPC_MOD = OPC_SPECIAL | 032 | 0300,
281
OPC_DIVU = OPC_SPECIAL | 033,
282
OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200,
283
OPC_MODU = OPC_SPECIAL | 033 | 0300,
284
OPC_DMULT = OPC_SPECIAL | 034,
285
OPC_DMUL = OPC_SPECIAL | 034 | 0200,
286
OPC_DMUH = OPC_SPECIAL | 034 | 0300,
287
OPC_DMULTU = OPC_SPECIAL | 035,
288
OPC_DMULU = OPC_SPECIAL | 035 | 0200,
289
OPC_DMUHU = OPC_SPECIAL | 035 | 0300,
290
OPC_DDIV = OPC_SPECIAL | 036,
291
OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200,
292
OPC_DMOD = OPC_SPECIAL | 036 | 0300,
293
OPC_DDIVU = OPC_SPECIAL | 037,
294
OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200,
295
OPC_DMODU = OPC_SPECIAL | 037 | 0300,
296
OPC_ADDU = OPC_SPECIAL | 041,
297
OPC_SUBU = OPC_SPECIAL | 043,
298
OPC_AND = OPC_SPECIAL | 044,
299
OPC_OR = OPC_SPECIAL | 045,
300
OPC_XOR = OPC_SPECIAL | 046,
301
OPC_NOR = OPC_SPECIAL | 047,
302
OPC_SLT = OPC_SPECIAL | 052,
303
OPC_SLTU = OPC_SPECIAL | 053,
304
OPC_DADDU = OPC_SPECIAL | 055,
305
OPC_DSUBU = OPC_SPECIAL | 057,
306
OPC_SELEQZ = OPC_SPECIAL | 065,
307
OPC_SELNEZ = OPC_SPECIAL | 067,
308
OPC_DSLL = OPC_SPECIAL | 070,
309
OPC_DSRL = OPC_SPECIAL | 072,
310
OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21),
311
OPC_DSRA = OPC_SPECIAL | 073,
312
OPC_DSLL32 = OPC_SPECIAL | 074,
313
OPC_DSRL32 = OPC_SPECIAL | 076,
314
OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21),
315
OPC_DSRA32 = OPC_SPECIAL | 077,
316
OPC_CLZ_R6 = OPC_SPECIAL | 0120,
317
OPC_DCLZ_R6 = OPC_SPECIAL | 0122,
319
OPC_REGIMM = 001 << 26,
320
OPC_BLTZ = OPC_REGIMM | (000 << 16),
321
OPC_BGEZ = OPC_REGIMM | (001 << 16),
323
OPC_SPECIAL2 = 034 << 26,
324
OPC_MUL_R5 = OPC_SPECIAL2 | 002,
325
OPC_CLZ = OPC_SPECIAL2 | 040,
326
OPC_DCLZ = OPC_SPECIAL2 | 044,
328
OPC_SPECIAL3 = 037 << 26,
329
OPC_EXT = OPC_SPECIAL3 | 000,
330
OPC_DEXTM = OPC_SPECIAL3 | 001,
331
OPC_DEXTU = OPC_SPECIAL3 | 002,
332
OPC_DEXT = OPC_SPECIAL3 | 003,
333
OPC_INS = OPC_SPECIAL3 | 004,
334
OPC_DINSM = OPC_SPECIAL3 | 005,
335
OPC_DINSU = OPC_SPECIAL3 | 006,
336
OPC_DINS = OPC_SPECIAL3 | 007,
337
OPC_WSBH = OPC_SPECIAL3 | 00240,
338
OPC_DSBH = OPC_SPECIAL3 | 00244,
339
OPC_DSHD = OPC_SPECIAL3 | 00544,
340
OPC_SEB = OPC_SPECIAL3 | 02040,
341
OPC_SEH = OPC_SPECIAL3 | 03040,
343
/* MIPS r6 doesn't have JR, JALR should be used instead */
344
OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5,
347
* MIPS r6 replaces MUL with an alternative encoding which is
348
* backwards-compatible at the assembly level.
350
OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5,
352
/* MIPS r6 introduced names for weaker variants of SYNC. These are
353
backward compatible to previous architecture revisions. */
354
OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6,
355
OPC_SYNC_MB = OPC_SYNC | 0x10 << 6,
356
OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
357
OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
358
OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
360
/* Aliases for convenience. */
361
ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
362
ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
368
static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
369
TCGReg rd, TCGReg rs, TCGReg rt)
374
inst |= (rs & 0x1F) << 21;
375
inst |= (rt & 0x1F) << 16;
376
inst |= (rd & 0x1F) << 11;
383
static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
384
TCGReg rt, TCGReg rs, TCGArg imm)
389
inst |= (rs & 0x1F) << 21;
390
inst |= (rt & 0x1F) << 16;
391
inst |= (imm & 0xffff);
398
static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
399
TCGReg rs, int msb, int lsb)
404
inst |= (rs & 0x1F) << 21;
405
inst |= (rt & 0x1F) << 16;
406
inst |= (msb & 0x1F) << 11;
407
inst |= (lsb & 0x1F) << 6;
411
static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm,
412
MIPSInsn oph, TCGReg rt, TCGReg rs,
419
} else if (msb >= 32) {423
tcg_out_opc_bf(s, opc, rt, rs, msb, lsb);
429
static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs)
431
tcg_out_opc_imm(s, opc, rt, rs, 0);
437
static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
438
TCGReg rd, TCGReg rt, TCGArg sa)
443
inst |= (rt & 0x1F) << 16;
444
inst |= (rd & 0x1F) << 11;
445
inst |= (sa & 0x1F) << 6;
450
static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
451
TCGReg rd, TCGReg rt, TCGArg sa)
455
inst = (sa & 32 ? opc2 : opc1);
456
inst |= (rt & 0x1F) << 16;
457
inst |= (rd & 0x1F) << 11;
458
inst |= (sa & 0x1F) << 6;
464
* Returns true if the branch was in range and the insn was emitted.
466
static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target)
468
uintptr_t dest = (uintptr_t)target;
469
uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4;
472
/* The pc-region branch happens within the 256MB region of
473
the delay slot (thus the +4). */
474
if ((from ^ dest) & -(1 << 28)) {477
tcg_debug_assert((dest & 3) == 0);
480
inst |= (dest >> 2) & 0x3ffffff;
485
static void tcg_out_nop(TCGContext *s)
490
static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
492
memset(p, 0, count * sizeof(tcg_insn_unit));
495
static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
497
tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa);
500
static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
502
tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa);
505
static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa)
507
tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa);
510
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
512
/* Simple reg-reg move, optimising out the 'do nothing' case */
514
tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
519
static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg)
521
if (arg == (int16_t)arg) {522
tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
525
if (arg == (uint16_t)arg) {526
tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
529
if (arg == (int32_t)arg && (arg & 0xffff) == 0) {530
tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
536
static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg)
539
* All signed 32-bit constants are loadable with two immediates,
540
* and everything else requires more work.
542
if (arg == (int32_t)arg) {543
if (!tcg_out_movi_one(s, ret, arg)) {544
tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
545
tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
552
static void tcg_out_movi_pool(TCGContext *s, TCGReg ret,
553
tcg_target_long arg, TCGReg tbreg)
555
new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL));
556
tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0);
559
static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
560
tcg_target_long arg, TCGReg tbreg)
565
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {569
/* Load all 32-bit constants. */
570
if (tcg_out_movi_two(s, ret, arg)) {573
assert(TCG_TARGET_REG_BITS == 64);
575
/* Load addresses within 2GB of TB with 1 or 3 insns. */
576
tmp = tcg_tbrel_diff(s, (void *)arg);
577
if (tmp == (int16_t)tmp) {578
tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp);
581
if (tcg_out_movi_two(s, ret, tmp)) {582
tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg);
587
* Load bitmasks with a right-shift. This is good for things
588
* like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4.
589
* or similarly using LUI. For this to work, bit 31 must be set.
591
if (arg > 0 && (int32_t)arg < 0) {593
if (tcg_out_movi_one(s, ret, arg << sh)) {594
tcg_out_dsrl(s, ret, ret, sh);
600
* Load slightly larger constants using left-shift.
601
* Limit this sequence to 3 insns to avoid too much expansion.
604
if (sh && tcg_out_movi_two(s, ret, arg >> sh)) {605
tcg_out_dsll(s, ret, ret, sh);
610
* Load slightly larger constants using left-shift and add/or.
611
* Prefer addi with a negative immediate when that would produce
612
* a larger shift. For this to work, bits 15 and 16 must be set.
616
if ((arg & 0x18000) == 0x18000) {622
if (tcg_out_movi_one(s, ret, tmp)) {623
tcg_out_dsll(s, ret, ret, sh);
624
tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo);
629
/* Otherwise, put 64-bit constants into the constant pool. */
630
tcg_out_movi_pool(s, ret, arg, tbreg);
633
static void tcg_out_movi(TCGContext *s, TCGType type,
634
TCGReg ret, tcg_target_long arg)
636
TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0;
637
tcg_out_movi_int(s, type, ret, arg, tbreg);
640
static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
642
tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32);
643
tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs);
646
static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs)
648
tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff);
651
static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
653
tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32);
654
tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs);
657
static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs)
659
tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff);
662
static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs)
664
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
665
tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0);
668
static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
671
tcg_out_ext32s(s, rd, rs);
675
static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs)
677
tcg_out_ext32u(s, rd, rs);
680
static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs)
682
tcg_out_ext32s(s, rd, rs);
685
static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
690
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
693
/* This function is only used for passing structs by reference. */
694
g_assert_not_reached();
697
static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
699
/* ret and arg can't be register tmp0 */
700
tcg_debug_assert(ret != TCG_TMP0);
701
tcg_debug_assert(arg != TCG_TMP0);
703
/* With arg = abcd: */
704
if (use_mips32r2_instructions) {705
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */
706
if (flags & TCG_BSWAP_OS) {707
tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */
708
} else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {709
tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */
714
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */
715
if (!(flags & TCG_BSWAP_IZ)) {716
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */
718
if (flags & TCG_BSWAP_OS) {719
tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */
720
tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */
722
tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */
723
if (flags & TCG_BSWAP_OZ) {724
tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */
727
tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */
730
static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
732
if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) {733
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub);
734
tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0);
738
static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags)
740
if (use_mips32r2_instructions) {741
tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg);
742
tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16);
743
if (flags & TCG_BSWAP_OZ) {744
tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0);
747
if (flags & TCG_BSWAP_OZ) {748
tcg_out_bswap_subr(s, bswap32u_addr);
750
tcg_out_bswap_subr(s, bswap32_addr);
752
/* delay slot -- never omit the insn, like tcg_out_mov might. */
753
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
754
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
758
static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg)
760
if (use_mips32r2_instructions) {761
tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg);
762
tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret);
764
tcg_out_bswap_subr(s, bswap64_addr);
765
/* delay slot -- never omit the insn, like tcg_out_mov might. */
766
tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO);
767
tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3);
771
static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
773
tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
774
if (use_mips32r2_instructions) {775
tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
777
tcg_out_dsll(s, ret, arg, 32);
778
tcg_out_dsrl(s, ret, ret, 32);
782
static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
783
TCGReg addr, intptr_t ofs)
787
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
788
if (addr != TCG_REG_ZERO) {789
tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
793
tcg_out_opc_imm(s, opc, data, addr, lo);
796
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
797
TCGReg arg1, intptr_t arg2)
799
MIPSInsn opc = OPC_LD;
800
if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {803
tcg_out_ldst(s, opc, arg, arg1, arg2);
806
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
807
TCGReg arg1, intptr_t arg2)
809
MIPSInsn opc = OPC_SD;
810
if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {813
tcg_out_ldst(s, opc, arg, arg1, arg2);
816
static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
817
TCGReg base, intptr_t ofs)
820
tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
826
static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
827
TCGReg ah, TCGArg bl, TCGArg bh, bool cbl,
828
bool cbh, bool is_sub)
830
TCGReg th = TCG_TMP1;
832
/* If we have a negative constant such that negating it would
833
make the high part zero, we can (usually) eliminate one insn. */
834
if (cbl && cbh && bh == -1 && bl != 0) {840
/* By operating on the high part first, we get to use the final
841
carry operation to move back from the temporary. */
843
tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh);
844
} else if (bh != 0 || ah == rl) {845
tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh));
850
/* Note that tcg optimization should eliminate the bl == 0 case. */
853
tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl);
854
tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl);
856
tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl);
857
tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl);
859
tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0);
862
tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
863
tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
864
} else if (rl == al && rl == bl) {865
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1);
866
tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
868
tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
869
tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
871
tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0);
875
#define SETCOND_INV TCG_TARGET_NB_REGS
876
#define SETCOND_NEZ (SETCOND_INV << 1)
877
#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ)
879
static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret,
880
TCGReg arg1, TCGReg arg2)
885
case TCG_COND_EQ: /* -> NE */
886
case TCG_COND_GE: /* -> LT */
887
case TCG_COND_GEU: /* -> LTU */
888
case TCG_COND_LE: /* -> GT */
889
case TCG_COND_LEU: /* -> GTU */
890
cond = tcg_invert_cond(cond);
891
flags ^= SETCOND_INV;
899
flags |= SETCOND_NEZ;
903
tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2);
906
tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
909
tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
912
tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
915
tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
918
g_assert_not_reached();
923
static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags)
925
if (tmpflags != ret) {926
TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
928
switch (tmpflags & SETCOND_FLAGS) {930
/* Intermediate result is boolean: simply invert. */
931
tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1);
934
/* Intermediate result is zero/non-zero: test != 0. */
935
tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp);
937
case SETCOND_NEZ | SETCOND_INV:
938
/* Intermediate result is zero/non-zero: test == 0. */
939
tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1);
942
g_assert_not_reached();
947
static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
948
TCGReg arg1, TCGReg arg2)
950
int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2);
951
tcg_out_setcond_end(s, ret, tmpflags);
954
static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
955
TCGReg arg2, TCGLabel *l)
957
static const MIPSInsn b_zero[16] = {958
[TCG_COND_LT] = OPC_BLTZ,
959
[TCG_COND_GT] = OPC_BGTZ,
960
[TCG_COND_LE] = OPC_BLEZ,
961
[TCG_COND_GE] = OPC_BGEZ,
978
b_opc = b_zero[cond];
988
int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2);
991
arg1 = tmpflags & ~SETCOND_FLAGS;
992
b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE;
995
tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0);
996
tcg_out_opc_br(s, b_opc, arg1, arg2);
1000
static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret,
1001
TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
1007
flags |= SETCOND_INV;
1010
flags |= SETCOND_NEZ;
1011
tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl);
1012
tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh);
1013
tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1);
1017
tcg_out_setcond(s, TCG_COND_EQ, TCG_TMP0, ah, bh);
1018
tcg_out_setcond(s, tcg_unsigned_cond(cond), TCG_TMP1, al, bl);
1019
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0);
1020
tcg_out_setcond(s, tcg_high_cond(cond), TCG_TMP0, ah, bh);
1021
tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1);
1027
static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
1028
TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
1030
int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh);
1031
tcg_out_setcond_end(s, ret, tmpflags);
1034
static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
1035
TCGReg bl, TCGReg bh, TCGLabel *l)
1037
int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh);
1038
TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
1039
MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE;
1041
tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0);
1042
tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO);
1046
static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
1047
TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2)
1052
/* If one of the values is zero, put it last to match SEL*Z instructions */
1053
if (use_mips32r6_instructions && v1 == 0) {1056
cond = tcg_invert_cond(cond);
1059
tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2);
1060
c1 = tmpflags & ~SETCOND_FLAGS;
1061
eqz = tmpflags & SETCOND_INV;
1063
if (use_mips32r6_instructions) {1064
MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ;
1065
MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ;
1068
tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1);
1070
tcg_out_opc_reg(s, m_opc_t, ret, v1, c1);
1072
tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1);
1077
/* This should be guaranteed via constraints */
1078
tcg_debug_assert(v2 == ret);
1080
if (use_movnz_instructions) {1081
MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN;
1082
tcg_out_opc_reg(s, m_opc, ret, v1, c1);
1084
/* Invert the condition in order to branch over the move. */
1085
MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ;
1086
tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2);
1088
/* Open-code tcg_out_mov, without the nop-move check. */
1089
tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO);
1093
static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
1096
* Note that __mips_abicalls requires the called function's address
1097
* to be loaded into $25 (t9), even if a direct branch is in range.
1099
* For n64, always drop the pointer into the constant pool.
1100
* We can re-use helper addresses often and do not want any
1101
* of the longer sequences tcg_out_movi may try.
1103
if (sizeof(uintptr_t) == 8) {1104
tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB);
1106
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
1109
/* But do try a direct branch, allowing the cpu better insn prefetch. */
1111
if (!tcg_out_opc_jmp(s, OPC_J, arg)) {1112
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
1115
if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) {1116
tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0);
1121
static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
1122
const TCGHelperInfo *info)
1124
tcg_out_call_int(s, arg, false);
1128
/* We have four temps, we might as well expose three of them. */
1129
static const TCGLdstHelperParam ldst_helper_param = {1130
.ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 }1133
static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1135
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1136
MemOp opc = get_memop(l->oi);
1138
/* resolve label address */
1139
if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1140
|| (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) {1144
tcg_out_ld_helper_args(s, l, &ldst_helper_param);
1146
tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false);
1150
tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param);
1152
tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1153
if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {1162
static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
1164
const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr);
1165
MemOp opc = get_memop(l->oi);
1167
/* resolve label address */
1168
if (!reloc_pc16(l->label_ptr[0], tgt_rx)
1169
|| (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) {1173
tcg_out_st_helper_args(s, l, &ldst_helper_param);
1175
tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false);
1179
tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO);
1180
if (!reloc_pc16(s->code_ptr - 1, l->raddr)) {1194
bool tcg_target_has_memory_bswap(MemOp memop)
1199
/* We expect to use a 16-bit negative offset from ENV. */
1200
#define MIN_TLB_MASK_TABLE_OFS -32768
1203
* For system-mode, perform the TLB load and compare.
1204
* For user-mode, perform any required alignment tests.
1205
* In both cases, return a TCGLabelQemuLdst structure if the slow path
1206
* is required and fill in @h with the host address for the fast path.
1208
static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
1209
TCGReg addrlo, TCGReg addrhi,
1210
MemOpIdx oi, bool is_ld)
1212
TCGType addr_type = s->addr_type;
1213
TCGLabelQemuLdst *ldst = NULL;
1214
MemOp opc = get_memop(oi);
1216
unsigned s_bits = opc & MO_SIZE;
1220
h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
1221
a_bits = h->aa.align;
1222
a_mask = (1 << a_bits) - 1;
1224
if (tcg_use_softmmu) {1225
unsigned s_mask = (1 << s_bits) - 1;
1226
int mem_index = get_mmuidx(oi);
1227
int fast_off = tlb_mask_table_ofs(s, mem_index);
1228
int mask_off = fast_off + offsetof(CPUTLBDescFast, mask);
1229
int table_off = fast_off + offsetof(CPUTLBDescFast, table);
1230
int add_off = offsetof(CPUTLBEntry, addend);
1231
int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read)
1232
: offsetof(CPUTLBEntry, addr_write);
1234
ldst = new_ldst_label(s);
1235
ldst->is_ld = is_ld;
1237
ldst->addrlo_reg = addrlo;
1238
ldst->addrhi_reg = addrhi;
1240
/* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */
1241
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off);
1242
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
1244
/* Extract the TLB index from the address into TMP3. */
1245
if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {1246
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo,
1247
s->page_bits - CPU_TLB_ENTRY_BITS);
1249
tcg_out_dsrl(s, TCG_TMP3, addrlo,
1250
s->page_bits - CPU_TLB_ENTRY_BITS);
1252
tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
1254
/* Add the tlb_table pointer, creating the CPUTLBEntry address. */
1255
tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
1257
if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {1258
/* Load the (low half) tlb comparator. */
1259
tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
1260
cmp_off + HOST_BIG_ENDIAN * 4);
1262
tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off);
1265
if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {1266
/* Load the tlb addend for the fast path. */
1267
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
1271
* Mask the page bits, keeping the alignment bits to compare against.
1272
* For unaligned accesses, compare against the end of the access to
1273
* verify that it does not cross a page boundary.
1275
tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask);
1276
if (a_mask < s_mask) {1277
tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32
1278
|| addr_type == TCG_TYPE_I32
1279
? OPC_ADDIU : OPC_DADDIU),
1280
TCG_TMP2, addrlo, s_mask - a_mask);
1281
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
1283
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo);
1286
/* Zero extend a 32-bit guest address for a 64-bit host. */
1287
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {1288
tcg_out_ext32u(s, TCG_TMP2, addrlo);
1292
ldst->label_ptr[0] = s->code_ptr;
1293
tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0);
1295
/* Load and test the high half tlb comparator. */
1296
if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) {1298
tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF);
1300
/* Load the tlb addend for the fast path. */
1301
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off);
1303
ldst->label_ptr[1] = s->code_ptr;
1304
tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0);
1309
tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo);
1311
if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {1312
ldst = new_ldst_label(s);
1314
ldst->is_ld = is_ld;
1316
ldst->addrlo_reg = addrlo;
1317
ldst->addrhi_reg = addrhi;
1319
/* We are expecting a_bits to max out at 7, much lower than ANDI. */
1320
tcg_debug_assert(a_bits < 16);
1321
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask);
1323
ldst->label_ptr[0] = s->code_ptr;
1324
if (use_mips32r6_instructions) {1325
tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0);
1327
tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO);
1333
if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {1334
tcg_out_ext32u(s, TCG_REG_A0, base);
1338
if (guest_base == (int16_t)guest_base) {1339
tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
1341
tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
1342
TCG_GUEST_BASE_REG);
1352
static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1353
TCGReg base, MemOp opc, TCGType type)
1355
switch (opc & MO_SSIZE) {1357
tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1360
tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
1363
tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
1366
tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
1369
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {1370
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
1375
tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
1378
/* Prefer to load from offset 0 first, but allow for overlap. */
1379
if (TCG_TARGET_REG_BITS == 64) {1380
tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
1381
} else if (HOST_BIG_ENDIAN ? hi != base : lo == base) {1382
tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1383
tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1385
tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
1386
tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
1390
g_assert_not_reached();
1394
static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1395
TCGReg base, MemOp opc, TCGType type)
1397
const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR;
1398
const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL;
1399
const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR;
1400
const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL;
1401
bool sgn = opc & MO_SIGN;
1403
switch (opc & MO_SIZE) {1405
if (HOST_BIG_ENDIAN) {1406
tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0);
1407
tcg_out_opc_imm(s, OPC_LBU, lo, base, 1);
1408
if (use_mips32r2_instructions) {1409
tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1411
tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8);
1412
tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0);
1414
} else if (use_mips32r2_instructions && lo != base) {1415
tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
1416
tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1);
1417
tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8);
1419
tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0);
1420
tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1);
1421
tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8);
1422
tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1);
1427
tcg_out_opc_imm(s, lw1, lo, base, 0);
1428
tcg_out_opc_imm(s, lw2, lo, base, 3);
1429
if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) {1430
tcg_out_ext32u(s, lo, lo);
1435
if (TCG_TARGET_REG_BITS == 64) {1436
tcg_out_opc_imm(s, ld1, lo, base, 0);
1437
tcg_out_opc_imm(s, ld2, lo, base, 7);
1439
tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
1440
tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
1441
tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
1442
tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
1447
g_assert_not_reached();
1451
static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
1452
TCGReg addrlo, TCGReg addrhi,
1453
MemOpIdx oi, TCGType data_type)
1455
MemOp opc = get_memop(oi);
1456
TCGLabelQemuLdst *ldst;
1459
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true);
1461
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {1462
tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type);
1464
tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type);
1468
ldst->type = data_type;
1469
ldst->datalo_reg = datalo;
1470
ldst->datahi_reg = datahi;
1471
ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1475
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
1476
TCGReg base, MemOp opc)
1478
switch (opc & MO_SIZE) {1480
tcg_out_opc_imm(s, OPC_SB, lo, base, 0);
1483
tcg_out_opc_imm(s, OPC_SH, lo, base, 0);
1486
tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
1489
if (TCG_TARGET_REG_BITS == 64) {1490
tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
1492
tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0);
1493
tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4);
1497
g_assert_not_reached();
1501
static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
1502
TCGReg base, MemOp opc)
1504
const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR;
1505
const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL;
1506
const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR;
1507
const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL;
1509
switch (opc & MO_SIZE) {1511
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8);
1512
tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0);
1513
tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1);
1517
tcg_out_opc_imm(s, sw1, lo, base, 0);
1518
tcg_out_opc_imm(s, sw2, lo, base, 3);
1522
if (TCG_TARGET_REG_BITS == 64) {1523
tcg_out_opc_imm(s, sd1, lo, base, 0);
1524
tcg_out_opc_imm(s, sd2, lo, base, 7);
1526
tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
1527
tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
1528
tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
1529
tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
1534
g_assert_not_reached();
1538
static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
1539
TCGReg addrlo, TCGReg addrhi,
1540
MemOpIdx oi, TCGType data_type)
1542
MemOp opc = get_memop(oi);
1543
TCGLabelQemuLdst *ldst;
1546
ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false);
1548
if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {1549
tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
1551
tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc);
1555
ldst->type = data_type;
1556
ldst->datalo_reg = datalo;
1557
ldst->datahi_reg = datahi;
1558
ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1562
static void tcg_out_mb(TCGContext *s, TCGArg a0)
1564
static const MIPSInsn sync[] = {1565
/* Note that SYNC_MB is a slightly weaker than SYNC 0,
1566
as the former is an ordering barrier and the latter
1567
is a completion barrier. */
1568
[0 ... TCG_MO_ALL] = OPC_SYNC_MB,
1569
[TCG_MO_LD_LD] = OPC_SYNC_RMB,
1570
[TCG_MO_ST_ST] = OPC_SYNC_WMB,
1571
[TCG_MO_LD_ST] = OPC_SYNC_RELEASE,
1572
[TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE,
1573
[TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE,
1575
tcg_out32(s, sync[a0 & TCG_MO_ALL]);
1578
static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6,
1579
int width, TCGReg a0, TCGReg a1, TCGArg a2)
1581
if (use_mips32r6_instructions) {1583
tcg_out_opc_reg(s, opcv6, a0, a1, 0);
1585
tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0);
1586
tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0);
1590
tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1591
} else if (a0 == a2) {1592
tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1593
tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1);
1594
} else if (a0 != a1) {1595
tcg_out_opc_reg(s, opcv2, a0, a1, a1);
1596
tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1);
1598
tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1);
1599
tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1);
1600
tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0);
1605
static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1607
TCGReg base = TCG_REG_ZERO;
1612
if (TCG_TARGET_REG_BITS == 64) {1613
ofs = tcg_tbrel_diff(s, (void *)a0);
1619
tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
1620
tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB);
1626
tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
1629
if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {1630
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr);
1631
tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
1634
tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo);
1637
static void tcg_out_goto_tb(TCGContext *s, int which)
1639
intptr_t ofs = get_jmp_target_addr(s, which);
1642
/* indirect jump method */
1643
if (TCG_TARGET_REG_BITS == 64) {1646
ofs = tcg_tbrel_diff(s, (void *)ofs);
1649
base = TCG_REG_ZERO;
1651
tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs);
1652
tcg_out_opc_reg(s, OPC_JR, 0, dest, 0);
1656
set_jmp_reset_offset(s, which);
1657
if (TCG_TARGET_REG_BITS == 64) {1658
/* For the unlinked case, need to reset TCG_REG_TB. */
1659
tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB,
1660
-tcg_current_code_size(s));
1664
void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1665
uintptr_t jmp_rx, uintptr_t jmp_rw)
1667
/* Always indirect, nothing to do */
1670
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1671
const TCGArg args[TCG_MAX_OP_ARGS],
1672
const int const_args[TCG_MAX_OP_ARGS])
1679
* Note that many operands use the constraint set "rZ".
1680
* We make use of the fact that 0 is the ZERO register,
1681
* and hence such cases need not check for const_args.
1689
case INDEX_op_goto_ptr:
1690
/* jmp to the given host address (could be epilogue) */
1691
tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
1692
if (TCG_TARGET_REG_BITS == 64) {1693
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
1699
tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO,
1703
case INDEX_op_ld8u_i32:
1704
case INDEX_op_ld8u_i64:
1707
case INDEX_op_ld8s_i32:
1708
case INDEX_op_ld8s_i64:
1711
case INDEX_op_ld16u_i32:
1712
case INDEX_op_ld16u_i64:
1715
case INDEX_op_ld16s_i32:
1716
case INDEX_op_ld16s_i64:
1719
case INDEX_op_ld_i32:
1720
case INDEX_op_ld32s_i64:
1723
case INDEX_op_ld32u_i64:
1726
case INDEX_op_ld_i64:
1729
case INDEX_op_st8_i32:
1730
case INDEX_op_st8_i64:
1733
case INDEX_op_st16_i32:
1734
case INDEX_op_st16_i64:
1737
case INDEX_op_st_i32:
1738
case INDEX_op_st32_i64:
1741
case INDEX_op_st_i64:
1744
tcg_out_ldst(s, i1, a0, a1, a2);
1747
case INDEX_op_add_i32:
1748
i1 = OPC_ADDU, i2 = OPC_ADDIU;
1750
case INDEX_op_add_i64:
1751
i1 = OPC_DADDU, i2 = OPC_DADDIU;
1753
case INDEX_op_or_i32:
1754
case INDEX_op_or_i64:
1755
i1 = OPC_OR, i2 = OPC_ORI;
1757
case INDEX_op_xor_i32:
1758
case INDEX_op_xor_i64:
1759
i1 = OPC_XOR, i2 = OPC_XORI;
1762
tcg_out_opc_imm(s, i2, a0, a1, a2);
1766
tcg_out_opc_reg(s, i1, a0, a1, a2);
1769
case INDEX_op_sub_i32:
1770
i1 = OPC_SUBU, i2 = OPC_ADDIU;
1772
case INDEX_op_sub_i64:
1773
i1 = OPC_DSUBU, i2 = OPC_DADDIU;
1776
tcg_out_opc_imm(s, i2, a0, a1, -a2);
1780
case INDEX_op_and_i32:
1781
if (c2 && a2 != (uint16_t)a2) {1782
int msb = ctz32(~a2) - 1;
1783
tcg_debug_assert(use_mips32r2_instructions);
1784
tcg_debug_assert(is_p2m1(a2));
1785
tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0);
1788
i1 = OPC_AND, i2 = OPC_ANDI;
1790
case INDEX_op_and_i64:
1791
if (c2 && a2 != (uint16_t)a2) {1792
int msb = ctz64(~a2) - 1;
1793
tcg_debug_assert(use_mips32r2_instructions);
1794
tcg_debug_assert(is_p2m1(a2));
1795
tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0);
1798
i1 = OPC_AND, i2 = OPC_ANDI;
1800
case INDEX_op_nor_i32:
1801
case INDEX_op_nor_i64:
1805
case INDEX_op_mul_i32:
1806
if (use_mips32_instructions) {1807
tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2);
1810
i1 = OPC_MULT, i2 = OPC_MFLO;
1812
case INDEX_op_mulsh_i32:
1813
if (use_mips32r6_instructions) {1814
tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2);
1817
i1 = OPC_MULT, i2 = OPC_MFHI;
1819
case INDEX_op_muluh_i32:
1820
if (use_mips32r6_instructions) {1821
tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2);
1824
i1 = OPC_MULTU, i2 = OPC_MFHI;
1826
case INDEX_op_div_i32:
1827
if (use_mips32r6_instructions) {1828
tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2);
1831
i1 = OPC_DIV, i2 = OPC_MFLO;
1833
case INDEX_op_divu_i32:
1834
if (use_mips32r6_instructions) {1835
tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2);
1838
i1 = OPC_DIVU, i2 = OPC_MFLO;
1840
case INDEX_op_rem_i32:
1841
if (use_mips32r6_instructions) {1842
tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2);
1845
i1 = OPC_DIV, i2 = OPC_MFHI;
1847
case INDEX_op_remu_i32:
1848
if (use_mips32r6_instructions) {1849
tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2);
1852
i1 = OPC_DIVU, i2 = OPC_MFHI;
1854
case INDEX_op_mul_i64:
1855
if (use_mips32r6_instructions) {1856
tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2);
1859
i1 = OPC_DMULT, i2 = OPC_MFLO;
1861
case INDEX_op_mulsh_i64:
1862
if (use_mips32r6_instructions) {1863
tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2);
1866
i1 = OPC_DMULT, i2 = OPC_MFHI;
1868
case INDEX_op_muluh_i64:
1869
if (use_mips32r6_instructions) {1870
tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2);
1873
i1 = OPC_DMULTU, i2 = OPC_MFHI;
1875
case INDEX_op_div_i64:
1876
if (use_mips32r6_instructions) {1877
tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2);
1880
i1 = OPC_DDIV, i2 = OPC_MFLO;
1882
case INDEX_op_divu_i64:
1883
if (use_mips32r6_instructions) {1884
tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2);
1887
i1 = OPC_DDIVU, i2 = OPC_MFLO;
1889
case INDEX_op_rem_i64:
1890
if (use_mips32r6_instructions) {1891
tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2);
1894
i1 = OPC_DDIV, i2 = OPC_MFHI;
1896
case INDEX_op_remu_i64:
1897
if (use_mips32r6_instructions) {1898
tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2);
1901
i1 = OPC_DDIVU, i2 = OPC_MFHI;
1903
tcg_out_opc_reg(s, i1, 0, a1, a2);
1904
tcg_out_opc_reg(s, i2, a0, 0, 0);
1907
case INDEX_op_muls2_i32:
1910
case INDEX_op_mulu2_i32:
1913
case INDEX_op_muls2_i64:
1916
case INDEX_op_mulu2_i64:
1919
tcg_out_opc_reg(s, i1, 0, a2, args[3]);
1920
tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0);
1921
tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0);
1924
case INDEX_op_neg_i32:
1927
case INDEX_op_neg_i64:
1930
case INDEX_op_not_i32:
1931
case INDEX_op_not_i64:
1935
tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1);
1938
case INDEX_op_bswap16_i32:
1939
case INDEX_op_bswap16_i64:
1940
tcg_out_bswap16(s, a0, a1, a2);
1942
case INDEX_op_bswap32_i32:
1943
tcg_out_bswap32(s, a0, a1, 0);
1945
case INDEX_op_bswap32_i64:
1946
tcg_out_bswap32(s, a0, a1, a2);
1948
case INDEX_op_bswap64_i64:
1949
tcg_out_bswap64(s, a0, a1);
1951
case INDEX_op_extrh_i64_i32:
1952
tcg_out_dsra(s, a0, a1, 32);
1955
case INDEX_op_sar_i32:
1956
i1 = OPC_SRAV, i2 = OPC_SRA;
1958
case INDEX_op_shl_i32:
1959
i1 = OPC_SLLV, i2 = OPC_SLL;
1961
case INDEX_op_shr_i32:
1962
i1 = OPC_SRLV, i2 = OPC_SRL;
1964
case INDEX_op_rotr_i32:
1965
i1 = OPC_ROTRV, i2 = OPC_ROTR;
1968
tcg_out_opc_sa(s, i2, a0, a1, a2);
1972
tcg_out_opc_reg(s, i1, a0, a2, a1);
1974
case INDEX_op_rotl_i32:
1976
tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2);
1978
tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2);
1979
tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1);
1982
case INDEX_op_sar_i64:
1984
tcg_out_dsra(s, a0, a1, a2);
1989
case INDEX_op_shl_i64:
1991
tcg_out_dsll(s, a0, a1, a2);
1996
case INDEX_op_shr_i64:
1998
tcg_out_dsrl(s, a0, a1, a2);
2003
case INDEX_op_rotr_i64:
2005
tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2);
2010
case INDEX_op_rotl_i64:
2012
tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2);
2014
tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2);
2015
tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1);
2019
case INDEX_op_clz_i32:
2020
tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2);
2022
case INDEX_op_clz_i64:
2023
tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2);
2026
case INDEX_op_deposit_i32:
2027
tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]);
2029
case INDEX_op_deposit_i64:
2030
tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2,
2031
args[3] + args[4] - 1, args[3]);
2033
case INDEX_op_extract_i32:
2034
tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2);
2036
case INDEX_op_extract_i64:
2037
tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1,
2041
case INDEX_op_brcond_i32:
2042
case INDEX_op_brcond_i64:
2043
tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
2045
case INDEX_op_brcond2_i32:
2046
tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5]));
2049
case INDEX_op_movcond_i32:
2050
case INDEX_op_movcond_i64:
2051
tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]);
2054
case INDEX_op_setcond_i32:
2055
case INDEX_op_setcond_i64:
2056
tcg_out_setcond(s, args[3], a0, a1, a2);
2058
case INDEX_op_setcond2_i32:
2059
tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]);
2062
case INDEX_op_qemu_ld_a64_i32:
2063
if (TCG_TARGET_REG_BITS == 32) {2064
tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
2068
case INDEX_op_qemu_ld_a32_i32:
2069
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
2071
case INDEX_op_qemu_ld_a32_i64:
2072
if (TCG_TARGET_REG_BITS == 64) {2073
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2075
tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
2078
case INDEX_op_qemu_ld_a64_i64:
2079
if (TCG_TARGET_REG_BITS == 64) {2080
tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2082
tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
2086
case INDEX_op_qemu_st_a64_i32:
2087
if (TCG_TARGET_REG_BITS == 32) {2088
tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32);
2092
case INDEX_op_qemu_st_a32_i32:
2093
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32);
2095
case INDEX_op_qemu_st_a32_i64:
2096
if (TCG_TARGET_REG_BITS == 64) {2097
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2099
tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64);
2102
case INDEX_op_qemu_st_a64_i64:
2103
if (TCG_TARGET_REG_BITS == 64) {2104
tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64);
2106
tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64);
2110
case INDEX_op_add2_i32:
2111
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2112
const_args[4], const_args[5], false);
2114
case INDEX_op_sub2_i32:
2115
tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5],
2116
const_args[4], const_args[5], true);
2122
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2123
case INDEX_op_mov_i64:
2124
case INDEX_op_call: /* Always emitted via tcg_out_call. */
2125
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
2126
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
2127
case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
2128
case INDEX_op_ext8s_i64:
2129
case INDEX_op_ext8u_i32:
2130
case INDEX_op_ext8u_i64:
2131
case INDEX_op_ext16s_i32:
2132
case INDEX_op_ext16s_i64:
2133
case INDEX_op_ext32s_i64:
2134
case INDEX_op_ext32u_i64:
2135
case INDEX_op_ext_i32_i64:
2136
case INDEX_op_extu_i32_i64:
2137
case INDEX_op_extrl_i64_i32:
2139
g_assert_not_reached();
2143
static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2146
case INDEX_op_goto_ptr:
2149
case INDEX_op_ld8u_i32:
2150
case INDEX_op_ld8s_i32:
2151
case INDEX_op_ld16u_i32:
2152
case INDEX_op_ld16s_i32:
2153
case INDEX_op_ld_i32:
2154
case INDEX_op_neg_i32:
2155
case INDEX_op_not_i32:
2156
case INDEX_op_bswap16_i32:
2157
case INDEX_op_bswap32_i32:
2158
case INDEX_op_ext8s_i32:
2159
case INDEX_op_ext16s_i32:
2160
case INDEX_op_extract_i32:
2161
case INDEX_op_ld8u_i64:
2162
case INDEX_op_ld8s_i64:
2163
case INDEX_op_ld16u_i64:
2164
case INDEX_op_ld16s_i64:
2165
case INDEX_op_ld32s_i64:
2166
case INDEX_op_ld32u_i64:
2167
case INDEX_op_ld_i64:
2168
case INDEX_op_neg_i64:
2169
case INDEX_op_not_i64:
2170
case INDEX_op_bswap16_i64:
2171
case INDEX_op_bswap32_i64:
2172
case INDEX_op_bswap64_i64:
2173
case INDEX_op_ext8s_i64:
2174
case INDEX_op_ext16s_i64:
2175
case INDEX_op_ext32s_i64:
2176
case INDEX_op_ext32u_i64:
2177
case INDEX_op_ext_i32_i64:
2178
case INDEX_op_extu_i32_i64:
2179
case INDEX_op_extrl_i64_i32:
2180
case INDEX_op_extrh_i64_i32:
2181
case INDEX_op_extract_i64:
2182
return C_O1_I1(r, r);
2184
case INDEX_op_st8_i32:
2185
case INDEX_op_st16_i32:
2186
case INDEX_op_st_i32:
2187
case INDEX_op_st8_i64:
2188
case INDEX_op_st16_i64:
2189
case INDEX_op_st32_i64:
2190
case INDEX_op_st_i64:
2191
return C_O0_I2(rZ, r);
2193
case INDEX_op_add_i32:
2194
case INDEX_op_add_i64:
2195
return C_O1_I2(r, r, rJ);
2196
case INDEX_op_sub_i32:
2197
case INDEX_op_sub_i64:
2198
return C_O1_I2(r, rZ, rN);
2199
case INDEX_op_mul_i32:
2200
case INDEX_op_mulsh_i32:
2201
case INDEX_op_muluh_i32:
2202
case INDEX_op_div_i32:
2203
case INDEX_op_divu_i32:
2204
case INDEX_op_rem_i32:
2205
case INDEX_op_remu_i32:
2206
case INDEX_op_nor_i32:
2207
case INDEX_op_setcond_i32:
2208
case INDEX_op_mul_i64:
2209
case INDEX_op_mulsh_i64:
2210
case INDEX_op_muluh_i64:
2211
case INDEX_op_div_i64:
2212
case INDEX_op_divu_i64:
2213
case INDEX_op_rem_i64:
2214
case INDEX_op_remu_i64:
2215
case INDEX_op_nor_i64:
2216
case INDEX_op_setcond_i64:
2217
return C_O1_I2(r, rZ, rZ);
2218
case INDEX_op_muls2_i32:
2219
case INDEX_op_mulu2_i32:
2220
case INDEX_op_muls2_i64:
2221
case INDEX_op_mulu2_i64:
2222
return C_O2_I2(r, r, r, r);
2223
case INDEX_op_and_i32:
2224
case INDEX_op_and_i64:
2225
return C_O1_I2(r, r, rIK);
2226
case INDEX_op_or_i32:
2227
case INDEX_op_xor_i32:
2228
case INDEX_op_or_i64:
2229
case INDEX_op_xor_i64:
2230
return C_O1_I2(r, r, rI);
2231
case INDEX_op_shl_i32:
2232
case INDEX_op_shr_i32:
2233
case INDEX_op_sar_i32:
2234
case INDEX_op_rotr_i32:
2235
case INDEX_op_rotl_i32:
2236
case INDEX_op_shl_i64:
2237
case INDEX_op_shr_i64:
2238
case INDEX_op_sar_i64:
2239
case INDEX_op_rotr_i64:
2240
case INDEX_op_rotl_i64:
2241
return C_O1_I2(r, r, ri);
2242
case INDEX_op_clz_i32:
2243
case INDEX_op_clz_i64:
2244
return C_O1_I2(r, r, rWZ);
2246
case INDEX_op_deposit_i32:
2247
case INDEX_op_deposit_i64:
2248
return C_O1_I2(r, 0, rZ);
2249
case INDEX_op_brcond_i32:
2250
case INDEX_op_brcond_i64:
2251
return C_O0_I2(rZ, rZ);
2252
case INDEX_op_movcond_i32:
2253
case INDEX_op_movcond_i64:
2254
return (use_mips32r6_instructions
2255
? C_O1_I4(r, rZ, rZ, rZ, rZ)
2256
: C_O1_I4(r, rZ, rZ, rZ, 0));
2257
case INDEX_op_add2_i32:
2258
case INDEX_op_sub2_i32:
2259
return C_O2_I4(r, r, rZ, rZ, rN, rN);
2260
case INDEX_op_setcond2_i32:
2261
return C_O1_I4(r, rZ, rZ, rZ, rZ);
2262
case INDEX_op_brcond2_i32:
2263
return C_O0_I4(rZ, rZ, rZ, rZ);
2265
case INDEX_op_qemu_ld_a32_i32:
2266
return C_O1_I1(r, r);
2267
case INDEX_op_qemu_ld_a64_i32:
2268
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r);
2269
case INDEX_op_qemu_st_a32_i32:
2270
return C_O0_I2(rZ, r);
2271
case INDEX_op_qemu_st_a64_i32:
2272
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r);
2273
case INDEX_op_qemu_ld_a32_i64:
2274
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r);
2275
case INDEX_op_qemu_ld_a64_i64:
2276
return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r);
2277
case INDEX_op_qemu_st_a32_i64:
2278
return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r);
2279
case INDEX_op_qemu_st_a64_i64:
2280
return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r)
2281
: C_O0_I4(rZ, rZ, r, r));
2284
g_assert_not_reached();
2288
static const int tcg_target_callee_save_regs[] = {2295
TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */
2296
TCG_REG_S7, /* used for guest_base */
2297
TCG_REG_S8, /* used for the global env (TCG_AREG0) */
2298
TCG_REG_RA, /* should be last for ABI compliance */
2301
/* The Linux kernel doesn't provide any information about the available
2302
instruction set. Probe it using a signal handler. */
2305
#ifndef use_movnz_instructions
2306
bool use_movnz_instructions = false;
2309
#ifndef use_mips32_instructions
2310
bool use_mips32_instructions = false;
2313
#ifndef use_mips32r2_instructions
2314
bool use_mips32r2_instructions = false;
2317
static volatile sig_atomic_t got_sigill;
2319
static void sigill_handler(int signo, siginfo_t *si, void *data)
2321
/* Skip the faulty instruction */
2322
ucontext_t *uc = (ucontext_t *)data;
2323
uc->uc_mcontext.pc += 4;
2328
static void tcg_target_detect_isa(void)
2330
struct sigaction sa_old, sa_new;
2332
memset(&sa_new, 0, sizeof(sa_new));
2333
sa_new.sa_flags = SA_SIGINFO;
2334
sa_new.sa_sigaction = sigill_handler;
2335
sigaction(SIGILL, &sa_new, &sa_old);
2337
/* Probe for movn/movz, necessary to implement movcond. */
2338
#ifndef use_movnz_instructions
2340
asm volatile(".set push\n"2342
"movn $zero, $zero, $zero\n"
2343
"movz $zero, $zero, $zero\n"
2346
use_movnz_instructions = !got_sigill;
2349
/* Probe for MIPS32 instructions. As no subsetting is allowed
2350
by the specification, it is only necessary to probe for one
2351
of the instructions. */
2352
#ifndef use_mips32_instructions
2354
asm volatile(".set push\n"2356
"mul $zero, $zero\n"
2359
use_mips32_instructions = !got_sigill;
2362
/* Probe for MIPS32r2 instructions if MIPS32 instructions are
2363
available. As no subsetting is allowed by the specification,
2364
it is only necessary to probe for one of the instructions. */
2365
#ifndef use_mips32r2_instructions
2366
if (use_mips32_instructions) {2368
asm volatile(".set push\n"2370
"seb $zero, $zero\n"
2373
use_mips32r2_instructions = !got_sigill;
2377
sigaction(SIGILL, &sa_old, NULL);
2380
static tcg_insn_unit *align_code_ptr(TCGContext *s)
2382
uintptr_t p = (uintptr_t)s->code_ptr;
2385
s->code_ptr = (void *)p;
2390
/* Stack frame parameters. */
2391
#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
2392
#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2393
#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2395
#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2396
+ TCG_TARGET_STACK_ALIGN - 1) \
2397
& -TCG_TARGET_STACK_ALIGN)
2398
#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2400
/* We're expecting to be able to use an immediate for frame allocation. */
2401
QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff);
2403
/* Generate global QEMU prologue and epilogue code */
2404
static void tcg_target_qemu_prologue(TCGContext *s)
2408
tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2411
tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2412
for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {2413
tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2414
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2417
if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) {2419
* The function call abi for n32 and n64 will have loaded $25 (t9)
2420
* with the address of the prologue, so we can use that instead
2423
#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls)
2424
# error "Unknown mips abi"
2426
tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base,
2427
TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0);
2428
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2431
if (TCG_TARGET_REG_BITS == 64) {2432
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
2435
/* Call generated code */
2436
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
2438
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2441
* Return path for goto_ptr. Set return value to 0, a-la exit_tb,
2442
* and fall through to the rest of the epilogue.
2444
tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2445
tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO);
2448
tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2449
for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {2450
tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2451
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2454
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2456
tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2458
if (use_mips32r2_instructions) {2462
/* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3;
2463
clobbers TCG_TMP1, TCG_TMP2. */
2466
* bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd.
2468
bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2469
/* t3 = (ssss)d000 */
2470
tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24);
2472
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24);
2474
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2476
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2478
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2480
tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2482
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2484
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2485
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2486
/* t3 = dcba -- delay slot */
2487
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2489
if (TCG_TARGET_REG_BITS == 32) {2494
* bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
2496
bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2497
/* t1 = (0000)000d */
2498
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff);
2500
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24);
2501
/* t1 = (0000)d000 */
2502
tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2504
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2506
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2508
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8);
2510
tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8);
2512
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2514
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2515
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2516
/* t3 = dcba -- delay slot */
2517
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2520
* bswap64 -- 64-bit swap. a0 = abcdefgh
2522
bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s));
2524
tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56);
2526
tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56);
2529
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00);
2531
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2533
tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40);
2535
tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2537
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2540
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2542
tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32);
2544
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2547
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00);
2549
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff);
2551
tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8);
2553
tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24);
2556
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2558
tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16);
2560
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2563
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff);
2565
tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00);
2567
tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40);
2569
tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24);
2572
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2);
2573
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
2574
/* t3 = hgfedcba -- delay slot */
2575
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
2578
static void tcg_out_tb_start(TCGContext *s)
2583
static void tcg_target_init(TCGContext *s)
2585
tcg_target_detect_isa();
2586
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
2587
if (TCG_TARGET_REG_BITS == 64) {2588
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
2591
tcg_target_call_clobber_regs = 0;
2592
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
2593
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
2594
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0);
2595
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1);
2596
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2);
2597
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3);
2598
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0);
2599
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1);
2600
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2);
2601
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3);
2602
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4);
2603
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5);
2604
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6);
2605
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7);
2606
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8);
2607
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9);
2609
s->reserved_regs = 0;
2610
tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */
2611
tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */
2612
tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */
2613
tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */
2614
tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */
2615
tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */
2616
tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */
2617
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
2618
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
2619
tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
2620
if (TCG_TARGET_REG_BITS == 64) {2621
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */
2627
uint8_t fde_def_cfa[4];
2628
uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2631
#define ELF_HOST_MACHINE EM_MIPS
2632
/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS,
2633
which is good because they're really quite complicated for MIPS. */
2635
static const DebugFrame debug_frame = {2636
.h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2639
.h.cie.code_align = 1,
2640
.h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2641
.h.cie.return_column = TCG_REG_RA,
2643
/* Total FDE size does not include the "len" member. */
2644
.h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2647
12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
2648
(FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2652
0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */
2653
0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */
2654
0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */
2655
0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */
2656
0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */
2657
0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */
2658
0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */
2659
0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */
2660
0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */
2664
void tcg_register_jit(const void *buf, size_t buf_size)
2666
tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));