qemu
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1/*
2* Emulation of Linux signals
3*
4* Copyright (c) 2003 Fabrice Bellard
5*
6* This program is free software; you can redistribute it and/or modify
7* it under the terms of the GNU General Public License as published by
8* the Free Software Foundation; either version 2 of the License, or
9* (at your option) any later version.
10*
11* This program is distributed in the hope that it will be useful,
12* but WITHOUT ANY WARRANTY; without even the implied warranty of
13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14* GNU General Public License for more details.
15*
16* You should have received a copy of the GNU General Public License
17* along with this program; if not, see <http://www.gnu.org/licenses/>.
18*/
19#include "qemu/osdep.h"
20#include "qemu.h"
21#include "user-internals.h"
22#include "signal-common.h"
23#include "linux-user/trace.h"
24#include "target/arm/cpu-features.h"
25
26struct target_sigcontext {
27uint64_t fault_address;
28/* AArch64 registers */
29uint64_t regs[31];
30uint64_t sp;
31uint64_t pc;
32uint64_t pstate;
33/* 4K reserved for FP/SIMD state and future expansion */
34char __reserved[4096] __attribute__((__aligned__(16)));
35};
36
37struct target_ucontext {
38abi_ulong tuc_flags;
39abi_ulong tuc_link;
40target_stack_t tuc_stack;
41target_sigset_t tuc_sigmask;
42/* glibc uses a 1024-bit sigset_t */
43char __unused[1024 / 8 - sizeof(target_sigset_t)];
44/* last for future expansion */
45struct target_sigcontext tuc_mcontext;
46};
47
48/*
49* Header to be used at the beginning of structures extending the user
50* context. Such structures must be placed after the rt_sigframe on the stack
51* and be 16-byte aligned. The last structure must be a dummy one with the
52* magic and size set to 0.
53*/
54struct target_aarch64_ctx {
55uint32_t magic;
56uint32_t size;
57};
58
59#define TARGET_FPSIMD_MAGIC 0x46508001
60
61struct target_fpsimd_context {
62struct target_aarch64_ctx head;
63uint32_t fpsr;
64uint32_t fpcr;
65uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */
66};
67
68#define TARGET_EXTRA_MAGIC 0x45585401
69
70struct target_extra_context {
71struct target_aarch64_ctx head;
72uint64_t datap; /* 16-byte aligned pointer to extra space cast to __u64 */
73uint32_t size; /* size in bytes of the extra space */
74uint32_t reserved[3];
75};
76
77#define TARGET_SVE_MAGIC 0x53564501
78
79struct target_sve_context {
80struct target_aarch64_ctx head;
81uint16_t vl;
82uint16_t flags;
83uint16_t reserved[2];
84/* The actual SVE data immediately follows. It is laid out
85* according to TARGET_SVE_SIG_{Z,P}REG_OFFSET, based off of
86* the original struct pointer.
87*/
88};
89
90#define TARGET_SVE_VQ_BYTES 16
91
92#define TARGET_SVE_SIG_ZREG_SIZE(VQ) ((VQ) * TARGET_SVE_VQ_BYTES)
93#define TARGET_SVE_SIG_PREG_SIZE(VQ) ((VQ) * (TARGET_SVE_VQ_BYTES / 8))
94
95#define TARGET_SVE_SIG_REGS_OFFSET \
96QEMU_ALIGN_UP(sizeof(struct target_sve_context), TARGET_SVE_VQ_BYTES)
97#define TARGET_SVE_SIG_ZREG_OFFSET(VQ, N) \
98(TARGET_SVE_SIG_REGS_OFFSET + TARGET_SVE_SIG_ZREG_SIZE(VQ) * (N))
99#define TARGET_SVE_SIG_PREG_OFFSET(VQ, N) \
100(TARGET_SVE_SIG_ZREG_OFFSET(VQ, 32) + TARGET_SVE_SIG_PREG_SIZE(VQ) * (N))
101#define TARGET_SVE_SIG_FFR_OFFSET(VQ) \
102(TARGET_SVE_SIG_PREG_OFFSET(VQ, 16))
103#define TARGET_SVE_SIG_CONTEXT_SIZE(VQ) \
104(TARGET_SVE_SIG_PREG_OFFSET(VQ, 17))
105
106#define TARGET_SVE_SIG_FLAG_SM 1
107
108#define TARGET_ZA_MAGIC 0x54366345
109
110struct target_za_context {
111struct target_aarch64_ctx head;
112uint16_t vl;
113uint16_t reserved[3];
114/* The actual ZA data immediately follows. */
115};
116
117#define TARGET_ZA_SIG_REGS_OFFSET \
118QEMU_ALIGN_UP(sizeof(struct target_za_context), TARGET_SVE_VQ_BYTES)
119#define TARGET_ZA_SIG_ZAV_OFFSET(VQ, N) \
120(TARGET_ZA_SIG_REGS_OFFSET + (VQ) * TARGET_SVE_VQ_BYTES * (N))
121#define TARGET_ZA_SIG_CONTEXT_SIZE(VQ) \
122TARGET_ZA_SIG_ZAV_OFFSET(VQ, VQ * TARGET_SVE_VQ_BYTES)
123
124struct target_rt_sigframe {
125struct target_siginfo info;
126struct target_ucontext uc;
127};
128
129struct target_rt_frame_record {
130uint64_t fp;
131uint64_t lr;
132};
133
134static void target_setup_general_frame(struct target_rt_sigframe *sf,
135CPUARMState *env, target_sigset_t *set)
136{
137int i;
138
139__put_user(0, &sf->uc.tuc_flags);
140__put_user(0, &sf->uc.tuc_link);
141
142target_save_altstack(&sf->uc.tuc_stack, env);
143
144for (i = 0; i < 31; i++) {
145__put_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]);
146}
147__put_user(env->xregs[31], &sf->uc.tuc_mcontext.sp);
148__put_user(env->pc, &sf->uc.tuc_mcontext.pc);
149__put_user(pstate_read(env), &sf->uc.tuc_mcontext.pstate);
150
151__put_user(env->exception.vaddress, &sf->uc.tuc_mcontext.fault_address);
152
153for (i = 0; i < TARGET_NSIG_WORDS; i++) {
154__put_user(set->sig[i], &sf->uc.tuc_sigmask.sig[i]);
155}
156}
157
158static void target_setup_fpsimd_record(struct target_fpsimd_context *fpsimd,
159CPUARMState *env)
160{
161int i;
162
163__put_user(TARGET_FPSIMD_MAGIC, &fpsimd->head.magic);
164__put_user(sizeof(struct target_fpsimd_context), &fpsimd->head.size);
165__put_user(vfp_get_fpsr(env), &fpsimd->fpsr);
166__put_user(vfp_get_fpcr(env), &fpsimd->fpcr);
167
168for (i = 0; i < 32; i++) {
169uint64_t *q = aa64_vfp_qreg(env, i);
170#if TARGET_BIG_ENDIAN
171__put_user(q[0], &fpsimd->vregs[i * 2 + 1]);
172__put_user(q[1], &fpsimd->vregs[i * 2]);
173#else
174__put_user(q[0], &fpsimd->vregs[i * 2]);
175__put_user(q[1], &fpsimd->vregs[i * 2 + 1]);
176#endif
177}
178}
179
180static void target_setup_extra_record(struct target_extra_context *extra,
181uint64_t datap, uint32_t extra_size)
182{
183__put_user(TARGET_EXTRA_MAGIC, &extra->head.magic);
184__put_user(sizeof(struct target_extra_context), &extra->head.size);
185__put_user(datap, &extra->datap);
186__put_user(extra_size, &extra->size);
187}
188
189static void target_setup_end_record(struct target_aarch64_ctx *end)
190{
191__put_user(0, &end->magic);
192__put_user(0, &end->size);
193}
194
195static void target_setup_sve_record(struct target_sve_context *sve,
196CPUARMState *env, int size)
197{
198int i, j, vq = sve_vq(env);
199
200memset(sve, 0, sizeof(*sve));
201__put_user(TARGET_SVE_MAGIC, &sve->head.magic);
202__put_user(size, &sve->head.size);
203__put_user(vq * TARGET_SVE_VQ_BYTES, &sve->vl);
204if (FIELD_EX64(env->svcr, SVCR, SM)) {
205__put_user(TARGET_SVE_SIG_FLAG_SM, &sve->flags);
206}
207
208/* Note that SVE regs are stored as a byte stream, with each byte element
209* at a subsequent address. This corresponds to a little-endian store
210* of our 64-bit hunks.
211*/
212for (i = 0; i < 32; ++i) {
213uint64_t *z = (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i);
214for (j = 0; j < vq * 2; ++j) {
215__put_user_e(env->vfp.zregs[i].d[j], z + j, le);
216}
217}
218for (i = 0; i <= 16; ++i) {
219uint16_t *p = (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i);
220for (j = 0; j < vq; ++j) {
221uint64_t r = env->vfp.pregs[i].p[j >> 2];
222__put_user_e(r >> ((j & 3) * 16), p + j, le);
223}
224}
225}
226
227static void target_setup_za_record(struct target_za_context *za,
228CPUARMState *env, int size)
229{
230int vq = sme_vq(env);
231int vl = vq * TARGET_SVE_VQ_BYTES;
232int i, j;
233
234memset(za, 0, sizeof(*za));
235__put_user(TARGET_ZA_MAGIC, &za->head.magic);
236__put_user(size, &za->head.size);
237__put_user(vl, &za->vl);
238
239if (size == TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
240return;
241}
242assert(size == TARGET_ZA_SIG_CONTEXT_SIZE(vq));
243
244/*
245* Note that ZA vectors are stored as a byte stream,
246* with each byte element at a subsequent address.
247*/
248for (i = 0; i < vl; ++i) {
249uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
250for (j = 0; j < vq * 2; ++j) {
251__put_user_e(env->zarray[i].d[j], z + j, le);
252}
253}
254}
255
256static void target_restore_general_frame(CPUARMState *env,
257struct target_rt_sigframe *sf)
258{
259sigset_t set;
260uint64_t pstate;
261int i;
262
263target_to_host_sigset(&set, &sf->uc.tuc_sigmask);
264set_sigmask(&set);
265
266for (i = 0; i < 31; i++) {
267__get_user(env->xregs[i], &sf->uc.tuc_mcontext.regs[i]);
268}
269
270__get_user(env->xregs[31], &sf->uc.tuc_mcontext.sp);
271__get_user(env->pc, &sf->uc.tuc_mcontext.pc);
272__get_user(pstate, &sf->uc.tuc_mcontext.pstate);
273pstate_write(env, pstate);
274}
275
276static void target_restore_fpsimd_record(CPUARMState *env,
277struct target_fpsimd_context *fpsimd)
278{
279uint32_t fpsr, fpcr;
280int i;
281
282__get_user(fpsr, &fpsimd->fpsr);
283vfp_set_fpsr(env, fpsr);
284__get_user(fpcr, &fpsimd->fpcr);
285vfp_set_fpcr(env, fpcr);
286
287for (i = 0; i < 32; i++) {
288uint64_t *q = aa64_vfp_qreg(env, i);
289#if TARGET_BIG_ENDIAN
290__get_user(q[0], &fpsimd->vregs[i * 2 + 1]);
291__get_user(q[1], &fpsimd->vregs[i * 2]);
292#else
293__get_user(q[0], &fpsimd->vregs[i * 2]);
294__get_user(q[1], &fpsimd->vregs[i * 2 + 1]);
295#endif
296}
297}
298
299static bool target_restore_sve_record(CPUARMState *env,
300struct target_sve_context *sve,
301int size, int *svcr)
302{
303int i, j, vl, vq, flags;
304bool sm;
305
306__get_user(vl, &sve->vl);
307__get_user(flags, &sve->flags);
308
309sm = flags & TARGET_SVE_SIG_FLAG_SM;
310
311/* The cpu must support Streaming or Non-streaming SVE. */
312if (sm
313? !cpu_isar_feature(aa64_sme, env_archcpu(env))
314: !cpu_isar_feature(aa64_sve, env_archcpu(env))) {
315return false;
316}
317
318/*
319* Note that we cannot use sve_vq() because that depends on the
320* current setting of PSTATE.SM, not the state to be restored.
321*/
322vq = sve_vqm1_for_el_sm(env, 0, sm) + 1;
323
324/* Reject mismatched VL. */
325if (vl != vq * TARGET_SVE_VQ_BYTES) {
326return false;
327}
328
329/* Accept empty record -- used to clear PSTATE.SM. */
330if (size <= sizeof(*sve)) {
331return true;
332}
333
334/* Reject non-empty but incomplete record. */
335if (size < TARGET_SVE_SIG_CONTEXT_SIZE(vq)) {
336return false;
337}
338
339*svcr = FIELD_DP64(*svcr, SVCR, SM, sm);
340
341/*
342* Note that SVE regs are stored as a byte stream, with each byte element
343* at a subsequent address. This corresponds to a little-endian load
344* of our 64-bit hunks.
345*/
346for (i = 0; i < 32; ++i) {
347uint64_t *z = (void *)sve + TARGET_SVE_SIG_ZREG_OFFSET(vq, i);
348for (j = 0; j < vq * 2; ++j) {
349__get_user_e(env->vfp.zregs[i].d[j], z + j, le);
350}
351}
352for (i = 0; i <= 16; ++i) {
353uint16_t *p = (void *)sve + TARGET_SVE_SIG_PREG_OFFSET(vq, i);
354for (j = 0; j < vq; ++j) {
355uint16_t r;
356__get_user_e(r, p + j, le);
357if (j & 3) {
358env->vfp.pregs[i].p[j >> 2] |= (uint64_t)r << ((j & 3) * 16);
359} else {
360env->vfp.pregs[i].p[j >> 2] = r;
361}
362}
363}
364return true;
365}
366
367static bool target_restore_za_record(CPUARMState *env,
368struct target_za_context *za,
369int size, int *svcr)
370{
371int i, j, vl, vq;
372
373if (!cpu_isar_feature(aa64_sme, env_archcpu(env))) {
374return false;
375}
376
377__get_user(vl, &za->vl);
378vq = sme_vq(env);
379
380/* Reject mismatched VL. */
381if (vl != vq * TARGET_SVE_VQ_BYTES) {
382return false;
383}
384
385/* Accept empty record -- used to clear PSTATE.ZA. */
386if (size <= TARGET_ZA_SIG_CONTEXT_SIZE(0)) {
387return true;
388}
389
390/* Reject non-empty but incomplete record. */
391if (size < TARGET_ZA_SIG_CONTEXT_SIZE(vq)) {
392return false;
393}
394
395*svcr = FIELD_DP64(*svcr, SVCR, ZA, 1);
396
397for (i = 0; i < vl; ++i) {
398uint64_t *z = (void *)za + TARGET_ZA_SIG_ZAV_OFFSET(vq, i);
399for (j = 0; j < vq * 2; ++j) {
400__get_user_e(env->zarray[i].d[j], z + j, le);
401}
402}
403return true;
404}
405
406static int target_restore_sigframe(CPUARMState *env,
407struct target_rt_sigframe *sf)
408{
409struct target_aarch64_ctx *ctx, *extra = NULL;
410struct target_fpsimd_context *fpsimd = NULL;
411struct target_sve_context *sve = NULL;
412struct target_za_context *za = NULL;
413uint64_t extra_datap = 0;
414bool used_extra = false;
415int sve_size = 0;
416int za_size = 0;
417int svcr = 0;
418
419target_restore_general_frame(env, sf);
420
421ctx = (struct target_aarch64_ctx *)sf->uc.tuc_mcontext.__reserved;
422while (ctx) {
423uint32_t magic, size, extra_size;
424
425__get_user(magic, &ctx->magic);
426__get_user(size, &ctx->size);
427switch (magic) {
428case 0:
429if (size != 0) {
430goto err;
431}
432if (used_extra) {
433ctx = NULL;
434} else {
435ctx = extra;
436used_extra = true;
437}
438continue;
439
440case TARGET_FPSIMD_MAGIC:
441if (fpsimd || size != sizeof(struct target_fpsimd_context)) {
442goto err;
443}
444fpsimd = (struct target_fpsimd_context *)ctx;
445break;
446
447case TARGET_SVE_MAGIC:
448if (sve || size < sizeof(struct target_sve_context)) {
449goto err;
450}
451sve = (struct target_sve_context *)ctx;
452sve_size = size;
453break;
454
455case TARGET_ZA_MAGIC:
456if (za || size < sizeof(struct target_za_context)) {
457goto err;
458}
459za = (struct target_za_context *)ctx;
460za_size = size;
461break;
462
463case TARGET_EXTRA_MAGIC:
464if (extra || size != sizeof(struct target_extra_context)) {
465goto err;
466}
467__get_user(extra_datap,
468&((struct target_extra_context *)ctx)->datap);
469__get_user(extra_size,
470&((struct target_extra_context *)ctx)->size);
471extra = lock_user(VERIFY_READ, extra_datap, extra_size, 0);
472if (!extra) {
473return 1;
474}
475break;
476
477default:
478/* Unknown record -- we certainly didn't generate it.
479* Did we in fact get out of sync?
480*/
481goto err;
482}
483ctx = (void *)ctx + size;
484}
485
486/* Require FPSIMD always. */
487if (fpsimd) {
488target_restore_fpsimd_record(env, fpsimd);
489} else {
490goto err;
491}
492
493/* SVE data, if present, overwrites FPSIMD data. */
494if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) {
495goto err;
496}
497if (za && !target_restore_za_record(env, za, za_size, &svcr)) {
498goto err;
499}
500if (env->svcr != svcr) {
501env->svcr = svcr;
502arm_rebuild_hflags(env);
503}
504unlock_user(extra, extra_datap, 0);
505return 0;
506
507err:
508unlock_user(extra, extra_datap, 0);
509return 1;
510}
511
512static abi_ulong get_sigframe(struct target_sigaction *ka,
513CPUARMState *env, int size)
514{
515abi_ulong sp;
516
517sp = target_sigsp(get_sp_from_cpustate(env), ka);
518
519sp = (sp - size) & ~15;
520
521return sp;
522}
523
524typedef struct {
525int total_size;
526int extra_base;
527int extra_size;
528int std_end_ofs;
529int extra_ofs;
530int extra_end_ofs;
531} target_sigframe_layout;
532
533static int alloc_sigframe_space(int this_size, target_sigframe_layout *l)
534{
535/* Make sure there will always be space for the end marker. */
536const int std_size = sizeof(struct target_rt_sigframe)
537- sizeof(struct target_aarch64_ctx);
538int this_loc = l->total_size;
539
540if (l->extra_base) {
541/* Once we have begun an extra space, all allocations go there. */
542l->extra_size += this_size;
543} else if (this_size + this_loc > std_size) {
544/* This allocation does not fit in the standard space. */
545/* Allocate the extra record. */
546l->extra_ofs = this_loc;
547l->total_size += sizeof(struct target_extra_context);
548
549/* Allocate the standard end record. */
550l->std_end_ofs = l->total_size;
551l->total_size += sizeof(struct target_aarch64_ctx);
552
553/* Allocate the requested record. */
554l->extra_base = this_loc = l->total_size;
555l->extra_size = this_size;
556}
557l->total_size += this_size;
558
559return this_loc;
560}
561
562static void target_setup_frame(int usig, struct target_sigaction *ka,
563target_siginfo_t *info, target_sigset_t *set,
564CPUARMState *env)
565{
566target_sigframe_layout layout = {
567/* Begin with the size pointing to the reserved space. */
568.total_size = offsetof(struct target_rt_sigframe,
569uc.tuc_mcontext.__reserved),
570};
571int fpsimd_ofs, fr_ofs, sve_ofs = 0, za_ofs = 0;
572int sve_size = 0, za_size = 0;
573struct target_rt_sigframe *frame;
574struct target_rt_frame_record *fr;
575abi_ulong frame_addr, return_addr;
576
577/* FPSIMD record is always in the standard space. */
578fpsimd_ofs = alloc_sigframe_space(sizeof(struct target_fpsimd_context),
579&layout);
580
581/* SVE state needs saving only if it exists. */
582if (cpu_isar_feature(aa64_sve, env_archcpu(env)) ||
583cpu_isar_feature(aa64_sme, env_archcpu(env))) {
584sve_size = QEMU_ALIGN_UP(TARGET_SVE_SIG_CONTEXT_SIZE(sve_vq(env)), 16);
585sve_ofs = alloc_sigframe_space(sve_size, &layout);
586}
587if (cpu_isar_feature(aa64_sme, env_archcpu(env))) {
588/* ZA state needs saving only if it is enabled. */
589if (FIELD_EX64(env->svcr, SVCR, ZA)) {
590za_size = TARGET_ZA_SIG_CONTEXT_SIZE(sme_vq(env));
591} else {
592za_size = TARGET_ZA_SIG_CONTEXT_SIZE(0);
593}
594za_ofs = alloc_sigframe_space(za_size, &layout);
595}
596
597if (layout.extra_ofs) {
598/* Reserve space for the extra end marker. The standard end marker
599* will have been allocated when we allocated the extra record.
600*/
601layout.extra_end_ofs
602= alloc_sigframe_space(sizeof(struct target_aarch64_ctx), &layout);
603} else {
604/* Reserve space for the standard end marker.
605* Do not use alloc_sigframe_space because we cheat
606* std_size therein to reserve space for this.
607*/
608layout.std_end_ofs = layout.total_size;
609layout.total_size += sizeof(struct target_aarch64_ctx);
610}
611
612/* We must always provide at least the standard 4K reserved space,
613* even if we don't use all of it (this is part of the ABI)
614*/
615layout.total_size = MAX(layout.total_size,
616sizeof(struct target_rt_sigframe));
617
618/*
619* Reserve space for the standard frame unwind pair: fp, lr.
620* Despite the name this is not a "real" record within the frame.
621*/
622fr_ofs = layout.total_size;
623layout.total_size += sizeof(struct target_rt_frame_record);
624
625frame_addr = get_sigframe(ka, env, layout.total_size);
626trace_user_setup_frame(env, frame_addr);
627frame = lock_user(VERIFY_WRITE, frame_addr, layout.total_size, 0);
628if (!frame) {
629goto give_sigsegv;
630}
631
632target_setup_general_frame(frame, env, set);
633target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env);
634target_setup_end_record((void *)frame + layout.std_end_ofs);
635if (layout.extra_ofs) {
636target_setup_extra_record((void *)frame + layout.extra_ofs,
637frame_addr + layout.extra_base,
638layout.extra_size);
639target_setup_end_record((void *)frame + layout.extra_end_ofs);
640}
641if (sve_ofs) {
642target_setup_sve_record((void *)frame + sve_ofs, env, sve_size);
643}
644if (za_ofs) {
645target_setup_za_record((void *)frame + za_ofs, env, za_size);
646}
647
648/* Set up the stack frame for unwinding. */
649fr = (void *)frame + fr_ofs;
650__put_user(env->xregs[29], &fr->fp);
651__put_user(env->xregs[30], &fr->lr);
652
653if (ka->sa_flags & TARGET_SA_RESTORER) {
654return_addr = ka->sa_restorer;
655} else {
656return_addr = default_rt_sigreturn;
657}
658env->xregs[0] = usig;
659env->xregs[29] = frame_addr + fr_ofs;
660env->xregs[30] = return_addr;
661env->xregs[31] = frame_addr;
662env->pc = ka->_sa_handler;
663
664/* Invoke the signal handler as if by indirect call. */
665if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
666env->btype = 2;
667}
668
669/* Invoke the signal handler with both SM and ZA disabled. */
670aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK);
671
672if (info) {
673frame->info = *info;
674env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info);
675env->xregs[2] = frame_addr + offsetof(struct target_rt_sigframe, uc);
676}
677
678unlock_user(frame, frame_addr, layout.total_size);
679return;
680
681give_sigsegv:
682unlock_user(frame, frame_addr, layout.total_size);
683force_sigsegv(usig);
684}
685
686void setup_rt_frame(int sig, struct target_sigaction *ka,
687target_siginfo_t *info, target_sigset_t *set,
688CPUARMState *env)
689{
690target_setup_frame(sig, ka, info, set, env);
691}
692
693void setup_frame(int sig, struct target_sigaction *ka,
694target_sigset_t *set, CPUARMState *env)
695{
696target_setup_frame(sig, ka, 0, set, env);
697}
698
699long do_rt_sigreturn(CPUARMState *env)
700{
701struct target_rt_sigframe *frame = NULL;
702abi_ulong frame_addr = env->xregs[31];
703
704trace_user_do_rt_sigreturn(env, frame_addr);
705if (frame_addr & 15) {
706goto badframe;
707}
708
709if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) {
710goto badframe;
711}
712
713if (target_restore_sigframe(env, frame)) {
714goto badframe;
715}
716
717target_restore_altstack(&frame->uc.tuc_stack, env);
718
719unlock_user_struct(frame, frame_addr, 0);
720return -QEMU_ESIGRETURN;
721
722badframe:
723unlock_user_struct(frame, frame_addr, 0);
724force_sig(TARGET_SIGSEGV);
725return -QEMU_ESIGRETURN;
726}
727
728long do_sigreturn(CPUARMState *env)
729{
730return do_rt_sigreturn(env);
731}
732
733void setup_sigtramp(abi_ulong sigtramp_page)
734{
735uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 8, 0);
736assert(tramp != NULL);
737
738/*
739* mov x8,#__NR_rt_sigreturn; svc #0
740* Since these are instructions they need to be put as little-endian
741* regardless of target default or current CPU endianness.
742*/
743__put_user_e(0xd2801168, &tramp[0], le);
744__put_user_e(0xd4000001, &tramp[1], le);
745
746default_rt_sigreturn = sigtramp_page;
747unlock_user(tramp, sigtramp_page, 8);
748}
749