qemu

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/*
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 *  qemu user cpu loop
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 *
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 *  Copyright (c) 2003-2008 Fabrice Bellard
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 *
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 *  This program is free software; you can redistribute it and/or modify
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 *  it under the terms of the GNU General Public License as published by
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 *  the Free Software Foundation; either version 2 of the License, or
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 *  (at your option) any later version.
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 *
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 *  This program is distributed in the hope that it will be useful,
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 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
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 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 *  GNU General Public License for more details.
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 *
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 *  You should have received a copy of the GNU General Public License
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 *  along with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "user-internals.h"
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#include "cpu_loop-common.h"
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#include "signal-common.h"
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#include "qemu/guest-random.h"
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#include "semihosting/common-semi.h"
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#include "target/arm/syndrome.h"
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#include "target/arm/cpu-features.h"
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#define get_user_code_u32(x, gaddr, env)                \
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    ({ abi_long __r = get_user_u32((x), (gaddr));       \
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        if (!__r && bswap_code(arm_sctlr_b(env))) {     \
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            (x) = bswap32(x);                           \
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        }                                               \
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        __r;                                            \
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    })
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#define get_user_code_u16(x, gaddr, env)                \
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    ({ abi_long __r = get_user_u16((x), (gaddr));       \
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        if (!__r && bswap_code(arm_sctlr_b(env))) {     \
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            (x) = bswap16(x);                           \
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        }                                               \
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        __r;                                            \
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    })
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#define get_user_data_u32(x, gaddr, env)                \
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    ({ abi_long __r = get_user_u32((x), (gaddr));       \
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        if (!__r && arm_cpu_bswap_data(env)) {          \
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            (x) = bswap32(x);                           \
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        }                                               \
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        __r;                                            \
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    })
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#define get_user_data_u16(x, gaddr, env)                \
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    ({ abi_long __r = get_user_u16((x), (gaddr));       \
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        if (!__r && arm_cpu_bswap_data(env)) {          \
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            (x) = bswap16(x);                           \
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        }                                               \
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        __r;                                            \
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    })
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#define put_user_data_u32(x, gaddr, env)                \
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    ({ typeof(x) __x = (x);                             \
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        if (arm_cpu_bswap_data(env)) {                  \
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            __x = bswap32(__x);                         \
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        }                                               \
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        put_user_u32(__x, (gaddr));                     \
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    })
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#define put_user_data_u16(x, gaddr, env)                \
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    ({ typeof(x) __x = (x);                             \
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        if (arm_cpu_bswap_data(env)) {                  \
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            __x = bswap16(__x);                         \
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        }                                               \
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        put_user_u16(__x, (gaddr));                     \
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    })
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/* AArch64 main loop */
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void cpu_loop(CPUARMState *env)
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{
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    CPUState *cs = env_cpu(env);
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    int trapnr, ec, fsc, si_code, si_signo;
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    abi_long ret;
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    for (;;) {
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        cpu_exec_start(cs);
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        trapnr = cpu_exec(cs);
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        cpu_exec_end(cs);
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        process_queued_cpu_work(cs);
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        switch (trapnr) {
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        case EXCP_SWI:
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            /* On syscall, PSTATE.ZA is preserved, PSTATE.SM is cleared. */
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            aarch64_set_svcr(env, 0, R_SVCR_SM_MASK);
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            ret = do_syscall(env,
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                             env->xregs[8],
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                             env->xregs[0],
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                             env->xregs[1],
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                             env->xregs[2],
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                             env->xregs[3],
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                             env->xregs[4],
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                             env->xregs[5],
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                             0, 0);
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            if (ret == -QEMU_ERESTARTSYS) {
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                env->pc -= 4;
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            } else if (ret != -QEMU_ESIGRETURN) {
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                env->xregs[0] = ret;
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            }
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            break;
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        case EXCP_INTERRUPT:
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            /* just indicate that signals should be handled asap */
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            break;
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        case EXCP_UDEF:
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            force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
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            break;
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        case EXCP_PREFETCH_ABORT:
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        case EXCP_DATA_ABORT:
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            ec = syn_get_ec(env->exception.syndrome);
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            switch (ec) {
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            case EC_DATAABORT:
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            case EC_INSNABORT:
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                /* Both EC have the same format for FSC, or close enough. */
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                fsc = extract32(env->exception.syndrome, 0, 6);
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                switch (fsc) {
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                case 0x04 ... 0x07: /* Translation fault, level {0-3} */
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                    si_signo = TARGET_SIGSEGV;
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                    si_code = TARGET_SEGV_MAPERR;
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                    break;
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                case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
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                case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
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                    si_signo = TARGET_SIGSEGV;
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                    si_code = TARGET_SEGV_ACCERR;
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                    break;
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                case 0x11: /* Synchronous Tag Check Fault */
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                    si_signo = TARGET_SIGSEGV;
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                    si_code = TARGET_SEGV_MTESERR;
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                    break;
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                case 0x21: /* Alignment fault */
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                    si_signo = TARGET_SIGBUS;
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                    si_code = TARGET_BUS_ADRALN;
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                    break;
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                default:
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                    g_assert_not_reached();
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                }
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                break;
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            case EC_PCALIGNMENT:
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                si_signo = TARGET_SIGBUS;
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                si_code = TARGET_BUS_ADRALN;
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                break;
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            default:
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                g_assert_not_reached();
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            }
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            force_sig_fault(si_signo, si_code, env->exception.vaddress);
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            break;
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        case EXCP_DEBUG:
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        case EXCP_BKPT:
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            force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
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            break;
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        case EXCP_SEMIHOST:
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            do_common_semihosting(cs);
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            env->pc += 4;
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            break;
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        case EXCP_YIELD:
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            /* nothing to do here for user-mode, just resume guest code */
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            break;
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        case EXCP_ATOMIC:
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            cpu_exec_step_atomic(cs);
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            break;
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        default:
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            EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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            abort();
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        }
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        /* Check for MTE asynchronous faults */
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        if (unlikely(env->cp15.tfsr_el[0])) {
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            env->cp15.tfsr_el[0] = 0;
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            force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0);
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        }
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        process_pending_signals(env);
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        /* Exception return on AArch64 always clears the exclusive monitor,
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         * so any return to running guest code implies this.
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         */
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        env->exclusive_addr = -1;
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    }
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}
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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    ARMCPU *cpu = env_archcpu(env);
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    CPUState *cs = env_cpu(env);
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    TaskState *ts = get_task_state(cs);
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    struct image_info *info = ts->info;
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    int i;
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    if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
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        fprintf(stderr,
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                "The selected ARM CPU does not support 64 bit mode\n");
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        exit(EXIT_FAILURE);
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    }
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    for (i = 0; i < 31; i++) {
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        env->xregs[i] = regs->regs[i];
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    }
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    env->pc = regs->pc;
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    env->xregs[31] = regs->sp;
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#if TARGET_BIG_ENDIAN
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    env->cp15.sctlr_el[1] |= SCTLR_E0E;
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    for (i = 1; i < 4; ++i) {
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        env->cp15.sctlr_el[i] |= SCTLR_EE;
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    }
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    arm_rebuild_hflags(env);
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#endif
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    if (cpu_isar_feature(aa64_pauth, cpu)) {
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        qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys));
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    }
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    ts->stack_base = info->start_stack;
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    ts->heap_base = info->brk;
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    /* This will be filled in on the first SYS_HEAPINFO call.  */
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    ts->heap_limit = 0;
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}
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