2
* USB xHCI controller emulation
4
* Copyright (c) 2011 Securiforest
5
* Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6
* Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8
* This library is free software; you can redistribute it and/or
9
* modify it under the terms of the GNU Lesser General Public
10
* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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* This library is distributed in the hope that it will be useful,
14
* but WITHOUT ANY WARRANTY; without even the implied warranty of
15
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16
* Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
22
#include "qemu/osdep.h"
23
#include "qemu/timer.h"
25
#include "qemu/module.h"
26
#include "qemu/queue.h"
27
#include "migration/vmstate.h"
28
#include "hw/qdev-properties.h"
30
#include "qapi/error.h"
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#define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
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#define DPRINTF(...) do {} while (0)42
#define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \43
__func__, __LINE__, _msg); abort(); } while (0)
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#define TRB_LINK_LIMIT 32
46
#define COMMAND_LIMIT 256
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#define TRANSFER_LIMIT 256
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#define LEN_OPER (0x400 + 0x10 * XHCI_MAXPORTS)
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#define LEN_RUNTIME ((XHCI_MAXINTRS + 1) * 0x20)
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#define LEN_DOORBELL ((XHCI_MAXSLOTS + 1) * 0x20)
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#define OFF_OPER LEN_CAP
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#define OFF_RUNTIME 0x1000
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#define OFF_DOORBELL 0x2000
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#if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
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#error Increase OFF_RUNTIME
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#if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
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#error Increase OFF_DOORBELL
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#if (OFF_DOORBELL + LEN_DOORBELL) > XHCI_LEN_REGS
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# error Increase XHCI_LEN_REGS
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#define USBCMD_RS (1<<0)
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#define USBCMD_HCRST (1<<1)
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#define USBCMD_INTE (1<<2)
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#define USBCMD_HSEE (1<<3)
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#define USBCMD_LHCRST (1<<7)
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#define USBCMD_CSS (1<<8)
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#define USBCMD_CRS (1<<9)
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#define USBCMD_EWE (1<<10)
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#define USBCMD_EU3S (1<<11)
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#define USBSTS_HCH (1<<0)
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#define USBSTS_HSE (1<<2)
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#define USBSTS_EINT (1<<3)
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#define USBSTS_PCD (1<<4)
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#define USBSTS_SSS (1<<8)
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#define USBSTS_RSS (1<<9)
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#define USBSTS_SRE (1<<10)
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#define USBSTS_CNR (1<<11)
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#define USBSTS_HCE (1<<12)
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#define PORTSC_CCS (1<<0)
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#define PORTSC_PED (1<<1)
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#define PORTSC_OCA (1<<3)
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#define PORTSC_PR (1<<4)
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#define PORTSC_PLS_SHIFT 5
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#define PORTSC_PLS_MASK 0xf
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#define PORTSC_PP (1<<9)
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#define PORTSC_SPEED_SHIFT 10
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#define PORTSC_SPEED_MASK 0xf
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#define PORTSC_SPEED_FULL (1<<10)
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#define PORTSC_SPEED_LOW (2<<10)
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#define PORTSC_SPEED_HIGH (3<<10)
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#define PORTSC_SPEED_SUPER (4<<10)
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#define PORTSC_PIC_SHIFT 14
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#define PORTSC_PIC_MASK 0x3
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#define PORTSC_LWS (1<<16)
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#define PORTSC_CSC (1<<17)
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#define PORTSC_PEC (1<<18)
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#define PORTSC_WRC (1<<19)
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#define PORTSC_OCC (1<<20)
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#define PORTSC_PRC (1<<21)
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#define PORTSC_PLC (1<<22)
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#define PORTSC_CEC (1<<23)
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#define PORTSC_CAS (1<<24)
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#define PORTSC_WCE (1<<25)
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#define PORTSC_WDE (1<<26)
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#define PORTSC_WOE (1<<27)
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#define PORTSC_DR (1<<30)
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#define PORTSC_WPR (1<<31)
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#define CRCR_RCS (1<<0)
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#define CRCR_CS (1<<1)
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#define CRCR_CA (1<<2)
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#define CRCR_CRR (1<<3)
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#define IMAN_IP (1<<0)
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#define IMAN_IE (1<<1)
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#define ERDP_EHB (1<<3)
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typedef struct XHCITRB {150
PLS_COMPILANCE_MODE = 10,
155
#define CR_LINK TR_LINK
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#define TRB_TYPE_SHIFT 10
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#define TRB_TYPE_MASK 0x3f
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#define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
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#define TRB_EV_ED (1<<2)
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#define TRB_TR_ENT (1<<1)
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#define TRB_TR_ISP (1<<2)
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#define TRB_TR_NS (1<<3)
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#define TRB_TR_CH (1<<4)
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#define TRB_TR_IOC (1<<5)
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#define TRB_TR_IDT (1<<6)
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#define TRB_TR_TBC_SHIFT 7
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#define TRB_TR_TBC_MASK 0x3
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#define TRB_TR_BEI (1<<9)
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#define TRB_TR_TLBPC_SHIFT 16
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#define TRB_TR_TLBPC_MASK 0xf
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#define TRB_TR_FRAMEID_SHIFT 20
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#define TRB_TR_FRAMEID_MASK 0x7ff
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#define TRB_TR_SIA (1<<31)
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#define TRB_TR_DIR (1<<16)
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#define TRB_CR_SLOTID_SHIFT 24
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#define TRB_CR_SLOTID_MASK 0xff
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#define TRB_CR_EPID_SHIFT 16
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#define TRB_CR_EPID_MASK 0x1f
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#define TRB_CR_BSR (1<<9)
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#define TRB_CR_DC (1<<9)
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#define TRB_LK_TC (1<<1)
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#define TRB_INTR_SHIFT 22
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#define TRB_INTR_MASK 0x3ff
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#define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
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#define EP_TYPE_MASK 0x7
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#define EP_TYPE_SHIFT 3
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#define EP_STATE_MASK 0x7
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#define EP_DISABLED (0<<0)
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#define EP_RUNNING (1<<0)
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#define EP_HALTED (2<<0)
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#define EP_STOPPED (3<<0)
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#define EP_ERROR (4<<0)
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#define SLOT_STATE_MASK 0x1f
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#define SLOT_STATE_SHIFT 27
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#define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
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#define SLOT_ENABLED 0
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#define SLOT_DEFAULT 1
210
#define SLOT_ADDRESSED 2
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#define SLOT_CONFIGURED 3
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#define SLOT_CONTEXT_ENTRIES_MASK 0x1f
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#define SLOT_CONTEXT_ENTRIES_SHIFT 27
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#define get_field(data, field) \
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(((data) >> field##_SHIFT) & field##_MASK)
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#define set_field(data, newval, field) do { \220
uint32_t val_ = *data; \
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val_ &= ~(field##_MASK << field##_SHIFT); \
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val_ |= ((newval) & field##_MASK) << field##_SHIFT; \
237
typedef struct XHCITransfer {238
XHCIEPContext *epctx;
245
unsigned int iso_pkts;
246
unsigned int streamid;
251
unsigned int trb_count;
257
unsigned int pktsize;
258
unsigned int cur_pkt;
260
uint64_t mfindex_kick;
262
QTAILQ_ENTRY(XHCITransfer) next;
265
struct XHCIStreamContext {271
struct XHCIEPContext {278
QTAILQ_HEAD(, XHCITransfer) transfers;
282
unsigned int max_psize;
284
uint32_t kick_active;
287
unsigned int max_pstreams;
289
unsigned int nr_pstreams;
290
XHCIStreamContext *pstreams;
292
/* iso xfer scheduling */
293
unsigned int interval;
294
int64_t mfindex_last;
295
QEMUTimer *kick_timer;
298
typedef struct XHCIEvRingSeg {305
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
306
unsigned int epid, unsigned int streamid);
307
static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid);
308
static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
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static void xhci_xfer_report(XHCITransfer *xfer);
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static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
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static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
313
static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx);
315
static const char *TRBType_names[] = {316
[TRB_RESERVED] = "TRB_RESERVED",
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[TR_NORMAL] = "TR_NORMAL",
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[TR_SETUP] = "TR_SETUP",
319
[TR_DATA] = "TR_DATA",
320
[TR_STATUS] = "TR_STATUS",
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[TR_ISOCH] = "TR_ISOCH",
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[TR_LINK] = "TR_LINK",
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[TR_EVDATA] = "TR_EVDATA",
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[TR_NOOP] = "TR_NOOP",
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[CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
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[CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
327
[CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
328
[CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
329
[CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
330
[CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
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[CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
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[CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
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[CR_RESET_DEVICE] = "CR_RESET_DEVICE",
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[CR_FORCE_EVENT] = "CR_FORCE_EVENT",
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[CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
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[CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
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[CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
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[CR_FORCE_HEADER] = "CR_FORCE_HEADER",
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[CR_NOOP] = "CR_NOOP",
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[ER_TRANSFER] = "ER_TRANSFER",
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[ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
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[ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
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[ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
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[ER_DOORBELL] = "ER_DOORBELL",
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[ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
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[ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
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[ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
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[CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
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[CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
352
static const char *TRBCCode_names[] = {353
[CC_INVALID] = "CC_INVALID",
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[CC_SUCCESS] = "CC_SUCCESS",
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[CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
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[CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
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[CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
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[CC_TRB_ERROR] = "CC_TRB_ERROR",
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[CC_STALL_ERROR] = "CC_STALL_ERROR",
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[CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
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[CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
362
[CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
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[CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
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[CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
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[CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
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[CC_SHORT_PACKET] = "CC_SHORT_PACKET",
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[CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
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[CC_RING_OVERRUN] = "CC_RING_OVERRUN",
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[CC_VF_ER_FULL] = "CC_VF_ER_FULL",
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[CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
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[CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
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[CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
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[CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
374
[CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
375
[CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
376
[CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
377
[CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
378
[CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
379
[CC_STOPPED] = "CC_STOPPED",
380
[CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
381
[CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
382
= "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
383
[CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
384
[CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
385
[CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
386
[CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
387
[CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
388
[CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
391
static const char *ep_state_names[] = {392
[EP_DISABLED] = "disabled",
393
[EP_RUNNING] = "running",
394
[EP_HALTED] = "halted",
395
[EP_STOPPED] = "stopped",
396
[EP_ERROR] = "error",
399
static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
401
if (index >= llen || list[index] == NULL) {407
static const char *trb_name(XHCITRB *trb)
409
return lookup_name(TRB_TYPE(*trb), TRBType_names,
410
ARRAY_SIZE(TRBType_names));
413
static const char *event_name(XHCIEvent *event)
415
return lookup_name(event->ccode, TRBCCode_names,
416
ARRAY_SIZE(TRBCCode_names));
419
static const char *ep_state_name(uint32_t state)
421
return lookup_name(state, ep_state_names,
422
ARRAY_SIZE(ep_state_names));
425
bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
427
return xhci->flags & (1 << bit);
430
void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit)
432
xhci->flags |= (1 << bit);
435
static uint64_t xhci_mfindex_get(XHCIState *xhci)
437
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
438
return (now - xhci->mfindex_start) / 125000;
441
static void xhci_mfwrap_update(XHCIState *xhci)
443
const uint32_t bits = USBCMD_RS | USBCMD_EWE;
444
uint32_t mfindex, left;
447
if ((xhci->usbcmd & bits) == bits) {448
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
449
mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
450
left = 0x4000 - mfindex;
451
timer_mod(xhci->mfwrap_timer, now + left * 125000);
453
timer_del(xhci->mfwrap_timer);
457
static void xhci_mfwrap_timer(void *opaque)
459
XHCIState *xhci = opaque;
460
XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };462
xhci_event(xhci, &wrap, 0);
463
xhci_mfwrap_update(xhci);
466
static void xhci_die(XHCIState *xhci)
468
xhci->usbsts |= USBSTS_HCE;
469
DPRINTF("xhci: asserted controller error\n");472
static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
474
if (sizeof(dma_addr_t) == 4) {477
return low | (((dma_addr_t)high << 16) << 16);
481
static inline dma_addr_t xhci_mask64(uint64_t addr)
483
if (sizeof(dma_addr_t) == 4) {484
return addr & 0xffffffff;
490
static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
491
uint32_t *buf, size_t len)
495
assert((len % sizeof(uint32_t)) == 0);
497
if (dma_memory_read(xhci->as, addr, buf, len,
498
MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {499
qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
501
memset(buf, 0xff, len);
506
for (i = 0; i < (len / sizeof(uint32_t)); i++) {507
buf[i] = le32_to_cpu(buf[i]);
511
static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
512
const uint32_t *buf, size_t len)
516
uint32_t n = len / sizeof(uint32_t);
518
assert((len % sizeof(uint32_t)) == 0);
519
assert(n <= ARRAY_SIZE(tmp));
521
for (i = 0; i < n; i++) {522
tmp[i] = cpu_to_le32(buf[i]);
524
if (dma_memory_write(xhci->as, addr, tmp, len,
525
MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {526
qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
533
static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
540
switch (uport->dev->speed) {544
index = uport->index + xhci->numports_3;
546
case USB_SPEED_SUPER:
547
index = uport->index;
552
return &xhci->ports[index];
555
static void xhci_intr_update(XHCIState *xhci, int v)
560
if (xhci->intr[0].iman & IMAN_IP &&
561
xhci->intr[0].iman & IMAN_IE &&
562
xhci->usbcmd & USBCMD_INTE) {565
if (xhci->intr_raise) {566
if (xhci->intr_raise(xhci, 0, level)) {567
xhci->intr[0].iman &= ~IMAN_IP;
571
if (xhci->intr_update) {572
xhci->intr_update(xhci, v,
573
xhci->intr[v].iman & IMAN_IE);
577
static void xhci_intr_raise(XHCIState *xhci, int v)
579
bool pending = (xhci->intr[v].erdp_low & ERDP_EHB);
581
xhci->intr[v].erdp_low |= ERDP_EHB;
582
xhci->intr[v].iman |= IMAN_IP;
583
xhci->usbsts |= USBSTS_EINT;
588
if (!(xhci->intr[v].iman & IMAN_IE)) {592
if (!(xhci->usbcmd & USBCMD_INTE)) {595
if (xhci->intr_raise) {596
if (xhci->intr_raise(xhci, v, true)) {597
xhci->intr[v].iman &= ~IMAN_IP;
602
static inline int xhci_running(XHCIState *xhci)
604
return !(xhci->usbsts & USBSTS_HCH);
607
static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
609
XHCIInterrupter *intr = &xhci->intr[v];
613
ev_trb.parameter = cpu_to_le64(event->ptr);
614
ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
615
ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
616
event->flags | (event->type << TRB_TYPE_SHIFT);
618
ev_trb.control |= TRB_C;
620
ev_trb.control = cpu_to_le32(ev_trb.control);
622
trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
623
event_name(event), ev_trb.parameter,
624
ev_trb.status, ev_trb.control);
626
addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
627
if (dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE,
628
MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {629
qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
635
if (intr->er_ep_idx >= intr->er_size) {637
intr->er_pcs = !intr->er_pcs;
641
static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
643
XHCIInterrupter *intr;
647
if (v >= xhci->numintrs) {648
DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);651
intr = &xhci->intr[v];
653
erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
654
if (erdp < intr->er_start ||
655
erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {656
DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);657
DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",658
v, intr->er_start, intr->er_size);
663
dp_idx = (erdp - intr->er_start) / TRB_SIZE;
664
assert(dp_idx < intr->er_size);
666
if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) {667
DPRINTF("xhci: ER %d full, send ring full error\n", v);668
XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};669
xhci_write_event(xhci, &full, v);
670
} else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) {671
DPRINTF("xhci: ER %d full, drop event\n", v);673
xhci_write_event(xhci, event, v);
676
xhci_intr_raise(xhci, v);
679
static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
682
ring->dequeue = base;
686
static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
689
uint32_t link_cnt = 0;
693
if (dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE,
694
MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {695
qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
699
trb->addr = ring->dequeue;
700
trb->ccs = ring->ccs;
701
le64_to_cpus(&trb->parameter);
702
le32_to_cpus(&trb->status);
703
le32_to_cpus(&trb->control);
705
trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
706
trb->parameter, trb->status, trb->control);
708
if ((trb->control & TRB_C) != ring->ccs) {712
type = TRB_TYPE(*trb);
714
if (type != TR_LINK) {716
*addr = ring->dequeue;
718
ring->dequeue += TRB_SIZE;
721
if (++link_cnt > TRB_LINK_LIMIT) {722
trace_usb_xhci_enforced_limit("trb-link");725
ring->dequeue = xhci_mask64(trb->parameter);
726
if (trb->control & TRB_LK_TC) {727
ring->ccs = !ring->ccs;
733
static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
737
dma_addr_t dequeue = ring->dequeue;
738
bool ccs = ring->ccs;
739
/* hack to bundle together the two/three TDs that make a setup transfer */
740
bool control_td_set = 0;
741
uint32_t link_cnt = 0;
745
if (dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE,
746
MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {747
qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
751
le64_to_cpus(&trb.parameter);
752
le32_to_cpus(&trb.status);
753
le32_to_cpus(&trb.control);
755
if ((trb.control & TRB_C) != ccs) {759
type = TRB_TYPE(trb);
761
if (type == TR_LINK) {762
if (++link_cnt > TRB_LINK_LIMIT) {765
dequeue = xhci_mask64(trb.parameter);
766
if (trb.control & TRB_LK_TC) {775
if (type == TR_SETUP) {777
} else if (type == TR_STATUS) {781
if (!control_td_set && !(trb.control & TRB_TR_CH)) {786
* According to the xHCI spec, Transfer Ring segments should have
787
* a maximum size of 64 kB (see chapter "6 Data Structures")
789
} while (length < TRB_LINK_LIMIT * 65536 / TRB_SIZE);
791
qemu_log_mask(LOG_GUEST_ERROR, "%s: exceeded maximum transfer ring size!\n",
797
static void xhci_er_reset(XHCIState *xhci, int v)
799
XHCIInterrupter *intr = &xhci->intr[v];
801
dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
803
if (intr->erstsz == 0 || erstba == 0) {809
/* cache the (sole) event ring segment location */
810
if (intr->erstsz != 1) {811
DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);815
if (dma_memory_read(xhci->as, erstba, &seg, sizeof(seg),
816
MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {817
qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory access failed!\n",
823
le32_to_cpus(&seg.addr_low);
824
le32_to_cpus(&seg.addr_high);
825
le32_to_cpus(&seg.size);
826
if (seg.size < 16 || seg.size > 4096) {827
DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);831
intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
832
intr->er_size = seg.size;
837
DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",838
v, intr->er_start, intr->er_size);
841
static void xhci_run(XHCIState *xhci)
843
trace_usb_xhci_run();
844
xhci->usbsts &= ~USBSTS_HCH;
845
xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
848
static void xhci_stop(XHCIState *xhci)
850
trace_usb_xhci_stop();
851
xhci->usbsts |= USBSTS_HCH;
852
xhci->crcr_low &= ~CRCR_CRR;
855
static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
858
XHCIStreamContext *stctx;
861
stctx = g_new0(XHCIStreamContext, count);
862
for (i = 0; i < count; i++) {863
stctx[i].pctx = base + i * 16;
869
static void xhci_reset_streams(XHCIEPContext *epctx)
873
for (i = 0; i < epctx->nr_pstreams; i++) {874
epctx->pstreams[i].sct = -1;
878
static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
880
assert(epctx->pstreams == NULL);
881
epctx->nr_pstreams = 2 << epctx->max_pstreams;
882
epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
885
static void xhci_free_streams(XHCIEPContext *epctx)
887
assert(epctx->pstreams != NULL);
889
g_free(epctx->pstreams);
890
epctx->pstreams = NULL;
891
epctx->nr_pstreams = 0;
894
static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
897
XHCIEPContext **epctxs,
901
XHCIEPContext *epctx;
905
assert(slotid >= 1 && slotid <= xhci->numslots);
907
slot = &xhci->slots[slotid - 1];
909
for (i = 2, j = 0; i <= 31; i++) {910
if (!(epmask & (1u << i))) {914
epctx = slot->eps[i - 1];
915
ep = xhci_epid_to_usbep(epctx);
916
if (!epctx || !epctx->nr_pstreams || !ep) {928
static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
931
USBEndpoint *eps[30];
934
nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
936
usb_device_free_streams(eps[0]->dev, eps, nr_eps);
940
static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
943
XHCIEPContext *epctxs[30];
944
USBEndpoint *eps[30];
945
int i, r, nr_eps, req_nr_streams, dev_max_streams;
947
nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
953
req_nr_streams = epctxs[0]->nr_pstreams;
954
dev_max_streams = eps[0]->max_streams;
956
for (i = 1; i < nr_eps; i++) {958
* HdG: I don't expect these to ever trigger, but if they do we need
959
* to come up with another solution, ie group identical endpoints
960
* together and make an usb_device_alloc_streams call per group.
962
if (epctxs[i]->nr_pstreams != req_nr_streams) {963
FIXME("guest streams config not identical for all eps");964
return CC_RESOURCE_ERROR;
966
if (eps[i]->max_streams != dev_max_streams) {967
FIXME("device streams config not identical for all eps");968
return CC_RESOURCE_ERROR;
973
* max-streams in both the device descriptor and in the controller is a
974
* power of 2. But stream id 0 is reserved, so if a device can do up to 4
975
* streams the guest will ask for 5 rounded up to the next power of 2 which
976
* becomes 8. For emulated devices usb_device_alloc_streams is a nop.
978
* For redirected devices however this is an issue, as there we must ask
979
* the real xhci controller to alloc streams, and the host driver for the
980
* real xhci controller will likely disallow allocating more streams then
981
* the device can handle.
983
* So we limit the requested nr_streams to the maximum number the device
986
if (req_nr_streams > dev_max_streams) {987
req_nr_streams = dev_max_streams;
990
r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
992
DPRINTF("xhci: alloc streams failed\n");993
return CC_RESOURCE_ERROR;
999
static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1000
unsigned int streamid,
1003
XHCIStreamContext *sctx;
1005
uint32_t ctx[2], sct;
1007
assert(streamid != 0);
1009
if (streamid >= epctx->nr_pstreams) {1010
*cc_error = CC_INVALID_STREAM_ID_ERROR;
1013
sctx = epctx->pstreams + streamid;
1015
fprintf(stderr, "xhci: FIXME: secondary streams not implemented yet");
1016
*cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1020
if (sctx->sct == -1) {1021
xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1022
sct = (ctx[0] >> 1) & 0x07;
1023
if (epctx->lsa && sct != 1) {1024
*cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1028
base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1029
xhci_ring_init(epctx->xhci, &sctx->ring, base);
1034
static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1035
XHCIStreamContext *sctx, uint32_t state)
1037
XHCIRing *ring = NULL;
1041
xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1042
ctx[0] &= ~EP_STATE_MASK;
1045
/* update ring dequeue ptr */
1046
if (epctx->nr_pstreams) {1049
xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1051
ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1052
ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1053
xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1056
ring = &epctx->ring;
1059
ctx[2] = ring->dequeue | ring->ccs;
1060
ctx[3] = (ring->dequeue >> 16) >> 16;
1062
DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",1063
epctx->pctx, state, ctx[3], ctx[2]);
1066
xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1067
if (epctx->state != state) {1068
trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1069
ep_state_name(epctx->state),
1070
ep_state_name(state));
1072
epctx->state = state;
1075
static void xhci_ep_kick_timer(void *opaque)
1077
XHCIEPContext *epctx = opaque;
1078
xhci_kick_epctx(epctx, 0);
1081
static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1082
unsigned int slotid,
1085
XHCIEPContext *epctx;
1087
epctx = g_new0(XHCIEPContext, 1);
1089
epctx->slotid = slotid;
1092
QTAILQ_INIT(&epctx->transfers);
1093
epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1098
static void xhci_init_epctx(XHCIEPContext *epctx,
1099
dma_addr_t pctx, uint32_t *ctx)
1103
dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1105
epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1107
epctx->max_psize = ctx[1]>>16;
1108
epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1109
epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
1110
epctx->lsa = (ctx[0] >> 15) & 1;
1111
if (epctx->max_pstreams) {1112
xhci_alloc_streams(epctx, dequeue);
1114
xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1115
epctx->ring.ccs = ctx[2] & 1;
1118
epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1121
static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1122
unsigned int epid, dma_addr_t pctx,
1126
XHCIEPContext *epctx;
1128
trace_usb_xhci_ep_enable(slotid, epid);
1129
assert(slotid >= 1 && slotid <= xhci->numslots);
1130
assert(epid >= 1 && epid <= 31);
1132
slot = &xhci->slots[slotid-1];
1133
if (slot->eps[epid-1]) {1134
xhci_disable_ep(xhci, slotid, epid);
1137
epctx = xhci_alloc_epctx(xhci, slotid, epid);
1138
slot->eps[epid-1] = epctx;
1139
xhci_init_epctx(epctx, pctx, ctx);
1141
DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "1142
"size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1144
epctx->mfindex_last = 0;
1146
epctx->state = EP_RUNNING;
1147
ctx[0] &= ~EP_STATE_MASK;
1148
ctx[0] |= EP_RUNNING;
1153
static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx,
1156
uint32_t limit = epctx->nr_pstreams + 16;
1159
if (epctx->xfer_count >= limit) {1163
xfer = g_new0(XHCITransfer, 1);
1164
xfer->epctx = epctx;
1165
xfer->trbs = g_new(XHCITRB, length);
1166
xfer->trb_count = length;
1167
usb_packet_init(&xfer->packet);
1169
QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next);
1170
epctx->xfer_count++;
1175
static void xhci_ep_free_xfer(XHCITransfer *xfer)
1177
QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next);
1178
xfer->epctx->xfer_count--;
1180
usb_packet_cleanup(&xfer->packet);
1185
static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1189
if (report && (t->running_async || t->running_retry)) {1191
xhci_xfer_report(t);
1194
if (t->running_async) {1195
usb_cancel_packet(&t->packet);
1196
t->running_async = 0;
1199
if (t->running_retry) {1201
t->epctx->retry = NULL;
1202
timer_del(t->epctx->kick_timer);
1204
t->running_retry = 0;
1215
static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1216
unsigned int epid, TRBCCode report)
1219
XHCIEPContext *epctx;
1222
USBEndpoint *ep = NULL;
1223
assert(slotid >= 1 && slotid <= xhci->numslots);
1224
assert(epid >= 1 && epid <= 31);
1226
DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);1228
slot = &xhci->slots[slotid-1];
1230
if (!slot->eps[epid-1]) {1234
epctx = slot->eps[epid-1];
1237
xfer = QTAILQ_FIRST(&epctx->transfers);
1241
killed += xhci_ep_nuke_one_xfer(xfer, report);
1243
report = 0; /* Only report once */
1245
xhci_ep_free_xfer(xfer);
1248
ep = xhci_epid_to_usbep(epctx);
1250
usb_device_ep_stopped(ep->dev, ep);
1255
static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1259
XHCIEPContext *epctx;
1261
trace_usb_xhci_ep_disable(slotid, epid);
1262
assert(slotid >= 1 && slotid <= xhci->numslots);
1263
assert(epid >= 1 && epid <= 31);
1265
slot = &xhci->slots[slotid-1];
1267
if (!slot->eps[epid-1]) {1268
DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);1272
xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1274
epctx = slot->eps[epid-1];
1276
if (epctx->nr_pstreams) {1277
xhci_free_streams(epctx);
1280
/* only touch guest RAM if we're not resetting the HC */
1281
if (xhci->dcbaap_low || xhci->dcbaap_high) {1282
xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1285
timer_free(epctx->kick_timer);
1287
slot->eps[epid-1] = NULL;
1292
static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1296
XHCIEPContext *epctx;
1298
trace_usb_xhci_ep_stop(slotid, epid);
1299
assert(slotid >= 1 && slotid <= xhci->numslots);
1301
if (epid < 1 || epid > 31) {1302
DPRINTF("xhci: bad ep %d\n", epid);1303
return CC_TRB_ERROR;
1306
slot = &xhci->slots[slotid-1];
1308
if (!slot->eps[epid-1]) {1309
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);1310
return CC_EP_NOT_ENABLED_ERROR;
1313
if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {1314
DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "1315
"data might be lost\n");
1318
epctx = slot->eps[epid-1];
1320
xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1322
if (epctx->nr_pstreams) {1323
xhci_reset_streams(epctx);
1329
static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1333
XHCIEPContext *epctx;
1335
trace_usb_xhci_ep_reset(slotid, epid);
1336
assert(slotid >= 1 && slotid <= xhci->numslots);
1338
if (epid < 1 || epid > 31) {1339
DPRINTF("xhci: bad ep %d\n", epid);1340
return CC_TRB_ERROR;
1343
slot = &xhci->slots[slotid-1];
1345
if (!slot->eps[epid-1]) {1346
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);1347
return CC_EP_NOT_ENABLED_ERROR;
1350
epctx = slot->eps[epid-1];
1352
if (epctx->state != EP_HALTED) {1353
DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",1354
epid, epctx->state);
1355
return CC_CONTEXT_STATE_ERROR;
1358
if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {1359
DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "1360
"data might be lost\n");
1363
if (!xhci->slots[slotid-1].uport ||
1364
!xhci->slots[slotid-1].uport->dev ||
1365
!xhci->slots[slotid-1].uport->dev->attached) {1366
return CC_USB_TRANSACTION_ERROR;
1369
xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1371
if (epctx->nr_pstreams) {1372
xhci_reset_streams(epctx);
1378
static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1379
unsigned int epid, unsigned int streamid,
1383
XHCIEPContext *epctx;
1384
XHCIStreamContext *sctx;
1387
assert(slotid >= 1 && slotid <= xhci->numslots);
1389
if (epid < 1 || epid > 31) {1390
DPRINTF("xhci: bad ep %d\n", epid);1391
return CC_TRB_ERROR;
1394
trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1395
dequeue = xhci_mask64(pdequeue);
1397
slot = &xhci->slots[slotid-1];
1399
if (!slot->eps[epid-1]) {1400
DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);1401
return CC_EP_NOT_ENABLED_ERROR;
1404
epctx = slot->eps[epid-1];
1406
if (epctx->state != EP_STOPPED) {1407
DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);1408
return CC_CONTEXT_STATE_ERROR;
1411
if (epctx->nr_pstreams) {1413
sctx = xhci_find_stream(epctx, streamid, &err);
1417
xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1418
sctx->ring.ccs = dequeue & 1;
1421
xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1422
epctx->ring.ccs = dequeue & 1;
1425
xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1430
static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1432
XHCIState *xhci = xfer->epctx->xhci;
1435
xfer->int_req = false;
1436
qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count, xhci->as);
1437
for (i = 0; i < xfer->trb_count; i++) {1438
XHCITRB *trb = &xfer->trbs[i];
1440
unsigned int chunk = 0;
1442
if (trb->control & TRB_TR_IOC) {1443
xfer->int_req = true;
1446
switch (TRB_TYPE(*trb)) {1448
if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {1449
DPRINTF("xhci: data direction mismatch for TR_DATA\n");1455
addr = xhci_mask64(trb->parameter);
1456
chunk = trb->status & 0x1ffff;
1457
if (trb->control & TRB_TR_IDT) {1458
if (chunk > 8 || in_xfer) {1459
DPRINTF("xhci: invalid immediate data TRB\n");1462
qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1464
qemu_sglist_add(&xfer->sgl, addr, chunk);
1473
qemu_sglist_destroy(&xfer->sgl);
1478
static void xhci_xfer_unmap(XHCITransfer *xfer)
1480
usb_packet_unmap(&xfer->packet, &xfer->sgl);
1481
qemu_sglist_destroy(&xfer->sgl);
1484
static void xhci_xfer_report(XHCITransfer *xfer)
1490
XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};1491
XHCIState *xhci = xfer->epctx->xhci;
1494
left = xfer->packet.actual_length;
1496
for (i = 0; i < xfer->trb_count; i++) {1497
XHCITRB *trb = &xfer->trbs[i];
1498
unsigned int chunk = 0;
1500
switch (TRB_TYPE(*trb)) {1502
chunk = trb->status & 0x1ffff;
1510
chunk = trb->status & 0x1ffff;
1513
if (xfer->status == CC_SUCCESS) {1526
if (!reported && ((trb->control & TRB_TR_IOC) ||
1527
(shortpkt && (trb->control & TRB_TR_ISP)) ||
1528
(xfer->status != CC_SUCCESS && left == 0))) {1529
event.slotid = xfer->epctx->slotid;
1530
event.epid = xfer->epctx->epid;
1531
event.length = (trb->status & 0x1ffff) - chunk;
1533
event.ptr = trb->addr;
1534
if (xfer->status == CC_SUCCESS) {1535
event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1537
event.ccode = xfer->status;
1539
if (TRB_TYPE(*trb) == TR_EVDATA) {1540
event.ptr = trb->parameter;
1541
event.flags |= TRB_EV_ED;
1542
event.length = edtla & 0xffffff;
1543
DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);1546
xhci_event(xhci, &event, TRB_INTR(*trb));
1548
if (xfer->status != CC_SUCCESS) {1553
switch (TRB_TYPE(*trb)) {1563
static void xhci_stall_ep(XHCITransfer *xfer)
1565
XHCIEPContext *epctx = xfer->epctx;
1566
XHCIState *xhci = epctx->xhci;
1568
XHCIStreamContext *sctx;
1570
if (epctx->type == ET_ISO_IN || epctx->type == ET_ISO_OUT) {1571
/* never halt isoch endpoints, 4.10.2 */
1575
if (epctx->nr_pstreams) {1576
sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1580
sctx->ring.dequeue = xfer->trbs[0].addr;
1581
sctx->ring.ccs = xfer->trbs[0].ccs;
1582
xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1584
epctx->ring.dequeue = xfer->trbs[0].addr;
1585
epctx->ring.ccs = xfer->trbs[0].ccs;
1586
xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1590
static int xhci_setup_packet(XHCITransfer *xfer)
1595
dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1597
if (xfer->packet.ep) {1598
ep = xfer->packet.ep;
1600
ep = xhci_epid_to_usbep(xfer->epctx);
1602
DPRINTF("xhci: slot %d has no device\n",1603
xfer->epctx->slotid);
1608
xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1609
usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1610
xfer->trbs[0].addr, false, xfer->int_req);
1611
if (usb_packet_map(&xfer->packet, &xfer->sgl)) {1612
qemu_sglist_destroy(&xfer->sgl);
1615
DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",1616
xfer->packet.pid, ep->dev->addr, ep->nr);
1620
static int xhci_try_complete_packet(XHCITransfer *xfer)
1622
if (xfer->packet.status == USB_RET_ASYNC) {1623
trace_usb_xhci_xfer_async(xfer);
1624
xfer->running_async = 1;
1625
xfer->running_retry = 0;
1628
} else if (xfer->packet.status == USB_RET_NAK) {1629
trace_usb_xhci_xfer_nak(xfer);
1630
xfer->running_async = 0;
1631
xfer->running_retry = 1;
1635
xfer->running_async = 0;
1636
xfer->running_retry = 0;
1638
xhci_xfer_unmap(xfer);
1641
if (xfer->packet.status == USB_RET_SUCCESS) {1642
trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1643
xfer->status = CC_SUCCESS;
1644
xhci_xfer_report(xfer);
1649
trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1650
switch (xfer->packet.status) {1652
case USB_RET_IOERROR:
1653
xfer->status = CC_USB_TRANSACTION_ERROR;
1654
xhci_xfer_report(xfer);
1655
xhci_stall_ep(xfer);
1658
xfer->status = CC_STALL_ERROR;
1659
xhci_xfer_report(xfer);
1660
xhci_stall_ep(xfer);
1662
case USB_RET_BABBLE:
1663
xfer->status = CC_BABBLE_DETECTED;
1664
xhci_xfer_report(xfer);
1665
xhci_stall_ep(xfer);
1668
DPRINTF("%s: FIXME: status = %d\n", __func__,1669
xfer->packet.status);
1670
FIXME("unhandled USB_RET_*");1675
static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1677
XHCITRB *trb_setup, *trb_status;
1678
uint8_t bmRequestType;
1680
trb_setup = &xfer->trbs[0];
1681
trb_status = &xfer->trbs[xfer->trb_count-1];
1683
trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1684
xfer->epctx->epid, xfer->streamid);
1686
/* at most one Event Data TRB allowed after STATUS */
1687
if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {1691
/* do some sanity checks */
1692
if (TRB_TYPE(*trb_setup) != TR_SETUP) {1693
DPRINTF("xhci: ep0 first TD not SETUP: %d\n",1694
TRB_TYPE(*trb_setup));
1697
if (TRB_TYPE(*trb_status) != TR_STATUS) {1698
DPRINTF("xhci: ep0 last TD not STATUS: %d\n",1699
TRB_TYPE(*trb_status));
1702
if (!(trb_setup->control & TRB_TR_IDT)) {1703
DPRINTF("xhci: Setup TRB doesn't have IDT set\n");1706
if ((trb_setup->status & 0x1ffff) != 8) {1707
DPRINTF("xhci: Setup TRB has bad length (%d)\n",1708
(trb_setup->status & 0x1ffff));
1712
bmRequestType = trb_setup->parameter;
1714
xfer->in_xfer = bmRequestType & USB_DIR_IN;
1715
xfer->iso_xfer = false;
1716
xfer->timed_xfer = false;
1718
if (xhci_setup_packet(xfer) < 0) {1721
xfer->packet.parameter = trb_setup->parameter;
1723
usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1724
xhci_try_complete_packet(xfer);
1728
static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1729
XHCIEPContext *epctx, uint64_t mfindex)
1731
uint64_t asap = ((mfindex + epctx->interval - 1) &
1732
~(epctx->interval-1));
1733
uint64_t kick = epctx->mfindex_last + epctx->interval;
1735
assert(epctx->interval != 0);
1736
xfer->mfindex_kick = MAX(asap, kick);
1739
static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1740
XHCIEPContext *epctx, uint64_t mfindex)
1742
if (xfer->trbs[0].control & TRB_TR_SIA) {1743
uint64_t asap = ((mfindex + epctx->interval - 1) &
1744
~(epctx->interval-1));
1745
if (asap >= epctx->mfindex_last &&
1746
asap <= epctx->mfindex_last + epctx->interval * 4) {1747
xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1749
xfer->mfindex_kick = asap;
1752
xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1753
& TRB_TR_FRAMEID_MASK) << 3;
1754
xfer->mfindex_kick |= mfindex & ~0x3fff;
1755
if (xfer->mfindex_kick + 0x100 < mfindex) {1756
xfer->mfindex_kick += 0x4000;
1761
static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1762
XHCIEPContext *epctx, uint64_t mfindex)
1764
if (xfer->mfindex_kick > mfindex) {1765
timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
1766
(xfer->mfindex_kick - mfindex) * 125000);
1767
xfer->running_retry = 1;
1769
epctx->mfindex_last = xfer->mfindex_kick;
1770
timer_del(epctx->kick_timer);
1771
xfer->running_retry = 0;
1776
static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1780
DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", epctx->slotid, epctx->epid);1782
xfer->in_xfer = epctx->type>>2;
1784
switch(epctx->type) {1788
xfer->iso_xfer = false;
1789
xfer->timed_xfer = true;
1790
mfindex = xhci_mfindex_get(xhci);
1791
xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
1792
xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1793
if (xfer->running_retry) {1800
xfer->iso_xfer = false;
1801
xfer->timed_xfer = false;
1806
xfer->iso_xfer = true;
1807
xfer->timed_xfer = true;
1808
mfindex = xhci_mfindex_get(xhci);
1809
xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1810
xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1811
if (xfer->running_retry) {1816
trace_usb_xhci_unimplemented("endpoint type", epctx->type);1820
if (xhci_setup_packet(xfer) < 0) {1823
usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1824
xhci_try_complete_packet(xfer);
1828
static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1830
trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1831
xfer->epctx->epid, xfer->streamid);
1832
return xhci_submit(xhci, xfer, epctx);
1835
static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
1836
unsigned int epid, unsigned int streamid)
1838
XHCIEPContext *epctx;
1840
assert(slotid >= 1 && slotid <= xhci->numslots);
1841
assert(epid >= 1 && epid <= 31);
1843
if (!xhci->slots[slotid-1].enabled) {1844
DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);1847
epctx = xhci->slots[slotid-1].eps[epid-1];
1849
DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",1854
if (epctx->kick_active) {1857
xhci_kick_epctx(epctx, streamid);
1860
static bool xhci_slot_ok(XHCIState *xhci, int slotid)
1862
return (xhci->slots[slotid - 1].uport &&
1863
xhci->slots[slotid - 1].uport->dev &&
1864
xhci->slots[slotid - 1].uport->dev->attached);
1867
static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid)
1869
XHCIState *xhci = epctx->xhci;
1870
XHCIStreamContext *stctx = NULL;
1873
USBEndpoint *ep = NULL;
1875
unsigned int count = 0;
1879
trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid);
1880
assert(!epctx->kick_active);
1882
/* If the device has been detached, but the guest has not noticed this
1883
yet the 2 above checks will succeed, but we must NOT continue */
1884
if (!xhci_slot_ok(xhci, epctx->slotid)) {1889
xfer = epctx->retry;
1891
trace_usb_xhci_xfer_retry(xfer);
1892
assert(xfer->running_retry);
1893
if (xfer->timed_xfer) {1894
/* time to kick the transfer? */
1895
mfindex = xhci_mfindex_get(xhci);
1896
xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
1897
if (xfer->running_retry) {1900
xfer->timed_xfer = 0;
1901
xfer->running_retry = 1;
1903
if (xfer->iso_xfer) {1904
/* retry iso transfer */
1905
if (xhci_setup_packet(xfer) < 0) {1908
usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1909
assert(xfer->packet.status != USB_RET_NAK);
1910
xhci_try_complete_packet(xfer);
1912
/* retry nak'ed transfer */
1913
if (xhci_setup_packet(xfer) < 0) {1916
usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1917
if (xfer->packet.status == USB_RET_NAK) {1918
xhci_xfer_unmap(xfer);
1921
xhci_try_complete_packet(xfer);
1923
assert(!xfer->running_retry);
1924
if (xfer->complete) {1925
/* update ring dequeue ptr */
1926
xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
1927
xhci_ep_free_xfer(epctx->retry);
1929
epctx->retry = NULL;
1932
if (epctx->state == EP_HALTED) {1933
DPRINTF("xhci: ep halted, not running schedule\n");1938
if (epctx->nr_pstreams) {1940
stctx = xhci_find_stream(epctx, streamid, &err);
1941
if (stctx == NULL) {1944
ring = &stctx->ring;
1945
xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
1947
ring = &epctx->ring;
1949
xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
1951
if (!ring->dequeue) {1955
epctx->kick_active++;
1957
length = xhci_ring_chain_length(xhci, ring);
1959
if (epctx->type == ET_ISO_OUT || epctx->type == ET_ISO_IN) {1961
XHCIEvent ev = { ER_TRANSFER };1962
ev.ccode = epctx->type == ET_ISO_IN ?
1963
CC_RING_OVERRUN : CC_RING_UNDERRUN;
1964
ev.slotid = epctx->slotid;
1965
ev.epid = epctx->epid;
1966
ev.ptr = epctx->ring.dequeue;
1967
xhci_event(xhci, &ev, xhci->slots[epctx->slotid-1].intr);
1971
xfer = xhci_ep_alloc_xfer(epctx, length);
1976
for (i = 0; i < length; i++) {1978
type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL);
1981
xhci_ep_free_xfer(xfer);
1982
epctx->kick_active--;
1986
xfer->streamid = streamid;
1988
if (epctx->epid == 1) {1989
xhci_fire_ctl_transfer(xhci, xfer);
1991
xhci_fire_transfer(xhci, xfer, epctx);
1993
if (!xhci_slot_ok(xhci, epctx->slotid)) {1994
/* surprise removal -> stop processing */
1997
if (xfer->complete) {1998
/* update ring dequeue ptr */
1999
xhci_set_ep_state(xhci, epctx, stctx, epctx->state);
2000
xhci_ep_free_xfer(xfer);
2004
if (epctx->state == EP_HALTED) {2007
if (xfer != NULL && xfer->running_retry) {2008
DPRINTF("xhci: xfer nacked, stopping schedule\n");2009
epctx->retry = xfer;
2010
xhci_xfer_unmap(xfer);
2013
if (count++ > TRANSFER_LIMIT) {2014
trace_usb_xhci_enforced_limit("transfers");2018
epctx->kick_active--;
2020
ep = xhci_epid_to_usbep(epctx);
2022
usb_device_flush_ep_queue(ep->dev, ep);
2026
static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2028
trace_usb_xhci_slot_enable(slotid);
2029
assert(slotid >= 1 && slotid <= xhci->numslots);
2030
xhci->slots[slotid-1].enabled = 1;
2031
xhci->slots[slotid-1].uport = NULL;
2032
memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2037
static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2041
trace_usb_xhci_slot_disable(slotid);
2042
assert(slotid >= 1 && slotid <= xhci->numslots);
2044
for (i = 1; i <= 31; i++) {2045
if (xhci->slots[slotid-1].eps[i-1]) {2046
xhci_disable_ep(xhci, slotid, i);
2050
xhci->slots[slotid-1].enabled = 0;
2051
xhci->slots[slotid-1].addressed = 0;
2052
xhci->slots[slotid-1].uport = NULL;
2053
xhci->slots[slotid-1].intr = 0;
2057
static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2063
port = (slot_ctx[1]>>16) & 0xFF;
2064
if (port < 1 || port > xhci->numports) {2067
port = xhci->ports[port-1].uport->index+1;
2068
pos = snprintf(path, sizeof(path), "%d", port);
2069
for (i = 0; i < 5; i++) {2070
port = (slot_ctx[0] >> 4*i) & 0x0f;
2074
pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2077
QTAILQ_FOREACH(uport, &xhci->bus.used, next) {2078
if (strcmp(uport->path, path) == 0) {2085
static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2086
uint64_t pictx, bool bsr)
2091
dma_addr_t ictx, octx, dcbaap;
2093
uint32_t ictl_ctx[2];
2094
uint32_t slot_ctx[4];
2095
uint32_t ep0_ctx[5];
2099
assert(slotid >= 1 && slotid <= xhci->numslots);
2101
dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2102
ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &poctx, MEMTXATTRS_UNSPECIFIED);
2103
ictx = xhci_mask64(pictx);
2104
octx = xhci_mask64(poctx);
2106
DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);2107
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);2109
xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2111
if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {2112
DPRINTF("xhci: invalid input context control %08x %08x\n",2113
ictl_ctx[0], ictl_ctx[1]);
2114
return CC_TRB_ERROR;
2117
xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2118
xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2120
DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",2121
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2123
DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",2124
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2126
uport = xhci_lookup_uport(xhci, slot_ctx);
2127
if (uport == NULL) {2128
DPRINTF("xhci: port not found\n");2129
return CC_TRB_ERROR;
2131
trace_usb_xhci_slot_address(slotid, uport->path);
2134
if (!dev || !dev->attached) {2135
DPRINTF("xhci: port %s not connected\n", uport->path);2136
return CC_USB_TRANSACTION_ERROR;
2139
for (i = 0; i < xhci->numslots; i++) {2140
if (i == slotid-1) {2143
if (xhci->slots[i].uport == uport) {2144
DPRINTF("xhci: port %s already assigned to slot %d\n",2146
return CC_TRB_ERROR;
2150
slot = &xhci->slots[slotid-1];
2151
slot->uport = uport;
2153
slot->intr = get_field(slot_ctx[2], TRB_INTR);
2155
/* Make sure device is in USB_STATE_DEFAULT state */
2156
usb_device_reset(dev);
2158
slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2163
slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2164
memset(&p, 0, sizeof(p));
2165
usb_packet_addbuf(&p, buf, sizeof(buf));
2166
usb_packet_setup(&p, USB_TOKEN_OUT,
2167
usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2169
usb_device_handle_control(dev, &p,
2170
DeviceOutRequest | USB_REQ_SET_ADDRESS,
2171
slotid, 0, 0, NULL);
2172
assert(p.status != USB_RET_ASYNC);
2173
usb_packet_cleanup(&p);
2176
res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2178
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",2179
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2180
DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",2181
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2183
xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2184
xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2186
xhci->slots[slotid-1].addressed = 1;
2191
static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2192
uint64_t pictx, bool dc)
2194
dma_addr_t ictx, octx;
2195
uint32_t ictl_ctx[2];
2196
uint32_t slot_ctx[4];
2197
uint32_t islot_ctx[4];
2202
trace_usb_xhci_slot_configure(slotid);
2203
assert(slotid >= 1 && slotid <= xhci->numslots);
2205
ictx = xhci_mask64(pictx);
2206
octx = xhci->slots[slotid-1].ctx;
2208
DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);2209
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);2212
for (i = 2; i <= 31; i++) {2213
if (xhci->slots[slotid-1].eps[i-1]) {2214
xhci_disable_ep(xhci, slotid, i);
2218
xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2219
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2220
slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2221
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",2222
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2223
xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2228
xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2230
if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {2231
DPRINTF("xhci: invalid input context control %08x %08x\n",2232
ictl_ctx[0], ictl_ctx[1]);
2233
return CC_TRB_ERROR;
2236
xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2237
xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2239
if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {2240
DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);2241
return CC_CONTEXT_STATE_ERROR;
2244
xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2246
for (i = 2; i <= 31; i++) {2247
if (ictl_ctx[0] & (1<<i)) {2248
xhci_disable_ep(xhci, slotid, i);
2250
if (ictl_ctx[1] & (1<<i)) {2251
xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2252
DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",2253
i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2254
ep_ctx[3], ep_ctx[4]);
2255
xhci_disable_ep(xhci, slotid, i);
2256
res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2257
if (res != CC_SUCCESS) {2260
DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",2261
i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2262
ep_ctx[3], ep_ctx[4]);
2263
xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2267
res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2268
if (res != CC_SUCCESS) {2269
for (i = 2; i <= 31; i++) {2270
if (ictl_ctx[1] & (1u << i)) {2271
xhci_disable_ep(xhci, slotid, i);
2277
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2278
slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2279
slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2280
slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2281
SLOT_CONTEXT_ENTRIES_SHIFT);
2282
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",2283
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2285
xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2291
static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2294
dma_addr_t ictx, octx;
2295
uint32_t ictl_ctx[2];
2296
uint32_t iep0_ctx[5];
2297
uint32_t ep0_ctx[5];
2298
uint32_t islot_ctx[4];
2299
uint32_t slot_ctx[4];
2301
trace_usb_xhci_slot_evaluate(slotid);
2302
assert(slotid >= 1 && slotid <= xhci->numslots);
2304
ictx = xhci_mask64(pictx);
2305
octx = xhci->slots[slotid-1].ctx;
2307
DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);2308
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);2310
xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2312
if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {2313
DPRINTF("xhci: invalid input context control %08x %08x\n",2314
ictl_ctx[0], ictl_ctx[1]);
2315
return CC_TRB_ERROR;
2318
if (ictl_ctx[1] & 0x1) {2319
xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2321
DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",2322
islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2324
xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2326
slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2327
slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2328
/* update interrupter target field */
2329
xhci->slots[slotid-1].intr = get_field(islot_ctx[2], TRB_INTR);
2330
set_field(&slot_ctx[2], xhci->slots[slotid-1].intr, TRB_INTR);
2332
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",2333
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2335
xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2338
if (ictl_ctx[1] & 0x2) {2339
xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2341
DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",2342
iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2343
iep0_ctx[3], iep0_ctx[4]);
2345
xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2347
ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2348
ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2350
DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",2351
ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2353
xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2359
static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2361
uint32_t slot_ctx[4];
2365
trace_usb_xhci_slot_reset(slotid);
2366
assert(slotid >= 1 && slotid <= xhci->numslots);
2368
octx = xhci->slots[slotid-1].ctx;
2370
DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);2372
for (i = 2; i <= 31; i++) {2373
if (xhci->slots[slotid-1].eps[i-1]) {2374
xhci_disable_ep(xhci, slotid, i);
2378
xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2379
slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2380
slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2381
DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",2382
slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2383
xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2388
static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2390
unsigned int slotid;
2391
slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2392
if (slotid < 1 || slotid > xhci->numslots) {2393
DPRINTF("xhci: bad slot id %d\n", slotid);2394
event->ccode = CC_TRB_ERROR;
2396
} else if (!xhci->slots[slotid-1].enabled) {2397
DPRINTF("xhci: slot id %d not enabled\n", slotid);2398
event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2404
/* cleanup slot state on usb device detach */
2405
static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2409
for (slot = 0; slot < xhci->numslots; slot++) {2410
if (xhci->slots[slot].uport == uport) {2414
if (slot == xhci->numslots) {2418
for (ep = 0; ep < 31; ep++) {2419
if (xhci->slots[slot].eps[ep]) {2420
xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2423
xhci->slots[slot].uport = NULL;
2426
static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2430
DPRINTF("xhci_get_port_bandwidth()\n");2432
ctx = xhci_mask64(pctx);
2434
DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);2436
/* TODO: actually implement real values here. This is 80% for all ports. */
2437
if (stb_dma(xhci->as, ctx, 0, MEMTXATTRS_UNSPECIFIED) != MEMTX_OK ||
2438
dma_memory_set(xhci->as, ctx + 1, 80, xhci->numports,
2439
MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) {2440
qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory write failed!\n",
2442
return CC_TRB_ERROR;
2448
static uint32_t rotl(uint32_t v, unsigned count)
2451
return (v << count) | (v >> (32 - count));
2455
static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2458
val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2459
val += rotl(lo + 0x49434878, hi & 0x1F);
2460
val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2464
static void xhci_process_commands(XHCIState *xhci)
2468
XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};2470
unsigned int i, slotid = 0, count = 0;
2472
DPRINTF("xhci_process_commands()\n");2473
if (!xhci_running(xhci)) {2474
DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");2478
xhci->crcr_low |= CRCR_CRR;
2480
while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {2483
case CR_ENABLE_SLOT:
2484
for (i = 0; i < xhci->numslots; i++) {2485
if (!xhci->slots[i].enabled) {2489
if (i >= xhci->numslots) {2490
DPRINTF("xhci: no device slots available\n");2491
event.ccode = CC_NO_SLOTS_ERROR;
2494
event.ccode = xhci_enable_slot(xhci, slotid);
2497
case CR_DISABLE_SLOT:
2498
slotid = xhci_get_slot(xhci, &event, &trb);
2500
event.ccode = xhci_disable_slot(xhci, slotid);
2503
case CR_ADDRESS_DEVICE:
2504
slotid = xhci_get_slot(xhci, &event, &trb);
2506
event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2507
trb.control & TRB_CR_BSR);
2510
case CR_CONFIGURE_ENDPOINT:
2511
slotid = xhci_get_slot(xhci, &event, &trb);
2513
event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2514
trb.control & TRB_CR_DC);
2517
case CR_EVALUATE_CONTEXT:
2518
slotid = xhci_get_slot(xhci, &event, &trb);
2520
event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2523
case CR_STOP_ENDPOINT:
2524
slotid = xhci_get_slot(xhci, &event, &trb);
2526
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2528
event.ccode = xhci_stop_ep(xhci, slotid, epid);
2531
case CR_RESET_ENDPOINT:
2532
slotid = xhci_get_slot(xhci, &event, &trb);
2534
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2536
event.ccode = xhci_reset_ep(xhci, slotid, epid);
2539
case CR_SET_TR_DEQUEUE:
2540
slotid = xhci_get_slot(xhci, &event, &trb);
2542
unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2544
unsigned int streamid = (trb.status >> 16) & 0xffff;
2545
event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2550
case CR_RESET_DEVICE:
2551
slotid = xhci_get_slot(xhci, &event, &trb);
2553
event.ccode = xhci_reset_slot(xhci, slotid);
2556
case CR_GET_PORT_BANDWIDTH:
2557
event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2560
event.ccode = CC_SUCCESS;
2562
case CR_VENDOR_NEC_FIRMWARE_REVISION:
2563
if (xhci->nec_quirks) {2564
event.type = 48; /* NEC reply */
2565
event.length = 0x3034;
2567
event.ccode = CC_TRB_ERROR;
2570
case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2571
if (xhci->nec_quirks) {2572
uint32_t chi = trb.parameter >> 32;
2573
uint32_t clo = trb.parameter;
2574
uint32_t val = xhci_nec_challenge(chi, clo);
2575
event.length = val & 0xFFFF;
2576
event.epid = val >> 16;
2578
event.type = 48; /* NEC reply */
2580
event.ccode = CC_TRB_ERROR;
2584
trace_usb_xhci_unimplemented("command", type);2585
event.ccode = CC_TRB_ERROR;
2588
event.slotid = slotid;
2589
xhci_event(xhci, &event, 0);
2591
if (count++ > COMMAND_LIMIT) {2592
trace_usb_xhci_enforced_limit("commands");2598
static bool xhci_port_have_device(XHCIPort *port)
2600
if (!port->uport->dev || !port->uport->dev->attached) {2601
return false; /* no device present */
2603
if (!((1 << port->uport->dev->speed) & port->speedmask)) {2604
return false; /* speed mismatch */
2609
static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2611
XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,2612
port->portnr << 24 };
2614
if ((port->portsc & bits) == bits) {2617
trace_usb_xhci_port_notify(port->portnr, bits);
2618
port->portsc |= bits;
2619
if (!xhci_running(port->xhci)) {2622
xhci_event(port->xhci, &ev, 0);
2625
static void xhci_port_update(XHCIPort *port, int is_detach)
2627
uint32_t pls = PLS_RX_DETECT;
2630
port->portsc = PORTSC_PP;
2631
if (!is_detach && xhci_port_have_device(port)) {2632
port->portsc |= PORTSC_CCS;
2633
switch (port->uport->dev->speed) {2635
port->portsc |= PORTSC_SPEED_LOW;
2638
case USB_SPEED_FULL:
2639
port->portsc |= PORTSC_SPEED_FULL;
2642
case USB_SPEED_HIGH:
2643
port->portsc |= PORTSC_SPEED_HIGH;
2646
case USB_SPEED_SUPER:
2647
port->portsc |= PORTSC_SPEED_SUPER;
2648
port->portsc |= PORTSC_PED;
2653
set_field(&port->portsc, pls, PORTSC_PLS);
2654
trace_usb_xhci_port_link(port->portnr, pls);
2655
xhci_port_notify(port, PORTSC_CSC);
2658
static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2660
trace_usb_xhci_port_reset(port->portnr, warm_reset);
2662
if (!xhci_port_have_device(port)) {2666
usb_device_reset(port->uport->dev);
2668
switch (port->uport->dev->speed) {2669
case USB_SPEED_SUPER:
2671
port->portsc |= PORTSC_WRC;
2675
case USB_SPEED_FULL:
2676
case USB_SPEED_HIGH:
2677
set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2678
trace_usb_xhci_port_link(port->portnr, PLS_U0);
2679
port->portsc |= PORTSC_PED;
2683
port->portsc &= ~PORTSC_PR;
2684
xhci_port_notify(port, PORTSC_PRC);
2687
static void xhci_reset(DeviceState *dev)
2689
XHCIState *xhci = XHCI(dev);
2692
trace_usb_xhci_reset();
2693
if (!(xhci->usbsts & USBSTS_HCH)) {2694
DPRINTF("xhci: reset while running!\n");2698
xhci->usbsts = USBSTS_HCH;
2701
xhci->crcr_high = 0;
2702
xhci->dcbaap_low = 0;
2703
xhci->dcbaap_high = 0;
2706
for (i = 0; i < xhci->numslots; i++) {2707
xhci_disable_slot(xhci, i+1);
2710
for (i = 0; i < xhci->numports; i++) {2711
xhci_port_update(xhci->ports + i, 0);
2714
for (i = 0; i < xhci->numintrs; i++) {2715
xhci->intr[i].iman = 0;
2716
xhci->intr[i].imod = 0;
2717
xhci->intr[i].erstsz = 0;
2718
xhci->intr[i].erstba_low = 0;
2719
xhci->intr[i].erstba_high = 0;
2720
xhci->intr[i].erdp_low = 0;
2721
xhci->intr[i].erdp_high = 0;
2723
xhci->intr[i].er_ep_idx = 0;
2724
xhci->intr[i].er_pcs = 1;
2725
xhci->intr[i].ev_buffer_put = 0;
2726
xhci->intr[i].ev_buffer_get = 0;
2729
xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2730
xhci_mfwrap_update(xhci);
2733
static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2735
XHCIState *xhci = ptr;
2739
case 0x00: /* HCIVERSION, CAPLENGTH */
2740
ret = 0x01000000 | LEN_CAP;
2742
case 0x04: /* HCSPARAMS 1 */
2743
ret = ((xhci->numports_2+xhci->numports_3)<<24)
2744
| (xhci->numintrs<<8) | xhci->numslots;
2746
case 0x08: /* HCSPARAMS 2 */
2749
case 0x0c: /* HCSPARAMS 3 */
2752
case 0x10: /* HCCPARAMS */
2753
if (sizeof(dma_addr_t) == 4) {2754
ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
2756
ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
2759
case 0x14: /* DBOFF */
2762
case 0x18: /* RTSOFF */
2766
/* extended capabilities */
2767
case 0x20: /* Supported Protocol:00 */
2768
ret = 0x02000402; /* USB 2.0 */
2770
case 0x24: /* Supported Protocol:04 */
2771
ret = 0x20425355; /* "USB " */
2773
case 0x28: /* Supported Protocol:08 */
2774
ret = (xhci->numports_2 << 8) | (xhci->numports_3 + 1);
2776
case 0x2c: /* Supported Protocol:0c */
2777
ret = 0x00000000; /* reserved */
2779
case 0x30: /* Supported Protocol:00 */
2780
ret = 0x03000002; /* USB 3.0 */
2782
case 0x34: /* Supported Protocol:04 */
2783
ret = 0x20425355; /* "USB " */
2785
case 0x38: /* Supported Protocol:08 */
2786
ret = (xhci->numports_3 << 8) | 1;
2788
case 0x3c: /* Supported Protocol:0c */
2789
ret = 0x00000000; /* reserved */
2792
trace_usb_xhci_unimplemented("cap read", reg);2796
trace_usb_xhci_cap_read(reg, ret);
2800
static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
2802
XHCIPort *port = ptr;
2806
case 0x00: /* PORTSC */
2809
case 0x04: /* PORTPMSC */
2810
case 0x08: /* PORTLI */
2813
case 0x0c: /* reserved */
2815
trace_usb_xhci_unimplemented("port read", reg);2819
trace_usb_xhci_port_read(port->portnr, reg, ret);
2823
static void xhci_port_write(void *ptr, hwaddr reg,
2824
uint64_t val, unsigned size)
2826
XHCIPort *port = ptr;
2827
uint32_t portsc, notify;
2829
trace_usb_xhci_port_write(port->portnr, reg, val);
2832
case 0x00: /* PORTSC */
2833
/* write-1-to-start bits */
2834
if (val & PORTSC_WPR) {2835
xhci_port_reset(port, true);
2838
if (val & PORTSC_PR) {2839
xhci_port_reset(port, false);
2843
portsc = port->portsc;
2845
/* write-1-to-clear bits*/
2846
portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2847
PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2848
if (val & PORTSC_LWS) {2849
/* overwrite PLS only when LWS=1 */
2850
uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
2851
uint32_t new_pls = get_field(val, PORTSC_PLS);
2854
if (old_pls != PLS_U0) {2855
set_field(&portsc, new_pls, PORTSC_PLS);
2856
trace_usb_xhci_port_link(port->portnr, new_pls);
2857
notify = PORTSC_PLC;
2861
if (old_pls < PLS_U3) {2862
set_field(&portsc, new_pls, PORTSC_PLS);
2863
trace_usb_xhci_port_link(port->portnr, new_pls);
2867
/* windows does this for some reason, don't spam stderr */
2870
DPRINTF("%s: ignore pls write (old %d, new %d)\n",2871
__func__, old_pls, new_pls);
2875
/* read/write bits */
2876
portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2877
portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2878
port->portsc = portsc;
2880
xhci_port_notify(port, notify);
2883
case 0x04: /* PORTPMSC */
2884
case 0x08: /* PORTLI */
2886
trace_usb_xhci_unimplemented("port write", reg);2890
static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
2892
XHCIState *xhci = ptr;
2896
case 0x00: /* USBCMD */
2899
case 0x04: /* USBSTS */
2902
case 0x08: /* PAGESIZE */
2905
case 0x14: /* DNCTRL */
2908
case 0x18: /* CRCR low */
2909
ret = xhci->crcr_low & ~0xe;
2911
case 0x1c: /* CRCR high */
2912
ret = xhci->crcr_high;
2914
case 0x30: /* DCBAAP low */
2915
ret = xhci->dcbaap_low;
2917
case 0x34: /* DCBAAP high */
2918
ret = xhci->dcbaap_high;
2920
case 0x38: /* CONFIG */
2924
trace_usb_xhci_unimplemented("oper read", reg);2928
trace_usb_xhci_oper_read(reg, ret);
2932
static void xhci_oper_write(void *ptr, hwaddr reg,
2933
uint64_t val, unsigned size)
2935
XHCIState *xhci = XHCI(ptr);
2937
trace_usb_xhci_oper_write(reg, val);
2940
case 0x00: /* USBCMD */
2941
if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {2943
} else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {2946
if (val & USBCMD_CSS) {2948
xhci->usbsts &= ~USBSTS_SRE;
2950
if (val & USBCMD_CRS) {2952
xhci->usbsts |= USBSTS_SRE;
2954
xhci->usbcmd = val & 0xc0f;
2955
xhci_mfwrap_update(xhci);
2956
if (val & USBCMD_HCRST) {2957
xhci_reset(DEVICE(xhci));
2959
xhci_intr_update(xhci, 0);
2962
case 0x04: /* USBSTS */
2963
/* these bits are write-1-to-clear */
2964
xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2965
xhci_intr_update(xhci, 0);
2968
case 0x14: /* DNCTRL */
2969
xhci->dnctrl = val & 0xffff;
2971
case 0x18: /* CRCR low */
2972
xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2974
case 0x1c: /* CRCR high */
2975
xhci->crcr_high = val;
2976
if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {2977
XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};2978
xhci->crcr_low &= ~CRCR_CRR;
2979
xhci_event(xhci, &event, 0);
2980
DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);2982
dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2983
xhci_ring_init(xhci, &xhci->cmd_ring, base);
2985
xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2987
case 0x30: /* DCBAAP low */
2988
xhci->dcbaap_low = val & 0xffffffc0;
2990
case 0x34: /* DCBAAP high */
2991
xhci->dcbaap_high = val;
2993
case 0x38: /* CONFIG */
2994
xhci->config = val & 0xff;
2997
trace_usb_xhci_unimplemented("oper write", reg);3001
static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3004
XHCIState *xhci = ptr;
3009
case 0x00: /* MFINDEX */
3010
ret = xhci_mfindex_get(xhci) & 0x3fff;
3013
trace_usb_xhci_unimplemented("runtime read", reg);3017
int v = (reg - 0x20) / 0x20;
3018
XHCIInterrupter *intr = &xhci->intr[v];
3019
switch (reg & 0x1f) {3020
case 0x00: /* IMAN */
3023
case 0x04: /* IMOD */
3026
case 0x08: /* ERSTSZ */
3029
case 0x10: /* ERSTBA low */
3030
ret = intr->erstba_low;
3032
case 0x14: /* ERSTBA high */
3033
ret = intr->erstba_high;
3035
case 0x18: /* ERDP low */
3036
ret = intr->erdp_low;
3038
case 0x1c: /* ERDP high */
3039
ret = intr->erdp_high;
3044
trace_usb_xhci_runtime_read(reg, ret);
3048
static void xhci_runtime_write(void *ptr, hwaddr reg,
3049
uint64_t val, unsigned size)
3051
XHCIState *xhci = ptr;
3052
XHCIInterrupter *intr;
3055
trace_usb_xhci_runtime_write(reg, val);
3058
trace_usb_xhci_unimplemented("runtime write", reg);3061
v = (reg - 0x20) / 0x20;
3062
intr = &xhci->intr[v];
3064
switch (reg & 0x1f) {3065
case 0x00: /* IMAN */
3066
if (val & IMAN_IP) {3067
intr->iman &= ~IMAN_IP;
3069
intr->iman &= ~IMAN_IE;
3070
intr->iman |= val & IMAN_IE;
3071
xhci_intr_update(xhci, v);
3073
case 0x04: /* IMOD */
3076
case 0x08: /* ERSTSZ */
3077
intr->erstsz = val & 0xffff;
3079
case 0x10: /* ERSTBA low */
3080
if (xhci->nec_quirks) {3081
/* NEC driver bug: it doesn't align this to 64 bytes */
3082
intr->erstba_low = val & 0xfffffff0;
3084
intr->erstba_low = val & 0xffffffc0;
3087
case 0x14: /* ERSTBA high */
3088
intr->erstba_high = val;
3089
xhci_er_reset(xhci, v);
3091
case 0x18: /* ERDP low */
3092
if (val & ERDP_EHB) {3093
intr->erdp_low &= ~ERDP_EHB;
3095
intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3096
if (val & ERDP_EHB) {3097
dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
3098
unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE;
3099
if (erdp >= intr->er_start &&
3100
erdp < (intr->er_start + TRB_SIZE * intr->er_size) &&
3101
dp_idx != intr->er_ep_idx) {3102
xhci_intr_raise(xhci, v);
3106
case 0x1c: /* ERDP high */
3107
intr->erdp_high = val;
3110
trace_usb_xhci_unimplemented("oper write", reg);3114
static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3117
/* doorbells always read as 0 */
3118
trace_usb_xhci_doorbell_read(reg, 0);
3122
static void xhci_doorbell_write(void *ptr, hwaddr reg,
3123
uint64_t val, unsigned size)
3125
XHCIState *xhci = ptr;
3126
unsigned int epid, streamid;
3128
trace_usb_xhci_doorbell_write(reg, val);
3130
if (!xhci_running(xhci)) {3131
DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");3139
xhci_process_commands(xhci);
3141
DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",3146
streamid = (val >> 16) & 0xffff;
3147
if (reg > xhci->numslots) {3148
DPRINTF("xhci: bad doorbell %d\n", (int)reg);3149
} else if (epid == 0 || epid > 31) {3150
DPRINTF("xhci: bad doorbell %d write: 0x%x\n",3151
(int)reg, (uint32_t)val);
3153
xhci_kick_ep(xhci, reg, epid, streamid);
3158
static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3164
static const MemoryRegionOps xhci_cap_ops = {3165
.read = xhci_cap_read,
3166
.write = xhci_cap_write,
3167
.valid.min_access_size = 1,
3168
.valid.max_access_size = 4,
3169
.impl.min_access_size = 4,
3170
.impl.max_access_size = 4,
3171
.endianness = DEVICE_LITTLE_ENDIAN,
3174
static const MemoryRegionOps xhci_oper_ops = {3175
.read = xhci_oper_read,
3176
.write = xhci_oper_write,
3177
.valid.min_access_size = 4,
3178
.valid.max_access_size = sizeof(dma_addr_t),
3179
.endianness = DEVICE_LITTLE_ENDIAN,
3182
static const MemoryRegionOps xhci_port_ops = {3183
.read = xhci_port_read,
3184
.write = xhci_port_write,
3185
.valid.min_access_size = 4,
3186
.valid.max_access_size = 4,
3187
.endianness = DEVICE_LITTLE_ENDIAN,
3190
static const MemoryRegionOps xhci_runtime_ops = {3191
.read = xhci_runtime_read,
3192
.write = xhci_runtime_write,
3193
.valid.min_access_size = 4,
3194
.valid.max_access_size = sizeof(dma_addr_t),
3195
.endianness = DEVICE_LITTLE_ENDIAN,
3198
static const MemoryRegionOps xhci_doorbell_ops = {3199
.read = xhci_doorbell_read,
3200
.write = xhci_doorbell_write,
3201
.valid.min_access_size = 4,
3202
.valid.max_access_size = 4,
3203
.endianness = DEVICE_LITTLE_ENDIAN,
3206
static void xhci_attach(USBPort *usbport)
3208
XHCIState *xhci = usbport->opaque;
3209
XHCIPort *port = xhci_lookup_port(xhci, usbport);
3211
xhci_port_update(port, 0);
3214
static void xhci_detach(USBPort *usbport)
3216
XHCIState *xhci = usbport->opaque;
3217
XHCIPort *port = xhci_lookup_port(xhci, usbport);
3219
xhci_detach_slot(xhci, usbport);
3220
xhci_port_update(port, 1);
3223
static void xhci_wakeup(USBPort *usbport)
3225
XHCIState *xhci = usbport->opaque;
3226
XHCIPort *port = xhci_lookup_port(xhci, usbport);
3229
if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {3232
set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3233
xhci_port_notify(port, PORTSC_PLC);
3236
static void xhci_complete(USBPort *port, USBPacket *packet)
3238
XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3240
if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {3241
xhci_ep_nuke_one_xfer(xfer, 0);
3244
xhci_try_complete_packet(xfer);
3245
xhci_kick_epctx(xfer->epctx, xfer->streamid);
3246
if (xfer->complete) {3247
xhci_ep_free_xfer(xfer);
3251
static void xhci_child_detach(USBPort *uport, USBDevice *child)
3253
USBBus *bus = usb_bus_from_device(child);
3254
XHCIState *xhci = container_of(bus, XHCIState, bus);
3256
xhci_detach_slot(xhci, child->port);
3259
static USBPortOps xhci_uport_ops = {3260
.attach = xhci_attach,
3261
.detach = xhci_detach,
3262
.wakeup = xhci_wakeup,
3263
.complete = xhci_complete,
3264
.child_detach = xhci_child_detach,
3267
static int xhci_find_epid(USBEndpoint *ep)
3272
if (ep->pid == USB_TOKEN_IN) {3273
return ep->nr * 2 + 1;
3279
static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx)
3287
uport = epctx->xhci->slots[epctx->slotid - 1].uport;
3288
if (!uport || !uport->dev) {3291
token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT;
3292
return usb_ep_get(uport->dev, token, epctx->epid >> 1);
3295
static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3296
unsigned int stream)
3298
XHCIState *xhci = container_of(bus, XHCIState, bus);
3301
DPRINTF("%s\n", __func__);3302
slotid = ep->dev->addr;
3303
if (slotid == 0 || slotid > xhci->numslots ||
3304
!xhci->slots[slotid - 1].enabled) {3305
DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);3308
xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3311
static USBBusOps xhci_bus_ops = {3312
.wakeup_endpoint = xhci_wakeup_endpoint,
3315
static void usb_xhci_init(XHCIState *xhci)
3318
unsigned int i, usbports, speedmask;
3320
xhci->usbsts = USBSTS_HCH;
3322
if (xhci->numports_2 > XHCI_MAXPORTS_2) {3323
xhci->numports_2 = XHCI_MAXPORTS_2;
3325
if (xhci->numports_3 > XHCI_MAXPORTS_3) {3326
xhci->numports_3 = XHCI_MAXPORTS_3;
3328
usbports = MAX(xhci->numports_2, xhci->numports_3);
3329
xhci->numports = xhci->numports_2 + xhci->numports_3;
3331
usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, xhci->hostOpaque);
3333
for (i = 0; i < usbports; i++) {3335
if (i < xhci->numports_2) {3336
port = &xhci->ports[i + xhci->numports_3];
3337
port->portnr = i + 1 + xhci->numports_3;
3338
port->uport = &xhci->uports[i];
3340
USB_SPEED_MASK_LOW |
3341
USB_SPEED_MASK_FULL |
3342
USB_SPEED_MASK_HIGH;
3343
assert(i < XHCI_MAXPORTS);
3344
snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3345
speedmask |= port->speedmask;
3347
if (i < xhci->numports_3) {3348
port = &xhci->ports[i];
3349
port->portnr = i + 1;
3350
port->uport = &xhci->uports[i];
3351
port->speedmask = USB_SPEED_MASK_SUPER;
3352
assert(i < XHCI_MAXPORTS);
3353
snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3354
speedmask |= port->speedmask;
3356
usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3357
&xhci_uport_ops, speedmask);
3361
static void usb_xhci_realize(DeviceState *dev, Error **errp)
3365
XHCIState *xhci = XHCI(dev);
3367
if (xhci->numintrs > XHCI_MAXINTRS) {3368
xhci->numintrs = XHCI_MAXINTRS;
3370
while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */3373
if (xhci->numintrs < 1) {3376
if (xhci->numslots > XHCI_MAXSLOTS) {3377
xhci->numslots = XHCI_MAXSLOTS;
3379
if (xhci->numslots < 1) {3382
if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) {3383
xhci->max_pstreams_mask = 7; /* == 256 primary streams */
3385
xhci->max_pstreams_mask = 0;
3388
usb_xhci_init(xhci);
3389
xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3391
memory_region_init(&xhci->mem, OBJECT(dev), "xhci", XHCI_LEN_REGS);
3392
memory_region_init_io(&xhci->mem_cap, OBJECT(dev), &xhci_cap_ops, xhci,
3393
"capabilities", LEN_CAP);
3394
memory_region_init_io(&xhci->mem_oper, OBJECT(dev), &xhci_oper_ops, xhci,
3395
"operational", 0x400);
3396
memory_region_init_io(&xhci->mem_runtime, OBJECT(dev), &xhci_runtime_ops,
3397
xhci, "runtime", LEN_RUNTIME);
3398
memory_region_init_io(&xhci->mem_doorbell, OBJECT(dev), &xhci_doorbell_ops,
3399
xhci, "doorbell", LEN_DOORBELL);
3401
memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3402
memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3403
memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3404
memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3406
for (i = 0; i < xhci->numports; i++) {3407
XHCIPort *port = &xhci->ports[i];
3408
uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3410
memory_region_init_io(&port->mem, OBJECT(dev), &xhci_port_ops, port,
3412
memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3416
static void usb_xhci_unrealize(DeviceState *dev)
3419
XHCIState *xhci = XHCI(dev);
3421
trace_usb_xhci_exit();
3423
for (i = 0; i < xhci->numslots; i++) {3424
xhci_disable_slot(xhci, i + 1);
3427
if (xhci->mfwrap_timer) {3428
timer_free(xhci->mfwrap_timer);
3429
xhci->mfwrap_timer = NULL;
3432
memory_region_del_subregion(&xhci->mem, &xhci->mem_cap);
3433
memory_region_del_subregion(&xhci->mem, &xhci->mem_oper);
3434
memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime);
3435
memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell);
3437
for (i = 0; i < xhci->numports; i++) {3438
XHCIPort *port = &xhci->ports[i];
3439
memory_region_del_subregion(&xhci->mem, &port->mem);
3442
usb_bus_release(&xhci->bus);
3445
static int usb_xhci_post_load(void *opaque, int version_id)
3447
XHCIState *xhci = opaque;
3449
XHCIEPContext *epctx;
3450
dma_addr_t dcbaap, pctx;
3451
uint32_t slot_ctx[4];
3453
int slotid, epid, state;
3456
dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3458
for (slotid = 1; slotid <= xhci->numslots; slotid++) {3459
slot = &xhci->slots[slotid-1];
3460
if (!slot->addressed) {3463
ldq_le_dma(xhci->as, dcbaap + 8 * slotid, &addr, MEMTXATTRS_UNSPECIFIED);
3464
slot->ctx = xhci_mask64(addr);
3466
xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3467
slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3469
/* should not happen, but may trigger on guest bugs */
3471
slot->addressed = 0;
3474
assert(slot->uport && slot->uport->dev);
3476
for (epid = 1; epid <= 31; epid++) {3477
pctx = slot->ctx + 32 * epid;
3478
xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3479
state = ep_ctx[0] & EP_STATE_MASK;
3480
if (state == EP_DISABLED) {3483
epctx = xhci_alloc_epctx(xhci, slotid, epid);
3484
slot->eps[epid-1] = epctx;
3485
xhci_init_epctx(epctx, pctx, ep_ctx);
3486
epctx->state = state;
3487
if (state == EP_RUNNING) {3488
/* kick endpoint after vmload is finished */
3489
timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3496
static const VMStateDescription vmstate_xhci_ring = {3497
.name = "xhci-ring",
3499
.fields = (const VMStateField[]) {3500
VMSTATE_UINT64(dequeue, XHCIRing),
3501
VMSTATE_BOOL(ccs, XHCIRing),
3502
VMSTATE_END_OF_LIST()
3506
static const VMStateDescription vmstate_xhci_port = {3507
.name = "xhci-port",
3509
.fields = (const VMStateField[]) {3510
VMSTATE_UINT32(portsc, XHCIPort),
3511
VMSTATE_END_OF_LIST()
3515
static const VMStateDescription vmstate_xhci_slot = {3516
.name = "xhci-slot",
3518
.fields = (const VMStateField[]) {3519
VMSTATE_BOOL(enabled, XHCISlot),
3520
VMSTATE_BOOL(addressed, XHCISlot),
3521
VMSTATE_END_OF_LIST()
3525
static const VMStateDescription vmstate_xhci_event = {3526
.name = "xhci-event",
3528
.fields = (const VMStateField[]) {3529
VMSTATE_UINT32(type, XHCIEvent),
3530
VMSTATE_UINT32(ccode, XHCIEvent),
3531
VMSTATE_UINT64(ptr, XHCIEvent),
3532
VMSTATE_UINT32(length, XHCIEvent),
3533
VMSTATE_UINT32(flags, XHCIEvent),
3534
VMSTATE_UINT8(slotid, XHCIEvent),
3535
VMSTATE_UINT8(epid, XHCIEvent),
3536
VMSTATE_END_OF_LIST()
3540
static bool xhci_er_full(void *opaque, int version_id)
3545
static const VMStateDescription vmstate_xhci_intr = {3546
.name = "xhci-intr",
3548
.fields = (const VMStateField[]) {3550
VMSTATE_UINT32(iman, XHCIInterrupter),
3551
VMSTATE_UINT32(imod, XHCIInterrupter),
3552
VMSTATE_UINT32(erstsz, XHCIInterrupter),
3553
VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3554
VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3555
VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3556
VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3559
VMSTATE_BOOL(msix_used, XHCIInterrupter),
3560
VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3561
VMSTATE_UINT64(er_start, XHCIInterrupter),
3562
VMSTATE_UINT32(er_size, XHCIInterrupter),
3563
VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3565
/* event queue (used if ring is full) */
3566
VMSTATE_BOOL(er_full_unused, XHCIInterrupter),
3567
VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3568
VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3569
VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3571
vmstate_xhci_event, XHCIEvent),
3573
VMSTATE_END_OF_LIST()
3577
const VMStateDescription vmstate_xhci = {3578
.name = "xhci-core",
3580
.post_load = usb_xhci_post_load,
3581
.fields = (const VMStateField[]) {3582
VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3583
vmstate_xhci_port, XHCIPort),
3584
VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3585
vmstate_xhci_slot, XHCISlot),
3586
VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3587
vmstate_xhci_intr, XHCIInterrupter),
3589
/* Operational Registers */
3590
VMSTATE_UINT32(usbcmd, XHCIState),
3591
VMSTATE_UINT32(usbsts, XHCIState),
3592
VMSTATE_UINT32(dnctrl, XHCIState),
3593
VMSTATE_UINT32(crcr_low, XHCIState),
3594
VMSTATE_UINT32(crcr_high, XHCIState),
3595
VMSTATE_UINT32(dcbaap_low, XHCIState),
3596
VMSTATE_UINT32(dcbaap_high, XHCIState),
3597
VMSTATE_UINT32(config, XHCIState),
3599
/* Runtime Registers & state */
3600
VMSTATE_INT64(mfindex_start, XHCIState),
3601
VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState),
3602
VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3604
VMSTATE_END_OF_LIST()
3608
static Property xhci_properties[] = {3609
DEFINE_PROP_BIT("streams", XHCIState, flags,3610
XHCI_FLAG_ENABLE_STREAMS, true),
3611
DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),3612
DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),3613
DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE,3615
DEFINE_PROP_END_OF_LIST(),
3618
static void xhci_class_init(ObjectClass *klass, void *data)
3620
DeviceClass *dc = DEVICE_CLASS(klass);
3622
dc->realize = usb_xhci_realize;
3623
dc->unrealize = usb_xhci_unrealize;
3624
dc->reset = xhci_reset;
3625
device_class_set_props(dc, xhci_properties);
3626
dc->user_creatable = false;
3629
static const TypeInfo xhci_info = {3631
.parent = TYPE_DEVICE,
3632
.instance_size = sizeof(XHCIState),
3633
.class_init = xhci_class_init,
3636
static void xhci_register_types(void)
3638
type_register_static(&xhci_info);
3641
type_init(xhci_register_types)