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* QEMU USB EHCI Emulation
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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* You should have received a copy of the GNU Lesser General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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#include "qemu/osdep.h"
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#include "hw/qdev-properties.h"
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#include "hw/usb/hcd-ehci.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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static const VMStateDescription vmstate_ehci_sysbus = {
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.name = "ehci-sysbus",
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState),
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static Property ehci_sysbus_properties[] = {
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DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128),
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DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable,
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DEFINE_PROP_END_OF_LIST(),
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static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp)
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SysBusDevice *d = SYS_BUS_DEVICE(dev);
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EHCISysBusState *i = SYS_BUS_EHCI(dev);
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EHCIState *s = &i->ehci;
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usb_ehci_realize(s, dev, errp);
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sysbus_init_irq(d, &s->irq);
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static void usb_ehci_sysbus_reset(DeviceState *dev)
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SysBusDevice *d = SYS_BUS_DEVICE(dev);
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EHCISysBusState *i = SYS_BUS_EHCI(d);
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EHCIState *s = &i->ehci;
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static void ehci_sysbus_init(Object *obj)
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SysBusDevice *d = SYS_BUS_DEVICE(obj);
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EHCISysBusState *i = SYS_BUS_EHCI(obj);
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SysBusEHCIClass *sec = SYS_BUS_EHCI_GET_CLASS(obj);
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EHCIState *s = &i->ehci;
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s->capsbase = sec->capsbase;
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s->opregbase = sec->opregbase;
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s->portscbase = sec->portscbase;
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s->portnr = sec->portnr;
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s->as = &address_space_memory;
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usb_ehci_init(s, DEVICE(obj));
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sysbus_init_mmio(d, &s->mem);
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static void ehci_sysbus_finalize(Object *obj)
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EHCISysBusState *i = SYS_BUS_EHCI(obj);
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EHCIState *s = &i->ehci;
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static void ehci_sysbus_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(klass);
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sec->portscbase = 0x44;
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sec->portnr = EHCI_PORTS;
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dc->realize = usb_ehci_sysbus_realize;
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dc->vmsd = &vmstate_ehci_sysbus;
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device_class_set_props(dc, ehci_sysbus_properties);
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dc->reset = usb_ehci_sysbus_reset;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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static const TypeInfo ehci_type_info = {
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.name = TYPE_SYS_BUS_EHCI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(EHCISysBusState),
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.instance_init = ehci_sysbus_init,
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.instance_finalize = ehci_sysbus_finalize,
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.class_init = ehci_sysbus_class_init,
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.class_size = sizeof(SysBusEHCIClass),
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static void ehci_platform_class_init(ObjectClass *oc, void *data)
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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sec->opregbase = 0x20;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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static const TypeInfo ehci_platform_type_info = {
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.name = TYPE_PLATFORM_EHCI,
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.parent = TYPE_SYS_BUS_EHCI,
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.class_init = ehci_platform_class_init,
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static void ehci_exynos4210_class_init(ObjectClass *oc, void *data)
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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sec->opregbase = 0x10;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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static const TypeInfo ehci_exynos4210_type_info = {
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.name = TYPE_EXYNOS4210_EHCI,
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.parent = TYPE_SYS_BUS_EHCI,
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.class_init = ehci_exynos4210_class_init,
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static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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sec->opregbase = 0x10;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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static const TypeInfo ehci_aw_h3_type_info = {
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.name = TYPE_AW_H3_EHCI,
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.parent = TYPE_SYS_BUS_EHCI,
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.class_init = ehci_aw_h3_class_init,
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static void ehci_npcm7xx_class_init(ObjectClass *oc, void *data)
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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sec->opregbase = 0x10;
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sec->portscbase = 0x44;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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static const TypeInfo ehci_npcm7xx_type_info = {
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.name = TYPE_NPCM7XX_EHCI,
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.parent = TYPE_SYS_BUS_EHCI,
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.class_init = ehci_npcm7xx_class_init,
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static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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sec->capsbase = 0x100;
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sec->opregbase = 0x140;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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static const TypeInfo ehci_tegra2_type_info = {
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.name = TYPE_TEGRA2_EHCI,
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.parent = TYPE_SYS_BUS_EHCI,
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.class_init = ehci_tegra2_class_init,
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static void ehci_ppc4xx_init(Object *o)
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EHCISysBusState *s = SYS_BUS_EHCI(o);
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s->ehci.companion_enable = true;
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static void ehci_ppc4xx_class_init(ObjectClass *oc, void *data)
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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sec->opregbase = 0x10;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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static const TypeInfo ehci_ppc4xx_type_info = {
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.name = TYPE_PPC4xx_EHCI,
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.parent = TYPE_SYS_BUS_EHCI,
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.class_init = ehci_ppc4xx_class_init,
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.instance_init = ehci_ppc4xx_init,
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* Faraday FUSBH200 USB 2.0 EHCI
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* @FUSBH200_REG_EOF_ASTR: EOF/Async. Sleep Timer Register
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* @FUSBH200_REG_BMCSR: Bus Monitor Control/Status Register
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enum FUSBH200EHCIRegs {
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FUSBH200_REG_EOF_ASTR = 0x34,
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FUSBH200_REG_BMCSR = 0x40,
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static uint64_t fusbh200_ehci_read(void *opaque, hwaddr addr, unsigned size)
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EHCIState *s = opaque;
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hwaddr off = s->opregbase + s->portscbase + 4 * s->portnr + addr;
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case FUSBH200_REG_EOF_ASTR:
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case FUSBH200_REG_BMCSR:
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/* High-Speed, VBUS valid, interrupt level-high active */
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return (2 << 9) | (1 << 8) | (1 << 3);
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static void fusbh200_ehci_write(void *opaque, hwaddr addr, uint64_t val,
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static const MemoryRegionOps fusbh200_ehci_mmio_ops = {
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.read = fusbh200_ehci_read,
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.write = fusbh200_ehci_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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static void fusbh200_ehci_init(Object *obj)
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EHCISysBusState *i = SYS_BUS_EHCI(obj);
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FUSBH200EHCIState *f = FUSBH200_EHCI(obj);
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EHCIState *s = &i->ehci;
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memory_region_init_io(&f->mem_vendor, OBJECT(f), &fusbh200_ehci_mmio_ops, s,
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memory_region_add_subregion(&s->mem,
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s->opregbase + s->portscbase + 4 * s->portnr,
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static void fusbh200_ehci_class_init(ObjectClass *oc, void *data)
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SysBusEHCIClass *sec = SYS_BUS_EHCI_CLASS(oc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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sec->opregbase = 0x10;
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sec->portscbase = 0x20;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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static const TypeInfo ehci_fusbh200_type_info = {
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.name = TYPE_FUSBH200_EHCI,
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.parent = TYPE_SYS_BUS_EHCI,
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.instance_size = sizeof(FUSBH200EHCIState),
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.instance_init = fusbh200_ehci_init,
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.class_init = fusbh200_ehci_class_init,
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static void ehci_sysbus_register_types(void)
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type_register_static(&ehci_type_info);
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type_register_static(&ehci_platform_type_info);
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type_register_static(&ehci_exynos4210_type_info);
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type_register_static(&ehci_aw_h3_type_info);
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type_register_static(&ehci_npcm7xx_type_info);
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type_register_static(&ehci_tegra2_type_info);
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type_register_static(&ehci_ppc4xx_type_info);
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type_register_static(&ehci_fusbh200_type_info);
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type_init(ehci_sysbus_register_types)