qemu

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/*
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 * Analog Devices ADM1266 Cascadable Super Sequencer with Margin Control and
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 * Fault Recording with PMBus
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 *
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 * https://www.analog.com/media/en/technical-documentation/data-sheets/adm1266.pdf
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 *
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 * Copyright 2023 Google LLC
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 *
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 */
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#include "qemu/osdep.h"
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#include "hw/i2c/pmbus_device.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define TYPE_ADM1266 "adm1266"
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OBJECT_DECLARE_SIMPLE_TYPE(ADM1266State, ADM1266)
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#define ADM1266_BLACKBOX_CONFIG                 0xD3
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#define ADM1266_PDIO_CONFIG                     0xD4
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#define ADM1266_READ_STATE                      0xD9
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#define ADM1266_READ_BLACKBOX                   0xDE
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#define ADM1266_SET_RTC                         0xDF
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#define ADM1266_GPIO_SYNC_CONFIGURATION         0xE1
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#define ADM1266_BLACKBOX_INFORMATION            0xE6
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#define ADM1266_PDIO_STATUS                     0xE9
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#define ADM1266_GPIO_STATUS                     0xEA
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/* Defaults */
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#define ADM1266_OPERATION_DEFAULT               0x80
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#define ADM1266_CAPABILITY_DEFAULT              0xA0
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#define ADM1266_CAPABILITY_NO_PEC               0x20
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#define ADM1266_PMBUS_REVISION_DEFAULT          0x22
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#define ADM1266_MFR_ID_DEFAULT                  "ADI"
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#define ADM1266_MFR_ID_DEFAULT_LEN              32
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#define ADM1266_MFR_MODEL_DEFAULT               "ADM1266-A1"
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#define ADM1266_MFR_MODEL_DEFAULT_LEN           32
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#define ADM1266_MFR_REVISION_DEFAULT            "25"
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#define ADM1266_MFR_REVISION_DEFAULT_LEN        8
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#define ADM1266_NUM_PAGES               17
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/**
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 * PAGE Index
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 * Page 0 VH1.
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 * Page 1 VH2.
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 * Page 2 VH3.
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 * Page 3 VH4.
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 * Page 4 VP1.
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 * Page 5 VP2.
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 * Page 6 VP3.
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 * Page 7 VP4.
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 * Page 8 VP5.
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 * Page 9 VP6.
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 * Page 10 VP7.
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 * Page 11 VP8.
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 * Page 12 VP9.
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 * Page 13 VP10.
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 * Page 14 VP11.
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 * Page 15 VP12.
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 * Page 16 VP13.
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 */
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typedef struct ADM1266State {
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    PMBusDevice parent;
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    char mfr_id[32];
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    char mfr_model[32];
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    char mfr_rev[8];
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} ADM1266State;
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static const uint8_t adm1266_ic_device_id[] = {0x03, 0x41, 0x12, 0x66};
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static const uint8_t adm1266_ic_device_rev[] = {0x08, 0x01, 0x08, 0x07, 0x0,
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                                                0x0, 0x07, 0x41, 0x30};
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static void adm1266_exit_reset(Object *obj, ResetType type)
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{
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    ADM1266State *s = ADM1266(obj);
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    PMBusDevice *pmdev = PMBUS_DEVICE(obj);
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    pmdev->page = 0;
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    pmdev->capability = ADM1266_CAPABILITY_NO_PEC;
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    for (int i = 0; i < ADM1266_NUM_PAGES; i++) {
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        pmdev->pages[i].operation = ADM1266_OPERATION_DEFAULT;
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        pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT;
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        pmdev->pages[i].vout_mode = 0;
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        pmdev->pages[i].read_vout = pmbus_data2linear_mode(12, 0);
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        pmdev->pages[i].vout_margin_high = pmbus_data2linear_mode(15, 0);
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        pmdev->pages[i].vout_margin_low = pmbus_data2linear_mode(3, 0);
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        pmdev->pages[i].vout_ov_fault_limit = pmbus_data2linear_mode(16, 0);
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        pmdev->pages[i].revision = ADM1266_PMBUS_REVISION_DEFAULT;
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    }
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    strncpy(s->mfr_id, ADM1266_MFR_ID_DEFAULT, 4);
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    strncpy(s->mfr_model, ADM1266_MFR_MODEL_DEFAULT, 11);
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    strncpy(s->mfr_rev, ADM1266_MFR_REVISION_DEFAULT, 3);
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}
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static uint8_t adm1266_read_byte(PMBusDevice *pmdev)
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{
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    ADM1266State *s = ADM1266(pmdev);
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    switch (pmdev->code) {
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    case PMBUS_MFR_ID:                    /* R/W block */
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        pmbus_send_string(pmdev, s->mfr_id);
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        break;
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    case PMBUS_MFR_MODEL:                 /* R/W block */
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        pmbus_send_string(pmdev, s->mfr_model);
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        break;
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    case PMBUS_MFR_REVISION:              /* R/W block */
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        pmbus_send_string(pmdev, s->mfr_rev);
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        break;
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    case PMBUS_IC_DEVICE_ID:
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        pmbus_send(pmdev, adm1266_ic_device_id, sizeof(adm1266_ic_device_id));
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        break;
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    case PMBUS_IC_DEVICE_REV:
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        pmbus_send(pmdev, adm1266_ic_device_rev, sizeof(adm1266_ic_device_rev));
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        break;
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    default:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: reading from unimplemented register: 0x%02x\n",
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                      __func__, pmdev->code);
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        return 0xFF;
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    }
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    return 0;
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}
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static int adm1266_write_data(PMBusDevice *pmdev, const uint8_t *buf,
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                              uint8_t len)
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{
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    ADM1266State *s = ADM1266(pmdev);
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    switch (pmdev->code) {
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    case PMBUS_MFR_ID:                    /* R/W block */
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        pmbus_receive_block(pmdev, (uint8_t *)s->mfr_id, sizeof(s->mfr_id));
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        break;
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    case PMBUS_MFR_MODEL:                 /* R/W block */
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        pmbus_receive_block(pmdev, (uint8_t *)s->mfr_model,
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                            sizeof(s->mfr_model));
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        break;
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    case PMBUS_MFR_REVISION:               /* R/W block*/
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        pmbus_receive_block(pmdev, (uint8_t *)s->mfr_rev, sizeof(s->mfr_rev));
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        break;
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    case ADM1266_SET_RTC:   /* do nothing */
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        break;
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    default:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: writing to unimplemented register: 0x%02x\n",
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                      __func__, pmdev->code);
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        break;
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    }
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    return 0;
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}
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static void adm1266_get(Object *obj, Visitor *v, const char *name, void *opaque,
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                        Error **errp)
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{
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    uint16_t value;
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    PMBusDevice *pmdev = PMBUS_DEVICE(obj);
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    PMBusVoutMode *mode = (PMBusVoutMode *)&pmdev->pages[0].vout_mode;
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    if (strcmp(name, "vout") == 0) {
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        value = pmbus_linear_mode2data(*(uint16_t *)opaque, mode->exp);
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    } else {
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        value = *(uint16_t *)opaque;
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    }
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    visit_type_uint16(v, name, &value, errp);
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}
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static void adm1266_set(Object *obj, Visitor *v, const char *name, void *opaque,
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                        Error **errp)
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{
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    uint16_t *internal = opaque;
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    uint16_t value;
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    PMBusDevice *pmdev = PMBUS_DEVICE(obj);
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    PMBusVoutMode *mode = (PMBusVoutMode *)&pmdev->pages[0].vout_mode;
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    if (!visit_type_uint16(v, name, &value, errp)) {
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        return;
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    }
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    *internal = pmbus_data2linear_mode(value, mode->exp);
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    pmbus_check_limits(pmdev);
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}
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static const VMStateDescription vmstate_adm1266 = {
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    .name = "ADM1266",
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    .version_id = 0,
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    .minimum_version_id = 0,
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    .fields = (const VMStateField[]){
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        VMSTATE_PMBUS_DEVICE(parent, ADM1266State),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void adm1266_init(Object *obj)
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{
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    PMBusDevice *pmdev = PMBUS_DEVICE(obj);
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    uint64_t flags = PB_HAS_VOUT_MODE | PB_HAS_VOUT | PB_HAS_VOUT_MARGIN |
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                     PB_HAS_VOUT_RATING | PB_HAS_STATUS_MFR_SPECIFIC;
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    for (int i = 0; i < ADM1266_NUM_PAGES; i++) {
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        pmbus_page_config(pmdev, i, flags);
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        object_property_add(obj, "vout[*]", "uint16",
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                            adm1266_get,
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                            adm1266_set, NULL, &pmdev->pages[i].read_vout);
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    }
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}
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static void adm1266_class_init(ObjectClass *klass, void *data)
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{
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    ResettableClass *rc = RESETTABLE_CLASS(klass);
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    PMBusDeviceClass *k = PMBUS_DEVICE_CLASS(klass);
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    dc->desc = "Analog Devices ADM1266 Hot Swap controller";
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    dc->vmsd = &vmstate_adm1266;
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    k->write_data = adm1266_write_data;
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    k->receive_byte = adm1266_read_byte;
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    k->device_num_pages = 17;
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    rc->phases.exit = adm1266_exit_reset;
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}
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static const TypeInfo adm1266_info = {
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    .name = TYPE_ADM1266,
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    .parent = TYPE_PMBUS_DEVICE,
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    .instance_size = sizeof(ADM1266State),
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    .instance_init = adm1266_init,
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    .class_init = adm1266_class_init,
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};
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static void adm1266_register_types(void)
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{
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    type_register_static(&adm1266_info);
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}
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type_init(adm1266_register_types)
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