qemu

1
/*
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 * QEMU ESP/NCR53C9x emulation
3
 *
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 * Copyright (c) 2005-2006 Fabrice Bellard
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 * Copyright (c) 2012 Herve Poussineau
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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26
#include "qemu/osdep.h"
27
#include "hw/pci/pci_device.h"
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#include "hw/irq.h"
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#include "hw/nvram/eeprom93xx.h"
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#include "hw/scsi/esp.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qom/object.h"
37

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#define TYPE_AM53C974_DEVICE "am53c974"
39

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typedef struct PCIESPState PCIESPState;
41
DECLARE_INSTANCE_CHECKER(PCIESPState, PCI_ESP,
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                         TYPE_AM53C974_DEVICE)
43

44
#define DMA_CMD   0x0
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#define DMA_STC   0x1
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#define DMA_SPA   0x2
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#define DMA_WBC   0x3
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#define DMA_WAC   0x4
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#define DMA_STAT  0x5
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#define DMA_SMDLA 0x6
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#define DMA_WMAC  0x7
52

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#define DMA_CMD_MASK   0x03
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#define DMA_CMD_DIAG   0x04
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#define DMA_CMD_MDL    0x10
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#define DMA_CMD_INTE_P 0x20
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#define DMA_CMD_INTE_D 0x40
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#define DMA_CMD_DIR    0x80
59

60
#define DMA_STAT_PWDN    0x01
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#define DMA_STAT_ERROR   0x02
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#define DMA_STAT_ABORT   0x04
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#define DMA_STAT_DONE    0x08
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#define DMA_STAT_SCSIINT 0x10
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#define DMA_STAT_BCMBLT  0x20
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67
#define SBAC_STATUS (1 << 24)
68

69
struct PCIESPState {
70
    /*< private >*/
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    PCIDevice parent_obj;
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    /*< public >*/
73

74
    MemoryRegion io;
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    uint32_t dma_regs[8];
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    uint32_t sbac;
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    ESPState esp;
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};
79

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static void esp_pci_update_irq(PCIESPState *pci)
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{
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    int scsi_level = !!(pci->dma_regs[DMA_STAT] & DMA_STAT_SCSIINT);
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    int dma_level = (pci->dma_regs[DMA_CMD] & DMA_CMD_INTE_D) ?
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                    !!(pci->dma_regs[DMA_STAT] & DMA_STAT_DONE) : 0;
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    int level = scsi_level || dma_level;
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87
    pci_set_irq(PCI_DEVICE(pci), level);
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}
89

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static void esp_irq_handler(void *opaque, int irq_num, int level)
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{
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    PCIESPState *pci = PCI_ESP(opaque);
93

94
    if (level) {
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        pci->dma_regs[DMA_STAT] |= DMA_STAT_SCSIINT;
96

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        /*
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         * If raising the ESP IRQ to indicate end of DMA transfer, set
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         * DMA_STAT_DONE at the same time. In theory this should be done in
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         * esp_pci_dma_memory_rw(), however there is a delay between setting
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         * DMA_STAT_DONE and the ESP IRQ arriving which is visible to the
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         * guest that can cause confusion e.g. Linux
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         */
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        if ((pci->dma_regs[DMA_CMD] & DMA_CMD_MASK) == 0x3 &&
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            pci->dma_regs[DMA_WBC] == 0) {
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                pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
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        }
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    } else {
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        pci->dma_regs[DMA_STAT] &= ~DMA_STAT_SCSIINT;
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    }
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112
    esp_pci_update_irq(pci);
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}
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115
static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
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{
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    ESPState *s = &pci->esp;
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119
    trace_esp_pci_dma_idle(val);
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    esp_dma_enable(s, 0, 0);
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}
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static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
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{
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    trace_esp_pci_dma_blast(val);
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    qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
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    pci->dma_regs[DMA_STAT] |= DMA_STAT_BCMBLT;
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}
129

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static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
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{
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    ESPState *s = &pci->esp;
133

134
    trace_esp_pci_dma_abort(val);
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    if (s->current_req) {
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        scsi_req_cancel(s->current_req);
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    }
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}
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static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
141
{
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    ESPState *s = &pci->esp;
143

144
    trace_esp_pci_dma_start(val);
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    pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
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    pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
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    pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
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    pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
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                               | DMA_STAT_DONE | DMA_STAT_ABORT
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                               | DMA_STAT_ERROR | DMA_STAT_PWDN);
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    esp_dma_enable(s, 0, 1);
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}
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static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
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{
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    trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
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    switch (saddr) {
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    case DMA_CMD:
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        pci->dma_regs[saddr] = val;
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        switch (val & DMA_CMD_MASK) {
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        case 0x0: /* IDLE */
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            esp_pci_handle_idle(pci, val);
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            break;
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        case 0x1: /* BLAST */
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            esp_pci_handle_blast(pci, val);
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            break;
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        case 0x2: /* ABORT */
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            esp_pci_handle_abort(pci, val);
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            break;
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        case 0x3: /* START */
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            esp_pci_handle_start(pci, val);
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            break;
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        default: /* can't happen */
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            abort();
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        }
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        break;
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    case DMA_STC:
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    case DMA_SPA:
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    case DMA_SMDLA:
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        pci->dma_regs[saddr] = val;
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        break;
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    case DMA_STAT:
186
        if (pci->sbac & SBAC_STATUS) {
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            /* clear some bits on write */
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            uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
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            pci->dma_regs[DMA_STAT] &= ~(val & mask);
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            esp_pci_update_irq(pci);
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        }
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        break;
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    default:
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        trace_esp_pci_error_invalid_write_dma(val, saddr);
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        return;
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    }
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}
198

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static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
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{
201
    uint32_t val;
202

203
    val = pci->dma_regs[saddr];
204
    if (saddr == DMA_STAT) {
205
        if (!(pci->sbac & SBAC_STATUS)) {
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            pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
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                                         DMA_STAT_DONE);
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            esp_pci_update_irq(pci);
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        }
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    }
211

212
    trace_esp_pci_dma_read(saddr, val);
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    return val;
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}
215

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static void esp_pci_io_write(void *opaque, hwaddr addr,
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                             uint64_t val, unsigned int size)
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{
219
    PCIESPState *pci = opaque;
220
    ESPState *s = &pci->esp;
221

222
    if (size < 4 || addr & 3) {
223
        /* need to upgrade request: we only support 4-bytes accesses */
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        uint32_t current = 0, mask;
225
        int shift;
226

227
        if (addr < 0x40) {
228
            current = s->wregs[addr >> 2];
229
        } else if (addr < 0x60) {
230
            current = pci->dma_regs[(addr - 0x40) >> 2];
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        } else if (addr < 0x74) {
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            current = pci->sbac;
233
        }
234

235
        shift = (4 - size) * 8;
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        mask = (~(uint32_t)0 << shift) >> shift;
237

238
        shift = ((4 - (addr & 3)) & 3) * 8;
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        val <<= shift;
240
        val |= current & ~(mask << shift);
241
        addr &= ~3;
242
        size = 4;
243
    }
244
    g_assert(size >= 4);
245

246
    if (addr < 0x40) {
247
        /* SCSI core reg */
248
        esp_reg_write(s, addr >> 2, val);
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    } else if (addr < 0x60) {
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        /* PCI DMA CCB */
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        esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
252
    } else if (addr == 0x70) {
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        /* DMA SCSI Bus and control */
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        trace_esp_pci_sbac_write(pci->sbac, val);
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        pci->sbac = val;
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    } else {
257
        trace_esp_pci_error_invalid_write((int)addr);
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    }
259
}
260

261
static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
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                                unsigned int size)
263
{
264
    PCIESPState *pci = opaque;
265
    ESPState *s = &pci->esp;
266
    uint32_t ret;
267

268
    if (addr < 0x40) {
269
        /* SCSI core reg */
270
        ret = esp_reg_read(s, addr >> 2);
271
    } else if (addr < 0x60) {
272
        /* PCI DMA CCB */
273
        ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
274
    } else if (addr == 0x70) {
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        /* DMA SCSI Bus and control */
276
        trace_esp_pci_sbac_read(pci->sbac);
277
        ret = pci->sbac;
278
    } else {
279
        /* Invalid region */
280
        trace_esp_pci_error_invalid_read((int)addr);
281
        ret = 0;
282
    }
283

284
    /* give only requested data */
285
    ret >>= (addr & 3) * 8;
286
    ret &= ~(~(uint64_t)0 << (8 * size));
287

288
    return ret;
289
}
290

291
static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
292
                                  DMADirection dir)
293
{
294
    dma_addr_t addr;
295
    DMADirection expected_dir;
296

297
    if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
298
        expected_dir = DMA_DIRECTION_FROM_DEVICE;
299
    } else {
300
        expected_dir = DMA_DIRECTION_TO_DEVICE;
301
    }
302

303
    if (dir != expected_dir) {
304
        trace_esp_pci_error_invalid_dma_direction();
305
        return;
306
    }
307

308
    if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
309
        qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
310
    }
311

312
    addr = pci->dma_regs[DMA_WAC];
313
    if (pci->dma_regs[DMA_WBC] < len) {
314
        len = pci->dma_regs[DMA_WBC];
315
    }
316

317
    pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir, MEMTXATTRS_UNSPECIFIED);
318

319
    /* update status registers */
320
    pci->dma_regs[DMA_WBC] -= len;
321
    pci->dma_regs[DMA_WAC] += len;
322
}
323

324
static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
325
{
326
    PCIESPState *pci = opaque;
327
    esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
328
}
329

330
static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
331
{
332
    PCIESPState *pci = opaque;
333
    esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
334
}
335

336
static const MemoryRegionOps esp_pci_io_ops = {
337
    .read = esp_pci_io_read,
338
    .write = esp_pci_io_write,
339
    .endianness = DEVICE_LITTLE_ENDIAN,
340
    .impl = {
341
        .min_access_size = 1,
342
        .max_access_size = 4,
343
    },
344
};
345

346
static void esp_pci_hard_reset(DeviceState *dev)
347
{
348
    PCIESPState *pci = PCI_ESP(dev);
349
    ESPState *s = &pci->esp;
350

351
    esp_hard_reset(s);
352
    pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
353
                              | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
354
    pci->dma_regs[DMA_WBC] &= ~0xffff;
355
    pci->dma_regs[DMA_WAC] = 0xffffffff;
356
    pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
357
                               | DMA_STAT_DONE | DMA_STAT_ABORT
358
                               | DMA_STAT_ERROR);
359
    pci->dma_regs[DMA_WMAC] = 0xfffffffd;
360
}
361

362
static const VMStateDescription vmstate_esp_pci_scsi = {
363
    .name = "pciespscsi",
364
    .version_id = 2,
365
    .minimum_version_id = 1,
366
    .pre_save = esp_pre_save,
367
    .fields = (const VMStateField[]) {
368
        VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
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        VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
370
        VMSTATE_UINT8_V(esp.mig_version_id, PCIESPState, 2),
371
        VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
372
        VMSTATE_END_OF_LIST()
373
    }
374
};
375

376
static const struct SCSIBusInfo esp_pci_scsi_info = {
377
    .tcq = false,
378
    .max_target = ESP_MAX_DEVS,
379
    .max_lun = 7,
380

381
    .transfer_data = esp_transfer_data,
382
    .complete = esp_command_complete,
383
    .cancel = esp_request_cancelled,
384
};
385

386
static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
387
{
388
    PCIESPState *pci = PCI_ESP(dev);
389
    DeviceState *d = DEVICE(dev);
390
    ESPState *s = &pci->esp;
391
    uint8_t *pci_conf;
392

393
    if (!qdev_realize(DEVICE(s), NULL, errp)) {
394
        return;
395
    }
396

397
    pci_conf = dev->config;
398

399
    /* Interrupt pin A */
400
    pci_conf[PCI_INTERRUPT_PIN] = 0x01;
401

402
    s->dma_memory_read = esp_pci_dma_memory_read;
403
    s->dma_memory_write = esp_pci_dma_memory_write;
404
    s->dma_opaque = pci;
405
    s->chip_id = TCHI_AM53C974;
406
    memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
407
                          "esp-io", 0x80);
408

409
    pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
410
    s->irq = qemu_allocate_irq(esp_irq_handler, pci, 0);
411

412
    scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info);
413
}
414

415
static void esp_pci_scsi_exit(PCIDevice *d)
416
{
417
    PCIESPState *pci = PCI_ESP(d);
418
    ESPState *s = &pci->esp;
419

420
    qemu_free_irq(s->irq);
421
}
422

423
static void esp_pci_init(Object *obj)
424
{
425
    PCIESPState *pci = PCI_ESP(obj);
426

427
    object_initialize_child(obj, "esp", &pci->esp, TYPE_ESP);
428
}
429

430
static void esp_pci_class_init(ObjectClass *klass, void *data)
431
{
432
    DeviceClass *dc = DEVICE_CLASS(klass);
433
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
434

435
    k->realize = esp_pci_scsi_realize;
436
    k->exit = esp_pci_scsi_exit;
437
    k->vendor_id = PCI_VENDOR_ID_AMD;
438
    k->device_id = PCI_DEVICE_ID_AMD_SCSI;
439
    k->revision = 0x10;
440
    k->class_id = PCI_CLASS_STORAGE_SCSI;
441
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
442
    dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
443
    dc->reset = esp_pci_hard_reset;
444
    dc->vmsd = &vmstate_esp_pci_scsi;
445
}
446

447
static const TypeInfo esp_pci_info = {
448
    .name = TYPE_AM53C974_DEVICE,
449
    .parent = TYPE_PCI_DEVICE,
450
    .instance_init = esp_pci_init,
451
    .instance_size = sizeof(PCIESPState),
452
    .class_init = esp_pci_class_init,
453
    .interfaces = (InterfaceInfo[]) {
454
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
455
        { },
456
    },
457
};
458

459
struct DC390State {
460
    PCIESPState pci;
461
    eeprom_t *eeprom;
462
};
463
typedef struct DC390State DC390State;
464

465
#define TYPE_DC390_DEVICE "dc390"
466
DECLARE_INSTANCE_CHECKER(DC390State, DC390,
467
                         TYPE_DC390_DEVICE)
468

469
#define EE_ADAPT_SCSI_ID 64
470
#define EE_MODE2         65
471
#define EE_DELAY         66
472
#define EE_TAG_CMD_NUM   67
473
#define EE_ADAPT_OPTIONS 68
474
#define EE_BOOT_SCSI_ID  69
475
#define EE_BOOT_SCSI_LUN 70
476
#define EE_CHKSUM1       126
477
#define EE_CHKSUM2       127
478

479
#define EE_ADAPT_OPTION_F6_F8_AT_BOOT   0x01
480
#define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
481
#define EE_ADAPT_OPTION_INT13           0x04
482
#define EE_ADAPT_OPTION_SCAM_SUPPORT    0x08
483

484

485
static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
486
{
487
    DC390State *pci = DC390(dev);
488
    uint32_t val;
489

490
    val = pci_default_read_config(dev, addr, l);
491

492
    if (addr == 0x00 && l == 1) {
493
        /* First byte of address space is AND-ed with EEPROM DO line */
494
        if (!eeprom93xx_read(pci->eeprom)) {
495
            val &= ~0xff;
496
        }
497
    }
498

499
    return val;
500
}
501

502
static void dc390_write_config(PCIDevice *dev,
503
                               uint32_t addr, uint32_t val, int l)
504
{
505
    DC390State *pci = DC390(dev);
506
    if (addr == 0x80) {
507
        /* EEPROM write */
508
        int eesk = val & 0x80 ? 1 : 0;
509
        int eedi = val & 0x40 ? 1 : 0;
510
        eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
511
    } else if (addr == 0xc0) {
512
        /* EEPROM CS low */
513
        eeprom93xx_write(pci->eeprom, 0, 0, 0);
514
    } else {
515
        pci_default_write_config(dev, addr, val, l);
516
    }
517
}
518

519
static void dc390_scsi_realize(PCIDevice *dev, Error **errp)
520
{
521
    DC390State *pci = DC390(dev);
522
    Error *err = NULL;
523
    uint8_t *contents;
524
    uint16_t chksum = 0;
525
    int i;
526

527
    /* init base class */
528
    esp_pci_scsi_realize(dev, &err);
529
    if (err) {
530
        error_propagate(errp, err);
531
        return;
532
    }
533

534
    /* EEPROM */
535
    pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
536

537
    /* set default eeprom values */
538
    contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
539

540
    for (i = 0; i < 16; i++) {
541
        contents[i * 2] = 0x57;
542
        contents[i * 2 + 1] = 0x00;
543
    }
544
    contents[EE_ADAPT_SCSI_ID] = 7;
545
    contents[EE_MODE2] = 0x0f;
546
    contents[EE_TAG_CMD_NUM] = 0x04;
547
    contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
548
                               | EE_ADAPT_OPTION_BOOT_FROM_CDROM
549
                               | EE_ADAPT_OPTION_INT13;
550

551
    /* update eeprom checksum */
552
    for (i = 0; i < EE_CHKSUM1; i += 2) {
553
        chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
554
    }
555
    chksum = 0x1234 - chksum;
556
    contents[EE_CHKSUM1] = chksum & 0xff;
557
    contents[EE_CHKSUM2] = chksum >> 8;
558
}
559

560
static void dc390_class_init(ObjectClass *klass, void *data)
561
{
562
    DeviceClass *dc = DEVICE_CLASS(klass);
563
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
564

565
    k->realize = dc390_scsi_realize;
566
    k->config_read = dc390_read_config;
567
    k->config_write = dc390_write_config;
568
    set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
569
    dc->desc = "Tekram DC-390 SCSI adapter";
570
}
571

572
static const TypeInfo dc390_info = {
573
    .name = TYPE_DC390_DEVICE,
574
    .parent = TYPE_AM53C974_DEVICE,
575
    .instance_size = sizeof(DC390State),
576
    .class_init = dc390_class_init,
577
};
578

579
static void esp_pci_register_types(void)
580
{
581
    type_register_static(&esp_pci_info);
582
    type_register_static(&dc390_info);
583
}
584

585
type_init(esp_pci_register_types)
586