qemu

1
/*
2
 * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
3
 *
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 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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 * Copyright (c) 2017 SiFive, Inc.
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 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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 *
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 * Provides a board compatible with the SiFive Freedom U SDK:
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 *
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 * 0) UART
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 * 1) CLINT (Core Level Interruptor)
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 * 2) PLIC (Platform Level Interrupt Controller)
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 * 3) PRCI (Power, Reset, Clock, Interrupt)
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 * 4) GPIO (General Purpose Input/Output Controller)
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 * 5) OTP (One-Time Programmable) memory with stored serial number
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 * 6) GEM (Gigabit Ethernet Controller) and management block
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 * 7) DMA (Direct Memory Access Controller)
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 * 8) SPI0 connected to an SPI flash
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 * 9) SPI2 connected to an SD card
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 * 10) PWM0 and PWM1
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 *
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 * This board currently generates devicetree dynamically that indicates at least
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 * two harts and up to five harts.
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2 or later, as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
32
 * more details.
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 *
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 * You should have received a copy of the GNU General Public License along with
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 * this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
37

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#include "qemu/osdep.h"
39
#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "hw/boards.h"
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#include "hw/irq.h"
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#include "hw/loader.h"
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#include "hw/sysbus.h"
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#include "hw/char/serial.h"
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#include "hw/cpu/cluster.h"
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#include "hw/misc/unimp.h"
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#include "hw/sd/sd.h"
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#include "hw/ssi/ssi.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_u.h"
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#include "hw/riscv/boot.h"
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#include "hw/char/sifive_uart.h"
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#include "hw/intc/riscv_aclint.h"
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#include "hw/intc/sifive_plic.h"
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#include "chardev/char.h"
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#include "net/eth.h"
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#include "sysemu/device_tree.h"
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#include "sysemu/runstate.h"
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#include "sysemu/sysemu.h"
63

64
#include <libfdt.h>
65

66
/* CLINT timebase frequency */
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#define CLINT_TIMEBASE_FREQ 1000000
68

69
static const MemMapEntry sifive_u_memmap[] = {
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    [SIFIVE_U_DEV_DEBUG] =    {        0x0,      0x100 },
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    [SIFIVE_U_DEV_MROM] =     {     0x1000,     0xf000 },
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    [SIFIVE_U_DEV_CLINT] =    {  0x2000000,    0x10000 },
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    [SIFIVE_U_DEV_L2CC] =     {  0x2010000,     0x1000 },
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    [SIFIVE_U_DEV_PDMA] =     {  0x3000000,   0x100000 },
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    [SIFIVE_U_DEV_L2LIM] =    {  0x8000000,  0x2000000 },
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    [SIFIVE_U_DEV_PLIC] =     {  0xc000000,  0x4000000 },
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    [SIFIVE_U_DEV_PRCI] =     { 0x10000000,     0x1000 },
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    [SIFIVE_U_DEV_UART0] =    { 0x10010000,     0x1000 },
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    [SIFIVE_U_DEV_UART1] =    { 0x10011000,     0x1000 },
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    [SIFIVE_U_DEV_PWM0] =     { 0x10020000,     0x1000 },
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    [SIFIVE_U_DEV_PWM1] =     { 0x10021000,     0x1000 },
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    [SIFIVE_U_DEV_QSPI0] =    { 0x10040000,     0x1000 },
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    [SIFIVE_U_DEV_QSPI2] =    { 0x10050000,     0x1000 },
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    [SIFIVE_U_DEV_GPIO] =     { 0x10060000,     0x1000 },
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    [SIFIVE_U_DEV_OTP] =      { 0x10070000,     0x1000 },
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    [SIFIVE_U_DEV_GEM] =      { 0x10090000,     0x2000 },
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    [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000,     0x1000 },
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    [SIFIVE_U_DEV_DMC] =      { 0x100b0000,    0x10000 },
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    [SIFIVE_U_DEV_FLASH0] =   { 0x20000000, 0x10000000 },
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    [SIFIVE_U_DEV_DRAM] =     { 0x80000000,        0x0 },
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};
92

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#define OTP_SERIAL          1
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#define GEM_REVISION        0x10070109
95

96
static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
97
                       bool is_32_bit)
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{
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    MachineState *ms = MACHINE(s);
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    uint64_t mem_size = ms->ram_size;
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    void *fdt;
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    int cpu;
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    uint32_t *cells;
104
    char *nodename;
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    uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1;
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    uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
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    static const char * const ethclk_names[2] = { "pclk", "hclk" };
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    static const char * const clint_compat[2] = {
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        "sifive,clint0", "riscv,clint0"
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    };
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    static const char * const plic_compat[2] = {
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        "sifive,plic-1.0.0", "riscv,plic0"
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    };
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    fdt = ms->fdt = create_device_tree(&s->fdt_size);
116
    if (!fdt) {
117
        error_report("create_device_tree() failed");
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        exit(1);
119
    }
120

121
    qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00");
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    qemu_fdt_setprop_string(fdt, "/", "compatible",
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                            "sifive,hifive-unleashed-a00");
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    qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
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    qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
126

127
    qemu_fdt_add_subnode(fdt, "/soc");
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    qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
129
    qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus");
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    qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
131
    qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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133
    hfclk_phandle = phandle++;
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    nodename = g_strdup_printf("/hfclk");
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    qemu_fdt_add_subnode(fdt, nodename);
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    qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle);
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    qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk");
138
    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
139
        SIFIVE_U_HFCLK_FREQ);
140
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
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    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
142
    g_free(nodename);
143

144
    rtcclk_phandle = phandle++;
145
    nodename = g_strdup_printf("/rtcclk");
146
    qemu_fdt_add_subnode(fdt, nodename);
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    qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle);
148
    qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk");
149
    qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
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        SIFIVE_U_RTCCLK_FREQ);
151
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
152
    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
153
    g_free(nodename);
154

155
    nodename = g_strdup_printf("/memory@%lx",
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        (long)memmap[SIFIVE_U_DEV_DRAM].base);
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    qemu_fdt_add_subnode(fdt, nodename);
158
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
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        memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
160
        mem_size >> 32, mem_size);
161
    qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
162
    g_free(nodename);
163

164
    qemu_fdt_add_subnode(fdt, "/cpus");
165
    qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
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        CLINT_TIMEBASE_FREQ);
167
    qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
168
    qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
169

170
    for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) {
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        int cpu_phandle = phandle++;
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        nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
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        char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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        qemu_fdt_add_subnode(fdt, nodename);
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        /* cpu 0 is the management hart that does not have mmu */
176
        if (cpu != 0) {
177
            if (is_32_bit) {
178
                qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv32");
179
            } else {
180
                qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
181
            }
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            riscv_isa_write_fdt(&s->soc.u_cpus.harts[cpu - 1], fdt, nodename);
183
        } else {
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            riscv_isa_write_fdt(&s->soc.e_cpus.harts[0], fdt, nodename);
185
        }
186
        qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
187
        qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
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        qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
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        qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
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        qemu_fdt_add_subnode(fdt, intc);
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        qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
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        qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
193
        qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
194
        qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
195
        g_free(intc);
196
        g_free(nodename);
197
    }
198

199
    cells =  g_new0(uint32_t, ms->smp.cpus * 4);
200
    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
201
        nodename =
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            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
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        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
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        cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
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        cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
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        cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
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        cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
208
        g_free(nodename);
209
    }
210
    nodename = g_strdup_printf("/soc/clint@%lx",
211
        (long)memmap[SIFIVE_U_DEV_CLINT].base);
212
    qemu_fdt_add_subnode(fdt, nodename);
213
    qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
214
        (char **)&clint_compat, ARRAY_SIZE(clint_compat));
215
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
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        0x0, memmap[SIFIVE_U_DEV_CLINT].base,
217
        0x0, memmap[SIFIVE_U_DEV_CLINT].size);
218
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
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        cells, ms->smp.cpus * sizeof(uint32_t) * 4);
220
    g_free(cells);
221
    g_free(nodename);
222

223
    nodename = g_strdup_printf("/soc/otp@%lx",
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        (long)memmap[SIFIVE_U_DEV_OTP].base);
225
    qemu_fdt_add_subnode(fdt, nodename);
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    qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
227
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
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        0x0, memmap[SIFIVE_U_DEV_OTP].base,
229
        0x0, memmap[SIFIVE_U_DEV_OTP].size);
230
    qemu_fdt_setprop_string(fdt, nodename, "compatible",
231
        "sifive,fu540-c000-otp");
232
    g_free(nodename);
233

234
    prci_phandle = phandle++;
235
    nodename = g_strdup_printf("/soc/clock-controller@%lx",
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        (long)memmap[SIFIVE_U_DEV_PRCI].base);
237
    qemu_fdt_add_subnode(fdt, nodename);
238
    qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
239
    qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
240
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
241
        hfclk_phandle, rtcclk_phandle);
242
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
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        0x0, memmap[SIFIVE_U_DEV_PRCI].base,
244
        0x0, memmap[SIFIVE_U_DEV_PRCI].size);
245
    qemu_fdt_setprop_string(fdt, nodename, "compatible",
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        "sifive,fu540-c000-prci");
247
    g_free(nodename);
248

249
    plic_phandle = phandle++;
250
    cells =  g_new0(uint32_t, ms->smp.cpus * 4 - 2);
251
    for (cpu = 0; cpu < ms->smp.cpus; cpu++) {
252
        nodename =
253
            g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
254
        uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
255
        /* cpu 0 is the management hart that does not have S-mode */
256
        if (cpu == 0) {
257
            cells[0] = cpu_to_be32(intc_phandle);
258
            cells[1] = cpu_to_be32(IRQ_M_EXT);
259
        } else {
260
            cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle);
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            cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT);
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            cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
263
            cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT);
264
        }
265
        g_free(nodename);
266
    }
267
    nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
268
        (long)memmap[SIFIVE_U_DEV_PLIC].base);
269
    qemu_fdt_add_subnode(fdt, nodename);
270
    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
271
    qemu_fdt_setprop_string_array(fdt, nodename, "compatible",
272
        (char **)&plic_compat, ARRAY_SIZE(plic_compat));
273
    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
274
    qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
275
        cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
276
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
277
        0x0, memmap[SIFIVE_U_DEV_PLIC].base,
278
        0x0, memmap[SIFIVE_U_DEV_PLIC].size);
279
    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev",
280
                          SIFIVE_U_PLIC_NUM_SOURCES - 1);
281
    qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
282
    plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
283
    g_free(cells);
284
    g_free(nodename);
285

286
    gpio_phandle = phandle++;
287
    nodename = g_strdup_printf("/soc/gpio@%lx",
288
        (long)memmap[SIFIVE_U_DEV_GPIO].base);
289
    qemu_fdt_add_subnode(fdt, nodename);
290
    qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
291
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
292
        prci_phandle, PRCI_CLK_TLCLK);
293
    qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 2);
294
    qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
295
    qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
296
    qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
297
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
298
        0x0, memmap[SIFIVE_U_DEV_GPIO].base,
299
        0x0, memmap[SIFIVE_U_DEV_GPIO].size);
300
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
301
        SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
302
        SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
303
        SIFIVE_U_GPIO_IRQ7, SIFIVE_U_GPIO_IRQ8, SIFIVE_U_GPIO_IRQ9,
304
        SIFIVE_U_GPIO_IRQ10, SIFIVE_U_GPIO_IRQ11, SIFIVE_U_GPIO_IRQ12,
305
        SIFIVE_U_GPIO_IRQ13, SIFIVE_U_GPIO_IRQ14, SIFIVE_U_GPIO_IRQ15);
306
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
307
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,gpio0");
308
    g_free(nodename);
309

310
    nodename = g_strdup_printf("/gpio-restart");
311
    qemu_fdt_add_subnode(fdt, nodename);
312
    qemu_fdt_setprop_cells(fdt, nodename, "gpios", gpio_phandle, 10, 1);
313
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
314
    g_free(nodename);
315

316
    nodename = g_strdup_printf("/soc/dma@%lx",
317
        (long)memmap[SIFIVE_U_DEV_PDMA].base);
318
    qemu_fdt_add_subnode(fdt, nodename);
319
    qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
320
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
321
        SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
322
        SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
323
        SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
324
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
325
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
326
        0x0, memmap[SIFIVE_U_DEV_PDMA].base,
327
        0x0, memmap[SIFIVE_U_DEV_PDMA].size);
328
    qemu_fdt_setprop_string(fdt, nodename, "compatible",
329
                            "sifive,fu540-c000-pdma");
330
    g_free(nodename);
331

332
    nodename = g_strdup_printf("/soc/cache-controller@%lx",
333
        (long)memmap[SIFIVE_U_DEV_L2CC].base);
334
    qemu_fdt_add_subnode(fdt, nodename);
335
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
336
        0x0, memmap[SIFIVE_U_DEV_L2CC].base,
337
        0x0, memmap[SIFIVE_U_DEV_L2CC].size);
338
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
339
        SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2);
340
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
341
    qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0);
342
    qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152);
343
    qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024);
344
    qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2);
345
    qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64);
346
    qemu_fdt_setprop_string(fdt, nodename, "compatible",
347
                            "sifive,fu540-c000-ccache");
348
    g_free(nodename);
349

350
    nodename = g_strdup_printf("/soc/spi@%lx",
351
        (long)memmap[SIFIVE_U_DEV_QSPI2].base);
352
    qemu_fdt_add_subnode(fdt, nodename);
353
    qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
354
    qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
355
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
356
        prci_phandle, PRCI_CLK_TLCLK);
357
    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI2_IRQ);
358
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
359
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
360
        0x0, memmap[SIFIVE_U_DEV_QSPI2].base,
361
        0x0, memmap[SIFIVE_U_DEV_QSPI2].size);
362
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
363
    g_free(nodename);
364

365
    nodename = g_strdup_printf("/soc/spi@%lx/mmc@0",
366
        (long)memmap[SIFIVE_U_DEV_QSPI2].base);
367
    qemu_fdt_add_subnode(fdt, nodename);
368
    qemu_fdt_setprop(fdt, nodename, "disable-wp", NULL, 0);
369
    qemu_fdt_setprop_cells(fdt, nodename, "voltage-ranges", 3300, 3300);
370
    qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 20000000);
371
    qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
372
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "mmc-spi-slot");
373
    g_free(nodename);
374

375
    nodename = g_strdup_printf("/soc/spi@%lx",
376
        (long)memmap[SIFIVE_U_DEV_QSPI0].base);
377
    qemu_fdt_add_subnode(fdt, nodename);
378
    qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
379
    qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
380
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
381
        prci_phandle, PRCI_CLK_TLCLK);
382
    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_QSPI0_IRQ);
383
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
384
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
385
        0x0, memmap[SIFIVE_U_DEV_QSPI0].base,
386
        0x0, memmap[SIFIVE_U_DEV_QSPI0].size);
387
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,spi0");
388
    g_free(nodename);
389

390
    nodename = g_strdup_printf("/soc/spi@%lx/flash@0",
391
        (long)memmap[SIFIVE_U_DEV_QSPI0].base);
392
    qemu_fdt_add_subnode(fdt, nodename);
393
    qemu_fdt_setprop_cell(fdt, nodename, "spi-rx-bus-width", 4);
394
    qemu_fdt_setprop_cell(fdt, nodename, "spi-tx-bus-width", 4);
395
    qemu_fdt_setprop(fdt, nodename, "m25p,fast-read", NULL, 0);
396
    qemu_fdt_setprop_cell(fdt, nodename, "spi-max-frequency", 50000000);
397
    qemu_fdt_setprop_cell(fdt, nodename, "reg", 0);
398
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "jedec,spi-nor");
399
    g_free(nodename);
400

401
    phy_phandle = phandle++;
402
    nodename = g_strdup_printf("/soc/ethernet@%lx",
403
        (long)memmap[SIFIVE_U_DEV_GEM].base);
404
    qemu_fdt_add_subnode(fdt, nodename);
405
    qemu_fdt_setprop_string(fdt, nodename, "compatible",
406
        "sifive,fu540-c000-gem");
407
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
408
        0x0, memmap[SIFIVE_U_DEV_GEM].base,
409
        0x0, memmap[SIFIVE_U_DEV_GEM].size,
410
        0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
411
        0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
412
    qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
413
    qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
414
    qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
415
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
416
    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
417
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
418
        prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
419
    qemu_fdt_setprop_string_array(fdt, nodename, "clock-names",
420
        (char **)&ethclk_names, ARRAY_SIZE(ethclk_names));
421
    qemu_fdt_setprop(fdt, nodename, "local-mac-address",
422
        s->soc.gem.conf.macaddr.a, ETH_ALEN);
423
    qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
424
    qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0);
425

426
    qemu_fdt_add_subnode(fdt, "/aliases");
427
    qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename);
428

429
    g_free(nodename);
430

431
    nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
432
        (long)memmap[SIFIVE_U_DEV_GEM].base);
433
    qemu_fdt_add_subnode(fdt, nodename);
434
    qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
435
    qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
436
    g_free(nodename);
437

438
    nodename = g_strdup_printf("/soc/pwm@%lx",
439
        (long)memmap[SIFIVE_U_DEV_PWM0].base);
440
    qemu_fdt_add_subnode(fdt, nodename);
441
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
442
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
443
        0x0, memmap[SIFIVE_U_DEV_PWM0].base,
444
        0x0, memmap[SIFIVE_U_DEV_PWM0].size);
445
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
446
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
447
                           SIFIVE_U_PWM0_IRQ0, SIFIVE_U_PWM0_IRQ1,
448
                           SIFIVE_U_PWM0_IRQ2, SIFIVE_U_PWM0_IRQ3);
449
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
450
                           prci_phandle, PRCI_CLK_TLCLK);
451
    qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
452
    g_free(nodename);
453

454
    nodename = g_strdup_printf("/soc/pwm@%lx",
455
        (long)memmap[SIFIVE_U_DEV_PWM1].base);
456
    qemu_fdt_add_subnode(fdt, nodename);
457
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,pwm0");
458
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
459
        0x0, memmap[SIFIVE_U_DEV_PWM1].base,
460
        0x0, memmap[SIFIVE_U_DEV_PWM1].size);
461
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
462
    qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
463
                           SIFIVE_U_PWM1_IRQ0, SIFIVE_U_PWM1_IRQ1,
464
                           SIFIVE_U_PWM1_IRQ2, SIFIVE_U_PWM1_IRQ3);
465
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
466
                           prci_phandle, PRCI_CLK_TLCLK);
467
    qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0);
468
    g_free(nodename);
469

470
    nodename = g_strdup_printf("/soc/serial@%lx",
471
        (long)memmap[SIFIVE_U_DEV_UART1].base);
472
    qemu_fdt_add_subnode(fdt, nodename);
473
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
474
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
475
        0x0, memmap[SIFIVE_U_DEV_UART1].base,
476
        0x0, memmap[SIFIVE_U_DEV_UART1].size);
477
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
478
        prci_phandle, PRCI_CLK_TLCLK);
479
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
480
    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART1_IRQ);
481

482
    qemu_fdt_setprop_string(fdt, "/aliases", "serial1", nodename);
483
    g_free(nodename);
484

485
    nodename = g_strdup_printf("/soc/serial@%lx",
486
        (long)memmap[SIFIVE_U_DEV_UART0].base);
487
    qemu_fdt_add_subnode(fdt, nodename);
488
    qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
489
    qemu_fdt_setprop_cells(fdt, nodename, "reg",
490
        0x0, memmap[SIFIVE_U_DEV_UART0].base,
491
        0x0, memmap[SIFIVE_U_DEV_UART0].size);
492
    qemu_fdt_setprop_cells(fdt, nodename, "clocks",
493
        prci_phandle, PRCI_CLK_TLCLK);
494
    qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
495
    qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
496

497
    qemu_fdt_add_subnode(fdt, "/chosen");
498
    qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
499
    qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename);
500

501
    g_free(nodename);
502
}
503

504
static void sifive_u_machine_reset(void *opaque, int n, int level)
505
{
506
    /* gpio pin active low triggers reset */
507
    if (!level) {
508
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
509
    }
510
}
511

512
static void sifive_u_machine_init(MachineState *machine)
513
{
514
    const MemMapEntry *memmap = sifive_u_memmap;
515
    SiFiveUState *s = RISCV_U_MACHINE(machine);
516
    MemoryRegion *system_memory = get_system_memory();
517
    MemoryRegion *flash0 = g_new(MemoryRegion, 1);
518
    target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
519
    target_ulong firmware_end_addr, kernel_start_addr;
520
    const char *firmware_name;
521
    uint32_t start_addr_hi32 = 0x00000000;
522
    int i;
523
    uint32_t fdt_load_addr;
524
    uint64_t kernel_entry;
525
    DriveInfo *dinfo;
526
    BlockBackend *blk;
527
    DeviceState *flash_dev, *sd_dev, *card_dev;
528
    qemu_irq flash_cs, sd_cs;
529

530
    /* Initialize SoC */
531
    object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
532
    object_property_set_uint(OBJECT(&s->soc), "serial", s->serial,
533
                             &error_abort);
534
    object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type,
535
                             &error_abort);
536
    qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
537

538
    /* register RAM */
539
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
540
                                machine->ram);
541

542
    /* register QSPI0 Flash */
543
    memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
544
                           memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
545
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
546
                                flash0);
547

548
    /* register gpio-restart */
549
    qdev_connect_gpio_out(DEVICE(&(s->soc.gpio)), 10,
550
                          qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
551

552
    /* load/create device tree */
553
    if (machine->dtb) {
554
        machine->fdt = load_device_tree(machine->dtb, &s->fdt_size);
555
        if (!machine->fdt) {
556
            error_report("load_device_tree() failed");
557
            exit(1);
558
        }
559
    } else {
560
        create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus));
561
    }
562

563
    if (s->start_in_flash) {
564
        /*
565
         * If start_in_flash property is given, assign s->msel to a value
566
         * that representing booting from QSPI0 memory-mapped flash.
567
         *
568
         * This also means that when both start_in_flash and msel properties
569
         * are given, start_in_flash takes the precedence over msel.
570
         *
571
         * Note this is to keep backward compatibility not to break existing
572
         * users that use start_in_flash property.
573
         */
574
        s->msel = MSEL_MEMMAP_QSPI0_FLASH;
575
    }
576

577
    switch (s->msel) {
578
    case MSEL_MEMMAP_QSPI0_FLASH:
579
        start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
580
        break;
581
    case MSEL_L2LIM_QSPI0_FLASH:
582
    case MSEL_L2LIM_QSPI2_SD:
583
        start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
584
        break;
585
    default:
586
        start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
587
        break;
588
    }
589

590
    firmware_name = riscv_default_firmware_name(&s->soc.u_cpus);
591
    firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
592
                                                     start_addr, NULL);
593

594
    if (machine->kernel_filename) {
595
        kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
596
                                                         firmware_end_addr);
597

598
        kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
599
                                         kernel_start_addr, true, NULL);
600
    } else {
601
       /*
602
        * If dynamic firmware is used, it doesn't know where is the next mode
603
        * if kernel argument is not set.
604
        */
605
        kernel_entry = 0;
606
    }
607

608
    fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base,
609
                                           memmap[SIFIVE_U_DEV_DRAM].size,
610
                                           machine);
611
    riscv_load_fdt(fdt_load_addr, machine->fdt);
612

613
    if (!riscv_is_32bit(&s->soc.u_cpus)) {
614
        start_addr_hi32 = (uint64_t)start_addr >> 32;
615
    }
616

617
    /* reset vector */
618
    uint32_t reset_vec[12] = {
619
        s->msel,                       /* MSEL pin state */
620
        0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(fw_dyn) */
621
        0x02c28613,                    /*     addi   a2, t0, %pcrel_lo(1b) */
622
        0xf1402573,                    /*     csrr   a0, mhartid  */
623
        0,
624
        0,
625
        0x00028067,                    /*     jr     t0 */
626
        start_addr,                    /* start: .dword */
627
        start_addr_hi32,
628
        fdt_load_addr,                 /* fdt_laddr: .dword */
629
        0x00000000,
630
        0x00000000,
631
                                       /* fw_dyn: */
632
    };
633
    if (riscv_is_32bit(&s->soc.u_cpus)) {
634
        reset_vec[4] = 0x0202a583;     /*     lw     a1, 32(t0) */
635
        reset_vec[5] = 0x0182a283;     /*     lw     t0, 24(t0) */
636
    } else {
637
        reset_vec[4] = 0x0202b583;     /*     ld     a1, 32(t0) */
638
        reset_vec[5] = 0x0182b283;     /*     ld     t0, 24(t0) */
639
    }
640

641

642
    /* copy in the reset vector in little_endian byte order */
643
    for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
644
        reset_vec[i] = cpu_to_le32(reset_vec[i]);
645
    }
646
    rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
647
                          memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
648

649
    riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
650
                                 memmap[SIFIVE_U_DEV_MROM].size,
651
                                 sizeof(reset_vec), kernel_entry);
652

653
    /* Connect an SPI flash to SPI0 */
654
    flash_dev = qdev_new("is25wp256");
655
    dinfo = drive_get(IF_MTD, 0, 0);
656
    if (dinfo) {
657
        qdev_prop_set_drive_err(flash_dev, "drive",
658
                                blk_by_legacy_dinfo(dinfo),
659
                                &error_fatal);
660
    }
661
    qdev_realize_and_unref(flash_dev, BUS(s->soc.spi0.spi), &error_fatal);
662

663
    flash_cs = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
664
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi0), 1, flash_cs);
665

666
    /* Connect an SD card to SPI2 */
667
    sd_dev = ssi_create_peripheral(s->soc.spi2.spi, "ssi-sd");
668

669
    sd_cs = qdev_get_gpio_in_named(sd_dev, SSI_GPIO_CS, 0);
670
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->soc.spi2), 1, sd_cs);
671

672
    dinfo = drive_get(IF_SD, 0, 0);
673
    blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
674
    card_dev = qdev_new(TYPE_SD_CARD_SPI);
675
    qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal);
676
    qdev_realize_and_unref(card_dev,
677
                           qdev_get_child_bus(sd_dev, "sd-bus"),
678
                           &error_fatal);
679
}
680

681
static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
682
{
683
    SiFiveUState *s = RISCV_U_MACHINE(obj);
684

685
    return s->start_in_flash;
686
}
687

688
static void sifive_u_machine_set_start_in_flash(Object *obj, bool value, Error **errp)
689
{
690
    SiFiveUState *s = RISCV_U_MACHINE(obj);
691

692
    s->start_in_flash = value;
693
}
694

695
static void sifive_u_machine_instance_init(Object *obj)
696
{
697
    SiFiveUState *s = RISCV_U_MACHINE(obj);
698

699
    s->start_in_flash = false;
700
    s->msel = 0;
701
    object_property_add_uint32_ptr(obj, "msel", &s->msel,
702
                                   OBJ_PROP_FLAG_READWRITE);
703
    object_property_set_description(obj, "msel",
704
                                    "Mode Select (MSEL[3:0]) pin state");
705

706
    s->serial = OTP_SERIAL;
707
    object_property_add_uint32_ptr(obj, "serial", &s->serial,
708
                                   OBJ_PROP_FLAG_READWRITE);
709
    object_property_set_description(obj, "serial", "Board serial number");
710
}
711

712
static void sifive_u_machine_class_init(ObjectClass *oc, void *data)
713
{
714
    MachineClass *mc = MACHINE_CLASS(oc);
715

716
    mc->desc = "RISC-V Board compatible with SiFive U SDK";
717
    mc->init = sifive_u_machine_init;
718
    mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
719
    mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
720
    mc->default_cpu_type = SIFIVE_U_CPU;
721
    mc->default_cpus = mc->min_cpus;
722
    mc->default_ram_id = "riscv.sifive.u.ram";
723

724
    object_class_property_add_bool(oc, "start-in-flash",
725
                                   sifive_u_machine_get_start_in_flash,
726
                                   sifive_u_machine_set_start_in_flash);
727
    object_class_property_set_description(oc, "start-in-flash",
728
                                          "Set on to tell QEMU's ROM to jump to "
729
                                          "flash. Otherwise QEMU will jump to DRAM "
730
                                          "or L2LIM depending on the msel value");
731
}
732

733
static const TypeInfo sifive_u_machine_typeinfo = {
734
    .name       = MACHINE_TYPE_NAME("sifive_u"),
735
    .parent     = TYPE_MACHINE,
736
    .class_init = sifive_u_machine_class_init,
737
    .instance_init = sifive_u_machine_instance_init,
738
    .instance_size = sizeof(SiFiveUState),
739
};
740

741
static void sifive_u_machine_init_register_types(void)
742
{
743
    type_register_static(&sifive_u_machine_typeinfo);
744
}
745

746
type_init(sifive_u_machine_init_register_types)
747

748
static void sifive_u_soc_instance_init(Object *obj)
749
{
750
    SiFiveUSoCState *s = RISCV_U_SOC(obj);
751

752
    object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
753
    qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
754

755
    object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
756
                            TYPE_RISCV_HART_ARRAY);
757
    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
758
    qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
759
    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
760
    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
761

762
    object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
763
    qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
764

765
    object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
766
                            TYPE_RISCV_HART_ARRAY);
767

768
    object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
769
    object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
770
    object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
771
    object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
772
    object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
773
    object_initialize_child(obj, "spi0", &s->spi0, TYPE_SIFIVE_SPI);
774
    object_initialize_child(obj, "spi2", &s->spi2, TYPE_SIFIVE_SPI);
775
    object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM);
776
    object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM);
777
}
778

779
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
780
{
781
    MachineState *ms = MACHINE(qdev_get_machine());
782
    SiFiveUSoCState *s = RISCV_U_SOC(dev);
783
    const MemMapEntry *memmap = sifive_u_memmap;
784
    MemoryRegion *system_memory = get_system_memory();
785
    MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
786
    MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
787
    char *plic_hart_config;
788
    int i, j;
789

790
    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
791
    qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
792
    qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
793
    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
794

795
    sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_fatal);
796
    sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_fatal);
797
    /*
798
     * The cluster must be realized after the RISC-V hart array container,
799
     * as the container's CPU object is only created on realize, and the
800
     * CPU must exist and have been parented into the cluster before the
801
     * cluster is realized.
802
     */
803
    qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
804
    qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
805

806
    /* boot rom */
807
    memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
808
                           memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
809
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
810
                                mask_rom);
811

812
    /*
813
     * Add L2-LIM at reset size.
814
     * This should be reduced in size as the L2 Cache Controller WayEnable
815
     * register is incremented. Unfortunately I don't see a nice (or any) way
816
     * to handle reducing or blocking out the L2 LIM while still allowing it
817
     * be re returned to all enabled after a reset. For the time being, just
818
     * leave it enabled all the time. This won't break anything, but will be
819
     * too generous to misbehaving guests.
820
     */
821
    memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
822
                           memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
823
    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
824
                                l2lim_mem);
825

826
    /* create PLIC hart topology configuration string */
827
    plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
828

829
    /* MMIO */
830
    s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
831
        plic_hart_config, ms->smp.cpus, 0,
832
        SIFIVE_U_PLIC_NUM_SOURCES,
833
        SIFIVE_U_PLIC_NUM_PRIORITIES,
834
        SIFIVE_U_PLIC_PRIORITY_BASE,
835
        SIFIVE_U_PLIC_PENDING_BASE,
836
        SIFIVE_U_PLIC_ENABLE_BASE,
837
        SIFIVE_U_PLIC_ENABLE_STRIDE,
838
        SIFIVE_U_PLIC_CONTEXT_BASE,
839
        SIFIVE_U_PLIC_CONTEXT_STRIDE,
840
        memmap[SIFIVE_U_DEV_PLIC].size);
841
    g_free(plic_hart_config);
842
    sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
843
        serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
844
    sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
845
        serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
846
    riscv_aclint_swi_create(memmap[SIFIVE_U_DEV_CLINT].base, 0,
847
        ms->smp.cpus, false);
848
    riscv_aclint_mtimer_create(memmap[SIFIVE_U_DEV_CLINT].base +
849
            RISCV_ACLINT_SWI_SIZE,
850
        RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
851
        RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
852
        CLINT_TIMEBASE_FREQ, false);
853

854
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
855
        return;
856
    }
857
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
858

859
    qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
860
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
861
        return;
862
    }
863
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
864

865
    /* Pass all GPIOs to the SOC layer so they are available to the board */
866
    qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
867

868
    /* Connect GPIO interrupts to the PLIC */
869
    for (i = 0; i < 16; i++) {
870
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
871
                           qdev_get_gpio_in(DEVICE(s->plic),
872
                                            SIFIVE_U_GPIO_IRQ0 + i));
873
    }
874

875
    /* PDMA */
876
    sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
877
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].base);
878

879
    /* Connect PDMA interrupts to the PLIC */
880
    for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
881
        sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
882
                           qdev_get_gpio_in(DEVICE(s->plic),
883
                                            SIFIVE_U_PDMA_IRQ0 + i));
884
    }
885

886
    qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
887
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
888
        return;
889
    }
890
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
891

892
    qemu_configure_nic_device(DEVICE(&s->gem), true, NULL);
893
    object_property_set_int(OBJECT(&s->gem), "revision", GEM_REVISION,
894
                            &error_abort);
895
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
896
        return;
897
    }
898
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
899
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
900
                       qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
901

902
    /* PWM */
903
    for (i = 0; i < 2; i++) {
904
        if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) {
905
            return;
906
        }
907
        sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0,
908
                                memmap[SIFIVE_U_DEV_PWM0].base + (0x1000 * i));
909

910
        /* Connect PWM interrupts to the PLIC */
911
        for (j = 0; j < SIFIVE_PWM_IRQS; j++) {
912
            sysbus_connect_irq(SYS_BUS_DEVICE(&s->pwm[i]), j,
913
                               qdev_get_gpio_in(DEVICE(s->plic),
914
                                        SIFIVE_U_PWM0_IRQ0 + (i * 4) + j));
915
        }
916
    }
917

918
    create_unimplemented_device("riscv.sifive.u.gem-mgmt",
919
        memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
920

921
    create_unimplemented_device("riscv.sifive.u.dmc",
922
        memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
923

924
    create_unimplemented_device("riscv.sifive.u.l2cc",
925
        memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size);
926

927
    sysbus_realize(SYS_BUS_DEVICE(&s->spi0), errp);
928
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi0), 0,
929
                    memmap[SIFIVE_U_DEV_QSPI0].base);
930
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi0), 0,
931
                       qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI0_IRQ));
932
    sysbus_realize(SYS_BUS_DEVICE(&s->spi2), errp);
933
    sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi2), 0,
934
                    memmap[SIFIVE_U_DEV_QSPI2].base);
935
    sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi2), 0,
936
                       qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_QSPI2_IRQ));
937
}
938

939
static Property sifive_u_soc_props[] = {
940
    DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL),
941
    DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type),
942
    DEFINE_PROP_END_OF_LIST()
943
};
944

945
static void sifive_u_soc_class_init(ObjectClass *oc, void *data)
946
{
947
    DeviceClass *dc = DEVICE_CLASS(oc);
948

949
    device_class_set_props(dc, sifive_u_soc_props);
950
    dc->realize = sifive_u_soc_realize;
951
    /* Reason: Uses serial_hds in realize function, thus can't be used twice */
952
    dc->user_creatable = false;
953
}
954

955
static const TypeInfo sifive_u_soc_type_info = {
956
    .name = TYPE_RISCV_U_SOC,
957
    .parent = TYPE_DEVICE,
958
    .instance_size = sizeof(SiFiveUSoCState),
959
    .instance_init = sifive_u_soc_instance_init,
960
    .class_init = sifive_u_soc_class_init,
961
};
962

963
static void sifive_u_soc_register_types(void)
964
{
965
    type_register_static(&sifive_u_soc_type_info);
966
}
967

968
type_init(sifive_u_soc_register_types)
969