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#include "qemu/osdep.h"
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#include "qemu/cutils.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "hw/char/serial.h"
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#include "hw/misc/unimp.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_e.h"
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#include "hw/riscv/boot.h"
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#include "hw/char/sifive_uart.h"
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#include "hw/intc/riscv_aclint.h"
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#include "hw/intc/sifive_plic.h"
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#include "hw/misc/sifive_e_prci.h"
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#include "hw/misc/sifive_e_aon.h"
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#include "chardev/char.h"
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#include "sysemu/sysemu.h"
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static const MemMapEntry sifive_e_memmap[] = {
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[SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 },
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[SIFIVE_E_DEV_MROM] = { 0x1000, 0x2000 },
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[SIFIVE_E_DEV_OTP] = { 0x20000, 0x2000 },
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[SIFIVE_E_DEV_CLINT] = { 0x2000000, 0x10000 },
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[SIFIVE_E_DEV_PLIC] = { 0xc000000, 0x4000000 },
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[SIFIVE_E_DEV_AON] = { 0x10000000, 0x8000 },
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[SIFIVE_E_DEV_PRCI] = { 0x10008000, 0x8000 },
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[SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000, 0x1000 },
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[SIFIVE_E_DEV_GPIO0] = { 0x10012000, 0x1000 },
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[SIFIVE_E_DEV_UART0] = { 0x10013000, 0x1000 },
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[SIFIVE_E_DEV_QSPI0] = { 0x10014000, 0x1000 },
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[SIFIVE_E_DEV_PWM0] = { 0x10015000, 0x1000 },
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[SIFIVE_E_DEV_UART1] = { 0x10023000, 0x1000 },
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[SIFIVE_E_DEV_QSPI1] = { 0x10024000, 0x1000 },
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[SIFIVE_E_DEV_PWM1] = { 0x10025000, 0x1000 },
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[SIFIVE_E_DEV_QSPI2] = { 0x10034000, 0x1000 },
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[SIFIVE_E_DEV_PWM2] = { 0x10035000, 0x1000 },
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[SIFIVE_E_DEV_XIP] = { 0x20000000, 0x20000000 },
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[SIFIVE_E_DEV_DTIM] = { 0x80000000, 0x4000 }
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static void sifive_e_machine_init(MachineState *machine)
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MachineClass *mc = MACHINE_GET_CLASS(machine);
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const MemMapEntry *memmap = sifive_e_memmap;
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SiFiveEState *s = RISCV_E_MACHINE(machine);
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MemoryRegion *sys_mem = get_system_memory();
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if (machine->ram_size != mc->default_ram_size) {
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char *sz = size_to_str(mc->default_ram_size);
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error_report("Invalid RAM size, should be %s", sz);
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object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_E_SOC);
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qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[SIFIVE_E_DEV_DTIM].base, machine->ram);
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uint32_t reset_vec[4];
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reset_vec[1] = 0x200102b7;
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reset_vec[1] = 0x204002b7;
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reset_vec[2] = 0x00028067;
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reset_vec[0] = reset_vec[3] = 0;
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for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
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reset_vec[i] = cpu_to_le32(reset_vec[i]);
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rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
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memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
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if (machine->kernel_filename) {
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riscv_load_kernel(machine, &s->soc.cpus,
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memmap[SIFIVE_E_DEV_DTIM].base,
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static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
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SiFiveEState *s = RISCV_E_MACHINE(obj);
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static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
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SiFiveEState *s = RISCV_E_MACHINE(obj);
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static void sifive_e_machine_instance_init(Object *obj)
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SiFiveEState *s = RISCV_E_MACHINE(obj);
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static void sifive_e_machine_class_init(ObjectClass *oc, void *data)
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MachineClass *mc = MACHINE_CLASS(oc);
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mc->desc = "RISC-V Board compatible with SiFive E SDK";
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mc->init = sifive_e_machine_init;
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mc->default_cpu_type = SIFIVE_E_CPU;
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mc->default_ram_id = "riscv.sifive.e.ram";
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mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
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object_class_property_add_bool(oc, "revb", sifive_e_machine_get_revb,
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sifive_e_machine_set_revb);
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object_class_property_set_description(oc, "revb",
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"Set on to tell QEMU that it should model "
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"the revB HiFive1 board");
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static const TypeInfo sifive_e_machine_typeinfo = {
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.name = MACHINE_TYPE_NAME("sifive_e"),
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.parent = TYPE_MACHINE,
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.class_init = sifive_e_machine_class_init,
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.instance_init = sifive_e_machine_instance_init,
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.instance_size = sizeof(SiFiveEState),
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static void sifive_e_machine_init_register_types(void)
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type_register_static(&sifive_e_machine_typeinfo);
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type_init(sifive_e_machine_init_register_types)
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static void sifive_e_soc_init(Object *obj)
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MachineState *ms = MACHINE(qdev_get_machine());
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SiFiveESoCState *s = RISCV_E_SOC(obj);
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object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
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object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
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object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
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object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
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object_initialize_child(obj, "riscv.sifive.e.aon", &s->aon,
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static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
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MachineState *ms = MACHINE(qdev_get_machine());
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const MemMapEntry *memmap = sifive_e_memmap;
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SiFiveESoCState *s = RISCV_E_SOC(dev);
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MemoryRegion *sys_mem = get_system_memory();
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object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
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sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
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memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
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memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
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memory_region_add_subregion(sys_mem,
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memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
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s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
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(char *)SIFIVE_E_PLIC_HART_CONFIG, ms->smp.cpus, 0,
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SIFIVE_E_PLIC_NUM_SOURCES,
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SIFIVE_E_PLIC_NUM_PRIORITIES,
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SIFIVE_E_PLIC_PRIORITY_BASE,
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SIFIVE_E_PLIC_PENDING_BASE,
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SIFIVE_E_PLIC_ENABLE_BASE,
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SIFIVE_E_PLIC_ENABLE_STRIDE,
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SIFIVE_E_PLIC_CONTEXT_BASE,
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SIFIVE_E_PLIC_CONTEXT_STRIDE,
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memmap[SIFIVE_E_DEV_PLIC].size);
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riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base,
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0, ms->smp.cpus, false);
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riscv_aclint_mtimer_create(memmap[SIFIVE_E_DEV_CLINT].base +
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RISCV_ACLINT_SWI_SIZE,
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RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
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RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
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SIFIVE_E_LFCLK_DEFAULT_FREQ, false);
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sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->aon), errp)) {
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->aon), 0, memmap[SIFIVE_E_DEV_AON].base);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
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qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
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for (int i = 0; i < 32; i++) {
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), i,
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qdev_get_gpio_in(DEVICE(s->plic),
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SIFIVE_E_GPIO0_IRQ0 + i));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->aon), 0,
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qdev_get_gpio_in(DEVICE(s->plic),
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SIFIVE_E_AON_WDT_IRQ));
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sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
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serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
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create_unimplemented_device("riscv.sifive.e.qspi0",
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memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
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create_unimplemented_device("riscv.sifive.e.pwm0",
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memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
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sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
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serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
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create_unimplemented_device("riscv.sifive.e.qspi1",
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memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
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create_unimplemented_device("riscv.sifive.e.pwm1",
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memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
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create_unimplemented_device("riscv.sifive.e.qspi2",
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memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
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create_unimplemented_device("riscv.sifive.e.pwm2",
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memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
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memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
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memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
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memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
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static void sifive_e_soc_class_init(ObjectClass *oc, void *data)
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = sifive_e_soc_realize;
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dc->user_creatable = false;
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static const TypeInfo sifive_e_soc_type_info = {
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.name = TYPE_RISCV_E_SOC,
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.parent = TYPE_DEVICE,
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.instance_size = sizeof(SiFiveESoCState),
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.instance_init = sifive_e_soc_init,
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.class_init = sifive_e_soc_class_init,
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static void sifive_e_soc_register_types(void)
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type_register_static(&sifive_e_soc_type_info);
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type_init(sifive_e_soc_register_types)