qemu

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/*
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 * PCIe Data Object Exchange
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 *
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 * Copyright (C) 2021 Avery Design Systems, Inc.
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 *
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 * This work is licensed under the terms of the GNU GPL, version 2 or later.
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 * See the COPYING file in the top-level directory.
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "qemu/range.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie_doe.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/msix.h"
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#define DWORD_BYTE 4
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typedef struct DoeDiscoveryReq {
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    DOEHeader header;
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    uint8_t index;
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    uint8_t reserved[3];
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} QEMU_PACKED DoeDiscoveryReq;
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typedef struct DoeDiscoveryRsp {
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    DOEHeader header;
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    uint16_t vendor_id;
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    uint8_t data_obj_type;
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    uint8_t next_index;
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} QEMU_PACKED DoeDiscoveryRsp;
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static bool pcie_doe_discovery(DOECap *doe_cap)
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{
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    DoeDiscoveryReq *req = pcie_doe_get_write_mbox_ptr(doe_cap);
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    DoeDiscoveryRsp rsp;
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    uint8_t index = req->index;
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    DOEProtocol *prot;
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    /* Discard request if length does not match DoeDiscoveryReq */
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    if (pcie_doe_get_obj_len(req) <
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        DIV_ROUND_UP(sizeof(DoeDiscoveryReq), DWORD_BYTE)) {
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        return false;
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    }
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    rsp.header = (DOEHeader) {
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        .vendor_id = PCI_VENDOR_ID_PCI_SIG,
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        .data_obj_type = PCI_SIG_DOE_DISCOVERY,
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        .length = DIV_ROUND_UP(sizeof(DoeDiscoveryRsp), DWORD_BYTE),
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    };
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    /* Point to the requested protocol, index 0 must be Discovery */
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    if (index == 0) {
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        rsp.vendor_id = PCI_VENDOR_ID_PCI_SIG;
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        rsp.data_obj_type = PCI_SIG_DOE_DISCOVERY;
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    } else {
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        if (index < doe_cap->protocol_num) {
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            prot = &doe_cap->protocols[index - 1];
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            rsp.vendor_id = prot->vendor_id;
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            rsp.data_obj_type = prot->data_obj_type;
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        } else {
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            rsp.vendor_id = 0xFFFF;
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            rsp.data_obj_type = 0xFF;
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        }
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    }
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    if (index + 1 == doe_cap->protocol_num) {
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        rsp.next_index = 0;
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    } else {
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        rsp.next_index = index + 1;
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    }
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    pcie_doe_set_rsp(doe_cap, &rsp);
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    return true;
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}
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static void pcie_doe_reset_mbox(DOECap *st)
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{
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    st->read_mbox_idx = 0;
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    st->read_mbox_len = 0;
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    st->write_mbox_len = 0;
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    memset(st->read_mbox, 0, PCI_DOE_DW_SIZE_MAX * DWORD_BYTE);
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    memset(st->write_mbox, 0, PCI_DOE_DW_SIZE_MAX * DWORD_BYTE);
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}
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void pcie_doe_init(PCIDevice *dev, DOECap *doe_cap, uint16_t offset,
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                   DOEProtocol *protocols, bool intr, uint16_t vec)
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{
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    pcie_add_capability(dev, PCI_EXT_CAP_ID_DOE, 0x1, offset,
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                        PCI_DOE_SIZEOF);
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    doe_cap->pdev = dev;
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    doe_cap->offset = offset;
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    if (intr && (msi_present(dev) || msix_present(dev))) {
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        doe_cap->cap.intr = intr;
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        doe_cap->cap.vec = vec;
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    }
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    doe_cap->write_mbox = g_malloc0(PCI_DOE_DW_SIZE_MAX * DWORD_BYTE);
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    doe_cap->read_mbox = g_malloc0(PCI_DOE_DW_SIZE_MAX * DWORD_BYTE);
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    pcie_doe_reset_mbox(doe_cap);
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    doe_cap->protocols = protocols;
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    for (; protocols->vendor_id; protocols++) {
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        doe_cap->protocol_num++;
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    }
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    assert(doe_cap->protocol_num < PCI_DOE_PROTOCOL_NUM_MAX);
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    /* Increment to allow for the discovery protocol */
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    doe_cap->protocol_num++;
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}
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void pcie_doe_fini(DOECap *doe_cap)
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{
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    g_free(doe_cap->read_mbox);
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    g_free(doe_cap->write_mbox);
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    g_free(doe_cap);
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}
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uint32_t pcie_doe_build_protocol(DOEProtocol *p)
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{
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    return DATA_OBJ_BUILD_HEADER1(p->vendor_id, p->data_obj_type);
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}
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void *pcie_doe_get_write_mbox_ptr(DOECap *doe_cap)
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{
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    return doe_cap->write_mbox;
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}
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/*
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 * Copy the response to read mailbox buffer
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 * This might be called in self-defined handle_request() if a DOE response is
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 * required in the corresponding protocol
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 */
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void pcie_doe_set_rsp(DOECap *doe_cap, void *rsp)
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{
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    uint32_t len = pcie_doe_get_obj_len(rsp);
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    memcpy(doe_cap->read_mbox + doe_cap->read_mbox_len, rsp, len * DWORD_BYTE);
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    doe_cap->read_mbox_len += len;
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}
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uint32_t pcie_doe_get_obj_len(void *obj)
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{
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    uint32_t len;
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    if (!obj) {
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        return 0;
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    }
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    /* Only lower 18 bits are valid */
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    len = DATA_OBJ_LEN_MASK(((DOEHeader *)obj)->length);
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    /* PCIe r6.0 Table 6.29: a value of 00000h indicates 2^18 DW */
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    return (len) ? len : PCI_DOE_DW_SIZE_MAX;
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}
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static void pcie_doe_irq_assert(DOECap *doe_cap)
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{
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    PCIDevice *dev = doe_cap->pdev;
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    if (doe_cap->cap.intr && doe_cap->ctrl.intr) {
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        if (doe_cap->status.intr) {
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            return;
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        }
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        doe_cap->status.intr = 1;
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        if (msix_enabled(dev)) {
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            msix_notify(dev, doe_cap->cap.vec);
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        } else if (msi_enabled(dev)) {
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            msi_notify(dev, doe_cap->cap.vec);
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        }
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    }
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}
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static void pcie_doe_set_ready(DOECap *doe_cap, bool rdy)
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{
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    doe_cap->status.ready = rdy;
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    if (rdy) {
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        pcie_doe_irq_assert(doe_cap);
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    }
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}
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static void pcie_doe_set_error(DOECap *doe_cap, bool err)
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{
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    doe_cap->status.error = err;
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    if (err) {
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        pcie_doe_irq_assert(doe_cap);
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    }
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}
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/*
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 * Check incoming request in write_mbox for protocol format
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 */
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static void pcie_doe_prepare_rsp(DOECap *doe_cap)
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{
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    bool success = false;
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    int p;
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    bool (*handle_request)(DOECap *) = NULL;
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    if (doe_cap->status.error) {
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        return;
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    }
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    if (doe_cap->write_mbox[0] ==
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        DATA_OBJ_BUILD_HEADER1(PCI_VENDOR_ID_PCI_SIG, PCI_SIG_DOE_DISCOVERY)) {
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        handle_request = pcie_doe_discovery;
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    } else {
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        for (p = 0; p < doe_cap->protocol_num - 1; p++) {
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            if (doe_cap->write_mbox[0] ==
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                pcie_doe_build_protocol(&doe_cap->protocols[p])) {
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                handle_request = doe_cap->protocols[p].handle_request;
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                break;
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            }
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        }
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    }
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    /*
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     * PCIe r6 DOE 6.30.1:
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     * If the number of DW transferred does not match the
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     * indicated Length for a data object, then the
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     * data object must be silently discarded.
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     */
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    if (handle_request && (doe_cap->write_mbox_len ==
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        pcie_doe_get_obj_len(pcie_doe_get_write_mbox_ptr(doe_cap)))) {
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        success = handle_request(doe_cap);
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    }
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    if (success) {
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        pcie_doe_set_ready(doe_cap, 1);
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    } else {
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        pcie_doe_reset_mbox(doe_cap);
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    }
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}
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/*
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 * Read from DOE config space.
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 * Return false if the address not within DOE_CAP range.
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 */
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bool pcie_doe_read_config(DOECap *doe_cap, uint32_t addr, int size,
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                          uint32_t *buf)
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{
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    uint32_t shift;
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    uint16_t doe_offset = doe_cap->offset;
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    if (!range_covers_byte(doe_offset + PCI_EXP_DOE_CAP,
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                           PCI_DOE_SIZEOF - 4, addr)) {
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        return false;
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    }
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    addr -= doe_offset;
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    *buf = 0;
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    if (range_covers_byte(PCI_EXP_DOE_CAP, DWORD_BYTE, addr)) {
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        *buf = FIELD_DP32(*buf, PCI_DOE_CAP_REG, INTR_SUPP,
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                          doe_cap->cap.intr);
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        *buf = FIELD_DP32(*buf, PCI_DOE_CAP_REG, DOE_INTR_MSG_NUM,
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                          doe_cap->cap.vec);
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    } else if (range_covers_byte(PCI_EXP_DOE_CTRL, DWORD_BYTE, addr)) {
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        /* Must return ABORT=0 and GO=0 */
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        *buf = FIELD_DP32(*buf, PCI_DOE_CAP_CONTROL, DOE_INTR_EN,
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                          doe_cap->ctrl.intr);
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    } else if (range_covers_byte(PCI_EXP_DOE_STATUS, DWORD_BYTE, addr)) {
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        *buf = FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DOE_BUSY,
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                          doe_cap->status.busy);
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        *buf = FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DOE_INTR_STATUS,
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                          doe_cap->status.intr);
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        *buf = FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DOE_ERROR,
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                          doe_cap->status.error);
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        *buf = FIELD_DP32(*buf, PCI_DOE_CAP_STATUS, DATA_OBJ_RDY,
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                          doe_cap->status.ready);
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    /* Mailbox should be DW accessed */
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    } else if (addr == PCI_EXP_DOE_RD_DATA_MBOX && size == DWORD_BYTE) {
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        if (doe_cap->status.ready && !doe_cap->status.error) {
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            *buf = doe_cap->read_mbox[doe_cap->read_mbox_idx];
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        }
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    }
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    /* Process Alignment */
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    shift = addr % DWORD_BYTE;
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    *buf = extract32(*buf, shift * 8, size * 8);
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    return true;
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}
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/*
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 * Write to DOE config space.
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 * Return if the address not within DOE_CAP range or receives an abort
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 */
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void pcie_doe_write_config(DOECap *doe_cap,
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                           uint32_t addr, uint32_t val, int size)
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{
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    uint16_t doe_offset = doe_cap->offset;
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    uint32_t shift;
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    if (!range_covers_byte(doe_offset + PCI_EXP_DOE_CAP,
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                           PCI_DOE_SIZEOF - 4, addr)) {
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        return;
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    }
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    /* Process Alignment */
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    shift = addr % DWORD_BYTE;
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    addr -= (doe_offset + shift);
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    val = deposit32(val, shift * 8, size * 8, val);
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    switch (addr) {
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    case PCI_EXP_DOE_CTRL:
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        if (FIELD_EX32(val, PCI_DOE_CAP_CONTROL, DOE_ABORT)) {
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            pcie_doe_set_ready(doe_cap, 0);
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            pcie_doe_set_error(doe_cap, 0);
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            pcie_doe_reset_mbox(doe_cap);
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            return;
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        }
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        if (FIELD_EX32(val, PCI_DOE_CAP_CONTROL, DOE_GO)) {
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            pcie_doe_prepare_rsp(doe_cap);
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        }
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        if (FIELD_EX32(val, PCI_DOE_CAP_CONTROL, DOE_INTR_EN)) {
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            doe_cap->ctrl.intr = 1;
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        /* Clear interrupt bit located within the first byte */
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        } else if (shift == 0) {
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            doe_cap->ctrl.intr = 0;
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        }
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        break;
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    case PCI_EXP_DOE_STATUS:
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        if (FIELD_EX32(val, PCI_DOE_CAP_STATUS, DOE_INTR_STATUS)) {
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            doe_cap->status.intr = 0;
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        }
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        break;
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    case PCI_EXP_DOE_RD_DATA_MBOX:
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        /* Mailbox should be DW accessed */
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        if (size != DWORD_BYTE) {
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            return;
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        }
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        doe_cap->read_mbox_idx++;
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        if (doe_cap->read_mbox_idx == doe_cap->read_mbox_len) {
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            pcie_doe_reset_mbox(doe_cap);
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            pcie_doe_set_ready(doe_cap, 0);
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        } else if (doe_cap->read_mbox_idx > doe_cap->read_mbox_len) {
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            /* Underflow */
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            pcie_doe_set_error(doe_cap, 1);
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        }
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        break;
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    case PCI_EXP_DOE_WR_DATA_MBOX:
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        /* Mailbox should be DW accessed */
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        if (size != DWORD_BYTE) {
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            return;
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        }
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        doe_cap->write_mbox[doe_cap->write_mbox_len] = val;
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        doe_cap->write_mbox_len++;
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        break;
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    case PCI_EXP_DOE_CAP:
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        /* fallthrough */
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    default:
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        break;
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    }
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}
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