qemu

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/*
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 * QEMU PCI bus manager
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 *
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 * Copyright (c) 2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to dea
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * split out from pci.c
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 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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 *                    VA Linux Systems Japan K.K.
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 */
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "qemu/module.h"
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#include "qemu/range.h"
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#include "qapi/error.h"
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#include "hw/acpi/acpi_aml_interface.h"
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#include "hw/acpi/pci.h"
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#include "hw/qdev-properties.h"
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/* PCI bridge subsystem vendor ID helper functions */
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#define PCI_SSVID_SIZEOF        8
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#define PCI_SSVID_SVID          4
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#define PCI_SSVID_SSID          6
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int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
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                          uint16_t svid, uint16_t ssid,
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                          Error **errp)
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{
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    int pos;
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    pos = pci_add_capability(dev, PCI_CAP_ID_SSVID, offset,
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                             PCI_SSVID_SIZEOF, errp);
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    if (pos < 0) {
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        return pos;
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    }
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    pci_set_word(dev->config + pos + PCI_SSVID_SVID, svid);
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    pci_set_word(dev->config + pos + PCI_SSVID_SSID, ssid);
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    return pos;
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}
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/* Accessor function to get parent bridge device from pci bus. */
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PCIDevice *pci_bridge_get_device(PCIBus *bus)
67
{
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    return bus->parent_dev;
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}
70

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/* Accessor function to get secondary bus from pci-to-pci bridge device */
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PCIBus *pci_bridge_get_sec_bus(PCIBridge *br)
73
{
74
    return &br->sec_bus;
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}
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77
static uint32_t pci_config_get_io_base(const PCIDevice *d,
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                                       uint32_t base, uint32_t base_upper16)
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{
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    uint32_t val;
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82
    val = ((uint32_t)d->config[base] & PCI_IO_RANGE_MASK) << 8;
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    if (d->config[base] & PCI_IO_RANGE_TYPE_32) {
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        val |= (uint32_t)pci_get_word(d->config + base_upper16) << 16;
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    }
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    return val;
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}
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static pcibus_t pci_config_get_memory_base(const PCIDevice *d, uint32_t base)
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{
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    return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
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        << 16;
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}
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static pcibus_t pci_config_get_pref_base(const PCIDevice *d,
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                                         uint32_t base, uint32_t upper)
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{
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    pcibus_t tmp;
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    pcibus_t val;
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    tmp = (pcibus_t)pci_get_word(d->config + base);
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    val = (tmp & PCI_PREF_RANGE_MASK) << 16;
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    if (tmp & PCI_PREF_RANGE_TYPE_64) {
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        val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
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    }
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    return val;
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}
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/* accessor function to get bridge filtering base address */
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pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type)
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{
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    pcibus_t base;
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    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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        base = pci_config_get_io_base(bridge,
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                                      PCI_IO_BASE, PCI_IO_BASE_UPPER16);
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    } else {
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        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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            base = pci_config_get_pref_base(
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                bridge, PCI_PREF_MEMORY_BASE, PCI_PREF_BASE_UPPER32);
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        } else {
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            base = pci_config_get_memory_base(bridge, PCI_MEMORY_BASE);
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        }
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    }
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    return base;
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}
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/* accessor function to get bridge filtering limit */
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pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type)
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{
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    pcibus_t limit;
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    if (type & PCI_BASE_ADDRESS_SPACE_IO) {
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        limit = pci_config_get_io_base(bridge,
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                                      PCI_IO_LIMIT, PCI_IO_LIMIT_UPPER16);
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        limit |= 0xfff;         /* PCI bridge spec 3.2.5.6. */
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    } else {
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        if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
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            limit = pci_config_get_pref_base(
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                bridge, PCI_PREF_MEMORY_LIMIT, PCI_PREF_LIMIT_UPPER32);
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        } else {
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            limit = pci_config_get_memory_base(bridge, PCI_MEMORY_LIMIT);
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        }
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        limit |= 0xfffff;       /* PCI bridge spec 3.2.5.{1, 8}. */
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    }
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    return limit;
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}
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static void pci_bridge_init_alias(PCIBridge *bridge, MemoryRegion *alias,
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                                  uint8_t type, const char *name,
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                                  MemoryRegion *space,
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                                  MemoryRegion *parent_space,
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                                  bool enabled)
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{
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    PCIDevice *bridge_dev = PCI_DEVICE(bridge);
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    pcibus_t base = pci_bridge_get_base(bridge_dev, type);
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    pcibus_t limit = pci_bridge_get_limit(bridge_dev, type);
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    /* TODO: this doesn't handle base = 0 limit = 2^64 - 1 correctly.
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     * Apparently no way to do this with existing memory APIs. */
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    pcibus_t size = enabled && limit >= base ? limit + 1 - base : 0;
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    memory_region_init_alias(alias, OBJECT(bridge), name, space, base, size);
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    memory_region_add_subregion_overlap(parent_space, base, alias, 1);
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}
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static void pci_bridge_init_vga_aliases(PCIBridge *br, PCIBus *parent,
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                                        MemoryRegion *alias_vga)
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{
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    PCIDevice *pd = PCI_DEVICE(br);
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    uint16_t brctl = pci_get_word(pd->config + PCI_BRIDGE_CONTROL);
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    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_LO], OBJECT(br),
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                             "pci_bridge_vga_io_lo", &br->address_space_io,
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                             QEMU_PCI_VGA_IO_LO_BASE, QEMU_PCI_VGA_IO_LO_SIZE);
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    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_IO_HI], OBJECT(br),
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                             "pci_bridge_vga_io_hi", &br->address_space_io,
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                             QEMU_PCI_VGA_IO_HI_BASE, QEMU_PCI_VGA_IO_HI_SIZE);
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    memory_region_init_alias(&alias_vga[QEMU_PCI_VGA_MEM], OBJECT(br),
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                             "pci_bridge_vga_mem", &br->address_space_mem,
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                             QEMU_PCI_VGA_MEM_BASE, QEMU_PCI_VGA_MEM_SIZE);
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    if (brctl & PCI_BRIDGE_CTL_VGA) {
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        pci_register_vga(pd, &alias_vga[QEMU_PCI_VGA_MEM],
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                         &alias_vga[QEMU_PCI_VGA_IO_LO],
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                         &alias_vga[QEMU_PCI_VGA_IO_HI]);
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    }
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}
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static void pci_bridge_region_init(PCIBridge *br)
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{
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    PCIDevice *pd = PCI_DEVICE(br);
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    PCIBus *parent = pci_get_bus(pd);
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    PCIBridgeWindows *w = &br->windows;
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    uint16_t cmd = pci_get_word(pd->config + PCI_COMMAND);
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    pci_bridge_init_alias(br, &w->alias_pref_mem,
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                          PCI_BASE_ADDRESS_MEM_PREFETCH,
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                          "pci_bridge_pref_mem",
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                          &br->address_space_mem,
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                          parent->address_space_mem,
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                          cmd & PCI_COMMAND_MEMORY);
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    pci_bridge_init_alias(br, &w->alias_mem,
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                          PCI_BASE_ADDRESS_SPACE_MEMORY,
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                          "pci_bridge_mem",
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                          &br->address_space_mem,
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                          parent->address_space_mem,
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                          cmd & PCI_COMMAND_MEMORY);
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    pci_bridge_init_alias(br, &w->alias_io,
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                          PCI_BASE_ADDRESS_SPACE_IO,
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                          "pci_bridge_io",
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                          &br->address_space_io,
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                          parent->address_space_io,
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                          cmd & PCI_COMMAND_IO);
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    pci_bridge_init_vga_aliases(br, parent, w->alias_vga);
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}
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static void pci_bridge_region_del(PCIBridge *br, PCIBridgeWindows *w)
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{
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    PCIDevice *pd = PCI_DEVICE(br);
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    PCIBus *parent = pci_get_bus(pd);
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    memory_region_del_subregion(parent->address_space_io, &w->alias_io);
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    memory_region_del_subregion(parent->address_space_mem, &w->alias_mem);
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    memory_region_del_subregion(parent->address_space_mem, &w->alias_pref_mem);
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    pci_unregister_vga(pd);
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}
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static void pci_bridge_region_cleanup(PCIBridge *br, PCIBridgeWindows *w)
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{
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    object_unparent(OBJECT(&w->alias_io));
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    object_unparent(OBJECT(&w->alias_mem));
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    object_unparent(OBJECT(&w->alias_pref_mem));
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    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_LO]));
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    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_IO_HI]));
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    object_unparent(OBJECT(&w->alias_vga[QEMU_PCI_VGA_MEM]));
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}
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void pci_bridge_update_mappings(PCIBridge *br)
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{
240
    PCIBridgeWindows *w = &br->windows;
241

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    /* Make updates atomic to: handle the case of one VCPU updating the bridge
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     * while another accesses an unaffected region. */
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    memory_region_transaction_begin();
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    pci_bridge_region_del(br, w);
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    pci_bridge_region_cleanup(br, w);
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    pci_bridge_region_init(br);
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    memory_region_transaction_commit();
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}
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/* default write_config function for PCI-to-PCI bridge */
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void pci_bridge_write_config(PCIDevice *d,
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                             uint32_t address, uint32_t val, int len)
254
{
255
    PCIBridge *s = PCI_BRIDGE(d);
256
    uint16_t oldctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
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    uint16_t newctl;
258

259
    pci_default_write_config(d, address, val, len);
260

261
    if (ranges_overlap(address, len, PCI_COMMAND, 2) ||
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263
        /* io base/limit */
264
        ranges_overlap(address, len, PCI_IO_BASE, 2) ||
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266
        /* memory base/limit, prefetchable base/limit and
267
           io base/limit upper 16 */
268
        ranges_overlap(address, len, PCI_MEMORY_BASE, 20) ||
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270
        /* vga enable */
271
        ranges_overlap(address, len, PCI_BRIDGE_CONTROL, 2)) {
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        pci_bridge_update_mappings(s);
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    }
274

275
    newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL);
276
    if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) {
277
        /* Trigger hot reset on 0->1 transition. */
278
        bus_cold_reset(BUS(&s->sec_bus));
279
    }
280
}
281

282
void pci_bridge_disable_base_limit(PCIDevice *dev)
283
{
284
    uint8_t *conf = dev->config;
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286
    pci_byte_test_and_set_mask(conf + PCI_IO_BASE,
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                               PCI_IO_RANGE_MASK & 0xff);
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    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
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                                 PCI_IO_RANGE_MASK & 0xff);
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    pci_word_test_and_set_mask(conf + PCI_MEMORY_BASE,
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                               PCI_MEMORY_RANGE_MASK & 0xffff);
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    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
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                                 PCI_MEMORY_RANGE_MASK & 0xffff);
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    pci_word_test_and_set_mask(conf + PCI_PREF_MEMORY_BASE,
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                               PCI_PREF_RANGE_MASK & 0xffff);
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    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
297
                                 PCI_PREF_RANGE_MASK & 0xffff);
298
    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
299
    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
300
}
301

302
/* reset bridge specific configuration registers */
303
void pci_bridge_reset(DeviceState *qdev)
304
{
305
    PCIDevice *dev = PCI_DEVICE(qdev);
306
    uint8_t *conf = dev->config;
307

308
    conf[PCI_PRIMARY_BUS] = 0;
309
    conf[PCI_SECONDARY_BUS] = 0;
310
    conf[PCI_SUBORDINATE_BUS] = 0;
311
    conf[PCI_SEC_LATENCY_TIMER] = 0;
312

313
    /*
314
     * the default values for base/limit registers aren't specified
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     * in the PCI-to-PCI-bridge spec. So we don't touch them here.
316
     * Each implementation can override it.
317
     * typical implementation does
318
     * zero base/limit registers or
319
     * disable forwarding: pci_bridge_disable_base_limit()
320
     * If disable forwarding is wanted, call pci_bridge_disable_base_limit()
321
     * after this function.
322
     */
323
    pci_byte_test_and_clear_mask(conf + PCI_IO_BASE,
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                                 PCI_IO_RANGE_MASK & 0xff);
325
    pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT,
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                                 PCI_IO_RANGE_MASK & 0xff);
327
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_BASE,
328
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
329
    pci_word_test_and_clear_mask(conf + PCI_MEMORY_LIMIT,
330
                                 PCI_MEMORY_RANGE_MASK & 0xffff);
331
    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_BASE,
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                                 PCI_PREF_RANGE_MASK & 0xffff);
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    pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
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                                 PCI_PREF_RANGE_MASK & 0xffff);
335
    pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
336
    pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
337

338
    pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
339
}
340

341
/* default qdev initialization function for PCI-to-PCI bridge */
342
void pci_bridge_initfn(PCIDevice *dev, const char *typename)
343
{
344
    PCIBus *parent = pci_get_bus(dev);
345
    PCIBridge *br = PCI_BRIDGE(dev);
346
    PCIBus *sec_bus = &br->sec_bus;
347

348
    pci_word_test_and_set_mask(dev->config + PCI_STATUS,
349
                               PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
350

351
    /*
352
     * TODO: We implement VGA Enable in the Bridge Control Register
353
     * therefore per the PCI to PCI bridge spec we must also implement
354
     * VGA Palette Snooping.  When done, set this bit writable:
355
     *
356
     * pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND,
357
     *                            PCI_COMMAND_VGA_PALETTE);
358
     */
359

360
    pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
361
    dev->config[PCI_HEADER_TYPE] =
362
        (dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
363
        PCI_HEADER_TYPE_BRIDGE;
364
    pci_set_word(dev->config + PCI_SEC_STATUS,
365
                 PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
366

367
    /*
368
     * If we don't specify the name, the bus will be addressed as <id>.0, where
369
     * id is the device id.
370
     * Since PCI Bridge devices have a single bus each, we don't need the index:
371
     * let users address the bus using the device name.
372
     */
373
    if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
374
            br->bus_name = dev->qdev.id;
375
    }
376

377
    qbus_init(sec_bus, sizeof(br->sec_bus), typename, DEVICE(dev),
378
              br->bus_name);
379
    sec_bus->parent_dev = dev;
380
    sec_bus->map_irq = br->map_irq ? br->map_irq : pci_swizzle_map_irq_fn;
381
    sec_bus->address_space_mem = &br->address_space_mem;
382
    memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
383
    sec_bus->address_space_io = &br->address_space_io;
384
    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
385
                       4 * GiB);
386
    pci_bridge_region_init(br);
387
    QLIST_INIT(&sec_bus->child);
388
    QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);
389

390
    /* For express secondary buses, secondary latency timer is RO 0 */
391
    if (pci_bus_is_express(sec_bus) && !br->pcie_writeable_slt_bug) {
392
        dev->wmask[PCI_SEC_LATENCY_TIMER] = 0;
393
    }
394
}
395

396
/* default qdev clean up function for PCI-to-PCI bridge */
397
void pci_bridge_exitfn(PCIDevice *pci_dev)
398
{
399
    PCIBridge *s = PCI_BRIDGE(pci_dev);
400
    assert(QLIST_EMPTY(&s->sec_bus.child));
401
    QLIST_REMOVE(&s->sec_bus, sibling);
402
    pci_bridge_region_del(s, &s->windows);
403
    pci_bridge_region_cleanup(s, &s->windows);
404
    /* object_unparent() is called automatically during device deletion */
405
}
406

407
/*
408
 * before qdev initialization(qdev_init()), this function sets bus_name and
409
 * map_irq callback which are necessary for pci_bridge_initfn() to
410
 * initialize bus.
411
 */
412
void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
413
                        pci_map_irq_fn map_irq)
414
{
415
    br->map_irq = map_irq;
416
    br->bus_name = bus_name;
417
}
418

419

420
int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset,
421
                                     PCIResReserve res_reserve, Error **errp)
422
{
423
    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
424
        res_reserve.mem_pref_64 != (uint64_t)-1) {
425
        error_setg(errp,
426
                   "PCI resource reserve cap: PREF32 and PREF64 conflict");
427
        return -EINVAL;
428
    }
429

430
    if (res_reserve.mem_non_pref != (uint64_t)-1 &&
431
        res_reserve.mem_non_pref >= 4 * GiB) {
432
        error_setg(errp,
433
                   "PCI resource reserve cap: mem-reserve must be less than 4G");
434
        return -EINVAL;
435
    }
436

437
    if (res_reserve.mem_pref_32 != (uint64_t)-1 &&
438
        res_reserve.mem_pref_32 >= 4 * GiB) {
439
        error_setg(errp,
440
                   "PCI resource reserve cap: pref32-reserve  must be less than 4G");
441
        return -EINVAL;
442
    }
443

444
    if (res_reserve.bus == (uint32_t)-1 &&
445
        res_reserve.io == (uint64_t)-1 &&
446
        res_reserve.mem_non_pref == (uint64_t)-1 &&
447
        res_reserve.mem_pref_32 == (uint64_t)-1 &&
448
        res_reserve.mem_pref_64 == (uint64_t)-1) {
449
        return 0;
450
    }
451

452
    size_t cap_len = sizeof(PCIBridgeQemuCap);
453
    PCIBridgeQemuCap cap = {
454
            .len = cap_len,
455
            .type = REDHAT_PCI_CAP_RESOURCE_RESERVE,
456
            .bus_res = cpu_to_le32(res_reserve.bus),
457
            .io = cpu_to_le64(res_reserve.io),
458
            .mem = cpu_to_le32(res_reserve.mem_non_pref),
459
            .mem_pref_32 = cpu_to_le32(res_reserve.mem_pref_32),
460
            .mem_pref_64 = cpu_to_le64(res_reserve.mem_pref_64)
461
    };
462

463
    int offset = pci_add_capability(dev, PCI_CAP_ID_VNDR,
464
                                    cap_offset, cap_len, errp);
465
    if (offset < 0) {
466
        return offset;
467
    }
468

469
    memcpy(dev->config + offset + PCI_CAP_FLAGS,
470
           (char *)&cap + PCI_CAP_FLAGS,
471
           cap_len - PCI_CAP_FLAGS);
472
    return 0;
473
}
474

475
static Property pci_bridge_properties[] = {
476
    DEFINE_PROP_BOOL("x-pci-express-writeable-slt-bug", PCIBridge,
477
                     pcie_writeable_slt_bug, false),
478
    DEFINE_PROP_END_OF_LIST(),
479
};
480

481
static void pci_bridge_class_init(ObjectClass *klass, void *data)
482
{
483
    AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
484
    DeviceClass *k = DEVICE_CLASS(klass);
485

486
    device_class_set_props(k, pci_bridge_properties);
487
    adevc->build_dev_aml = build_pci_bridge_aml;
488
}
489

490
static const TypeInfo pci_bridge_type_info = {
491
    .name = TYPE_PCI_BRIDGE,
492
    .parent = TYPE_PCI_DEVICE,
493
    .instance_size = sizeof(PCIBridge),
494
    .class_init = pci_bridge_class_init,
495
    .abstract = true,
496
    .interfaces = (InterfaceInfo[]) {
497
        { TYPE_ACPI_DEV_AML_IF },
498
        { },
499
    },
500
};
501

502
static void pci_bridge_register_types(void)
503
{
504
    type_register_static(&pci_bridge_type_info);
505
}
506

507
type_init(pci_bridge_register_types)
508