qemu

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/*
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 * msi.c
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 *
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 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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 *                    VA Linux Systems Japan K.K.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "qemu/osdep.h"
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#include "hw/pci/msi.h"
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#include "hw/xen/xen.h"
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#include "qemu/range.h"
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#include "qapi/error.h"
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#include "sysemu/xen.h"
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#include "hw/i386/kvm/xen_evtchn.h"
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/* PCI_MSI_ADDRESS_LO */
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#define PCI_MSI_ADDRESS_LO_MASK         (~0x3)
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/* If we get rid of cap allocator, we won't need those. */
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#define PCI_MSI_32_SIZEOF       0x0a
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#define PCI_MSI_64_SIZEOF       0x0e
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#define PCI_MSI_32M_SIZEOF      0x14
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#define PCI_MSI_64M_SIZEOF      0x18
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#define PCI_MSI_VECTORS_MAX     32
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/*
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 * Flag for interrupt controllers to declare broken MSI/MSI-X support.
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 * values: false - broken; true - non-broken.
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 *
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 * Setting this flag to false will remove MSI/MSI-X capability from all devices.
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 *
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 * It is preferable for controllers to set this to true (non-broken) even if
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 * they do not actually support MSI/MSI-X: guests normally probe the controller
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 * type and do not attempt to enable MSI/MSI-X with interrupt controllers not
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 * supporting such, so removing the capability is not required, and
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 * it seems cleaner to have a given device look the same for all boards.
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 *
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 * TODO: some existing controllers violate the above rule. Identify and fix them.
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 */
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bool msi_nonbroken;
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/* If we get rid of cap allocator, we won't need this. */
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static inline uint8_t msi_cap_sizeof(uint16_t flags)
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{
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    switch (flags & (PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT)) {
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    case PCI_MSI_FLAGS_MASKBIT | PCI_MSI_FLAGS_64BIT:
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        return PCI_MSI_64M_SIZEOF;
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    case PCI_MSI_FLAGS_64BIT:
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        return PCI_MSI_64_SIZEOF;
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    case PCI_MSI_FLAGS_MASKBIT:
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        return PCI_MSI_32M_SIZEOF;
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    case 0:
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        return PCI_MSI_32_SIZEOF;
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    default:
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        abort();
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        break;
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    }
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    return 0;
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}
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//#define MSI_DEBUG
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#ifdef MSI_DEBUG
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# define MSI_DPRINTF(fmt, ...)                                          \
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    fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
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#else
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# define MSI_DPRINTF(fmt, ...)  do { } while (0)
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#endif
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#define MSI_DEV_PRINTF(dev, fmt, ...)                                   \
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    MSI_DPRINTF("%s:%x " fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
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static inline unsigned int msi_nr_vectors(uint16_t flags)
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{
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    return 1U <<
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        ((flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE));
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}
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static inline uint8_t msi_flags_off(const PCIDevice* dev)
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{
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    return dev->msi_cap + PCI_MSI_FLAGS;
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}
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static inline uint8_t msi_address_lo_off(const PCIDevice* dev)
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{
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    return dev->msi_cap + PCI_MSI_ADDRESS_LO;
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}
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static inline uint8_t msi_address_hi_off(const PCIDevice* dev)
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{
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    return dev->msi_cap + PCI_MSI_ADDRESS_HI;
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}
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static inline uint8_t msi_data_off(const PCIDevice* dev, bool msi64bit)
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{
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    return dev->msi_cap + (msi64bit ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32);
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}
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static inline uint8_t msi_mask_off(const PCIDevice* dev, bool msi64bit)
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{
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    return dev->msi_cap + (msi64bit ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32);
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}
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static inline uint8_t msi_pending_off(const PCIDevice* dev, bool msi64bit)
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{
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    return dev->msi_cap + (msi64bit ? PCI_MSI_PENDING_64 : PCI_MSI_PENDING_32);
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}
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/*
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 * Special API for POWER to configure the vectors through
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 * a side channel. Should never be used by devices.
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 */
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void msi_set_message(PCIDevice *dev, MSIMessage msg)
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{
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    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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    if (msi64bit) {
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        pci_set_quad(dev->config + msi_address_lo_off(dev), msg.address);
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    } else {
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        pci_set_long(dev->config + msi_address_lo_off(dev), msg.address);
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    }
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    pci_set_word(dev->config + msi_data_off(dev, msi64bit), msg.data);
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}
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static MSIMessage msi_prepare_message(PCIDevice *dev, unsigned int vector)
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{
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    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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    unsigned int nr_vectors = msi_nr_vectors(flags);
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    MSIMessage msg;
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    assert(vector < nr_vectors);
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    if (msi64bit) {
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        msg.address = pci_get_quad(dev->config + msi_address_lo_off(dev));
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    } else {
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        msg.address = pci_get_long(dev->config + msi_address_lo_off(dev));
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    }
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    /* upper bit 31:16 is zero */
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    msg.data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
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    if (nr_vectors > 1) {
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        msg.data &= ~(nr_vectors - 1);
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        msg.data |= vector;
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    }
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    return msg;
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}
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MSIMessage msi_get_message(PCIDevice *dev, unsigned int vector)
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{
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    return dev->msi_prepare_message(dev, vector);
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}
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bool msi_enabled(const PCIDevice *dev)
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{
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    return msi_present(dev) &&
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        (pci_get_word(dev->config + msi_flags_off(dev)) &
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         PCI_MSI_FLAGS_ENABLE);
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}
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/*
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 * Make PCI device @dev MSI-capable.
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 * Non-zero @offset puts capability MSI at that offset in PCI config
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 * space.
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 * @nr_vectors is the number of MSI vectors (1, 2, 4, 8, 16 or 32).
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 * If @msi64bit, make the device capable of sending a 64-bit message
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 * address.
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 * If @msi_per_vector_mask, make the device support per-vector masking.
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 * @errp is for returning errors.
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 * Return 0 on success; set @errp and return -errno on error.
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 *
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 * -ENOTSUP means lacking msi support for a msi-capable platform.
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 * -EINVAL means capability overlap, happens when @offset is non-zero,
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 *  also means a programming error, except device assignment, which can check
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 *  if a real HW is broken.
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 */
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int msi_init(struct PCIDevice *dev, uint8_t offset,
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             unsigned int nr_vectors, bool msi64bit,
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             bool msi_per_vector_mask, Error **errp)
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{
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    unsigned int vectors_order;
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    uint16_t flags;
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    uint8_t cap_size;
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    int config_offset;
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    if (!msi_nonbroken) {
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        error_setg(errp, "MSI is not supported by interrupt controller");
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        return -ENOTSUP;
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    }
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    MSI_DEV_PRINTF(dev,
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                   "init offset: 0x%"PRIx8" vector: %"PRId8
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                   " 64bit %d mask %d\n",
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                   offset, nr_vectors, msi64bit, msi_per_vector_mask);
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    assert(!(nr_vectors & (nr_vectors - 1)));   /* power of 2 */
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    assert(nr_vectors > 0);
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    assert(nr_vectors <= PCI_MSI_VECTORS_MAX);
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    /* the nr of MSI vectors is up to 32 */
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    vectors_order = ctz32(nr_vectors);
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    flags = vectors_order << ctz32(PCI_MSI_FLAGS_QMASK);
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    if (msi64bit) {
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        flags |= PCI_MSI_FLAGS_64BIT;
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    }
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    if (msi_per_vector_mask) {
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        flags |= PCI_MSI_FLAGS_MASKBIT;
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    }
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    cap_size = msi_cap_sizeof(flags);
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    config_offset = pci_add_capability(dev, PCI_CAP_ID_MSI, offset,
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                                        cap_size, errp);
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    if (config_offset < 0) {
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        return config_offset;
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    }
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    dev->msi_cap = config_offset;
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    dev->cap_present |= QEMU_PCI_CAP_MSI;
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    pci_set_word(dev->config + msi_flags_off(dev), flags);
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    pci_set_word(dev->wmask + msi_flags_off(dev),
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                 PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
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    pci_set_long(dev->wmask + msi_address_lo_off(dev),
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                 PCI_MSI_ADDRESS_LO_MASK);
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    if (msi64bit) {
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        pci_set_long(dev->wmask + msi_address_hi_off(dev), 0xffffffff);
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    }
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    pci_set_word(dev->wmask + msi_data_off(dev, msi64bit), 0xffff);
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    if (msi_per_vector_mask) {
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        /* Make mask bits 0 to nr_vectors - 1 writable. */
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        pci_set_long(dev->wmask + msi_mask_off(dev, msi64bit),
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                     0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors));
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    }
251

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    dev->msi_prepare_message = msi_prepare_message;
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    return 0;
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}
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void msi_uninit(struct PCIDevice *dev)
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{
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    uint16_t flags;
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    uint8_t cap_size;
261

262
    if (!msi_present(dev)) {
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        return;
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    }
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    flags = pci_get_word(dev->config + msi_flags_off(dev));
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    cap_size = msi_cap_sizeof(flags);
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    pci_del_capability(dev, PCI_CAP_ID_MSI, cap_size);
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    dev->cap_present &= ~QEMU_PCI_CAP_MSI;
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    dev->msi_prepare_message = NULL;
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    MSI_DEV_PRINTF(dev, "uninit\n");
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}
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void msi_reset(PCIDevice *dev)
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{
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    uint16_t flags;
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    bool msi64bit;
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    if (!msi_present(dev)) {
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        return;
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    }
282

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    flags = pci_get_word(dev->config + msi_flags_off(dev));
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    flags &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
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    msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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    pci_set_word(dev->config + msi_flags_off(dev), flags);
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    pci_set_long(dev->config + msi_address_lo_off(dev), 0);
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    if (msi64bit) {
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        pci_set_long(dev->config + msi_address_hi_off(dev), 0);
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    }
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    pci_set_word(dev->config + msi_data_off(dev, msi64bit), 0);
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    if (flags & PCI_MSI_FLAGS_MASKBIT) {
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        pci_set_long(dev->config + msi_mask_off(dev, msi64bit), 0);
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        pci_set_long(dev->config + msi_pending_off(dev, msi64bit), 0);
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    }
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    MSI_DEV_PRINTF(dev, "reset\n");
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}
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bool msi_is_masked(const PCIDevice *dev, unsigned int vector)
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{
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    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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    uint32_t mask, data;
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    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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    assert(vector < PCI_MSI_VECTORS_MAX);
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    if (!(flags & PCI_MSI_FLAGS_MASKBIT)) {
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        return false;
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    }
310

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    data = pci_get_word(dev->config + msi_data_off(dev, msi64bit));
312
    if (xen_enabled() && xen_is_pirq_msi(data)) {
313
        return false;
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    }
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    mask = pci_get_long(dev->config +
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                        msi_mask_off(dev, flags & PCI_MSI_FLAGS_64BIT));
318
    return mask & (1U << vector);
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}
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void msi_set_mask(PCIDevice *dev, int vector, bool mask, Error **errp)
322
{
323
    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
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    uint32_t irq_state, vector_mask, pending;
326

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    if (vector >= PCI_MSI_VECTORS_MAX) {
328
        error_setg(errp, "msi: vector %d not allocated. max vector is %d",
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                   vector, (PCI_MSI_VECTORS_MAX - 1));
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        return;
331
    }
332

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    vector_mask = (1U << vector);
334

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    irq_state = pci_get_long(dev->config + msi_mask_off(dev, msi64bit));
336

337
    if (mask) {
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        irq_state |= vector_mask;
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    } else {
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        irq_state &= ~vector_mask;
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    }
342

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    pci_set_long(dev->config + msi_mask_off(dev, msi64bit), irq_state);
344

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    pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
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    if (!mask && (pending & vector_mask)) {
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        pending &= ~vector_mask;
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        pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
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        msi_notify(dev, vector);
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    }
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}
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void msi_notify(PCIDevice *dev, unsigned int vector)
354
{
355
    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
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    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
357
    unsigned int nr_vectors = msi_nr_vectors(flags);
358
    MSIMessage msg;
359

360
    assert(vector < nr_vectors);
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    if (msi_is_masked(dev, vector)) {
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        assert(flags & PCI_MSI_FLAGS_MASKBIT);
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        pci_long_test_and_set_mask(
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            dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
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        MSI_DEV_PRINTF(dev, "pending vector 0x%x\n", vector);
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        return;
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    }
368

369
    msg = msi_get_message(dev, vector);
370

371
    MSI_DEV_PRINTF(dev,
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                   "notify vector 0x%x"
373
                   " address: 0x%"PRIx64" data: 0x%"PRIx32"\n",
374
                   vector, msg.address, msg.data);
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    msi_send_message(dev, msg);
376
}
377

378
void msi_send_message(PCIDevice *dev, MSIMessage msg)
379
{
380
    dev->msi_trigger(dev, msg);
381
}
382

383
/* Normally called by pci_default_write_config(). */
384
void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
385
{
386
    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
387
    bool msi64bit = flags & PCI_MSI_FLAGS_64BIT;
388
    bool msi_per_vector_mask = flags & PCI_MSI_FLAGS_MASKBIT;
389
    unsigned int nr_vectors;
390
    uint8_t log_num_vecs;
391
    uint8_t log_max_vecs;
392
    unsigned int vector;
393
    uint32_t pending;
394

395
    if (!msi_present(dev) ||
396
        !ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
397
        return;
398
    }
399

400
#ifdef MSI_DEBUG
401
    MSI_DEV_PRINTF(dev, "addr 0x%"PRIx32" val 0x%"PRIx32" len %d\n",
402
                   addr, val, len);
403
    MSI_DEV_PRINTF(dev, "ctrl: 0x%"PRIx16" address: 0x%"PRIx32,
404
                   flags,
405
                   pci_get_long(dev->config + msi_address_lo_off(dev)));
406
    if (msi64bit) {
407
        fprintf(stderr, " address-hi: 0x%"PRIx32,
408
                pci_get_long(dev->config + msi_address_hi_off(dev)));
409
    }
410
    fprintf(stderr, " data: 0x%"PRIx16,
411
            pci_get_word(dev->config + msi_data_off(dev, msi64bit)));
412
    if (flags & PCI_MSI_FLAGS_MASKBIT) {
413
        fprintf(stderr, " mask 0x%"PRIx32" pending 0x%"PRIx32,
414
                pci_get_long(dev->config + msi_mask_off(dev, msi64bit)),
415
                pci_get_long(dev->config + msi_pending_off(dev, msi64bit)));
416
    }
417
    fprintf(stderr, "\n");
418
#endif
419

420
    if (xen_mode == XEN_EMULATE) {
421
        for (vector = 0; vector < msi_nr_vectors(flags); vector++) {
422
            MSIMessage msg = msi_prepare_message(dev, vector);
423

424
            xen_evtchn_snoop_msi(dev, false, vector, msg.address, msg.data,
425
                                 msi_is_masked(dev, vector));
426
        }
427
    }
428

429
    if (!(flags & PCI_MSI_FLAGS_ENABLE)) {
430
        return;
431
    }
432

433
    /*
434
     * Now MSI is enabled, clear INTx# interrupts.
435
     * the driver is prohibited from writing enable bit to mask
436
     * a service request. But the guest OS could do this.
437
     * So we just discard the interrupts as moderate fallback.
438
     *
439
     * 6.8.3.3. Enabling Operation
440
     *   While enabled for MSI or MSI-X operation, a function is prohibited
441
     *   from using its INTx# pin (if implemented) to request
442
     *   service (MSI, MSI-X, and INTx# are mutually exclusive).
443
     */
444
    pci_device_deassert_intx(dev);
445

446
    /*
447
     * nr_vectors might be set bigger than capable. So clamp it.
448
     * This is not legal by spec, so we can do anything we like,
449
     * just don't crash the host
450
     */
451
    log_num_vecs =
452
        (flags & PCI_MSI_FLAGS_QSIZE) >> ctz32(PCI_MSI_FLAGS_QSIZE);
453
    log_max_vecs =
454
        (flags & PCI_MSI_FLAGS_QMASK) >> ctz32(PCI_MSI_FLAGS_QMASK);
455
    if (log_num_vecs > log_max_vecs) {
456
        flags &= ~PCI_MSI_FLAGS_QSIZE;
457
        flags |= log_max_vecs << ctz32(PCI_MSI_FLAGS_QSIZE);
458
        pci_set_word(dev->config + msi_flags_off(dev), flags);
459
    }
460

461
    if (!msi_per_vector_mask) {
462
        /* if per vector masking isn't supported,
463
           there is no pending interrupt. */
464
        return;
465
    }
466

467
    nr_vectors = msi_nr_vectors(flags);
468

469
    /* This will discard pending interrupts, if any. */
470
    pending = pci_get_long(dev->config + msi_pending_off(dev, msi64bit));
471
    pending &= 0xffffffff >> (PCI_MSI_VECTORS_MAX - nr_vectors);
472
    pci_set_long(dev->config + msi_pending_off(dev, msi64bit), pending);
473

474
    /* deliver pending interrupts which are unmasked */
475
    for (vector = 0; vector < nr_vectors; ++vector) {
476
        if (msi_is_masked(dev, vector) || !(pending & (1U << vector))) {
477
            continue;
478
        }
479

480
        pci_long_test_and_clear_mask(
481
            dev->config + msi_pending_off(dev, msi64bit), 1U << vector);
482
        msi_notify(dev, vector);
483
    }
484
}
485

486
unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
487
{
488
    uint16_t flags = pci_get_word(dev->config + msi_flags_off(dev));
489
    return msi_nr_vectors(flags);
490
}
491