qemu

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/*
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 * QEMU Simba PCI bridge
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 *
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 * Copyright (c) 2006 Fabrice Bellard
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 * Copyright (c) 2012,2013 Artyom Tarasenko
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 * Copyright (c) 2018 Mark Cave-Ayland
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_bus.h"
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#include "qemu/module.h"
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#include "hw/pci-bridge/simba.h"
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/*
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 * Chipset docs:
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 * APB: "Advanced PCI Bridge (APB) User's Manual",
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 * http://www.sun.com/processors/manuals/805-1251.pdf
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 */
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static void simba_pci_bridge_realize(PCIDevice *dev, Error **errp)
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{
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    /*
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     * command register:
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     * According to PCI bridge spec, after reset
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     *   bus master bit is off
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     *   memory space enable bit is off
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     * According to manual (805-1251.pdf).
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     *   the reset value should be zero unless the boot pin is tied high
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     *   (which is true) and thus it should be PCI_COMMAND_MEMORY.
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     */
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    SimbaPCIBridge *br = SIMBA_PCI_BRIDGE(dev);
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    pci_bridge_initfn(dev, TYPE_PCI_BUS);
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    pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY);
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    pci_set_word(dev->config + PCI_STATUS,
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                 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ |
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                 PCI_STATUS_DEVSEL_MEDIUM);
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    /* Allow 32-bit IO addresses */
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    pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32);
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    pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32);
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    pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff);
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    pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff);
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    pci_bridge_update_mappings(PCI_BRIDGE(br));
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}
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static void simba_pci_bridge_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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    k->realize = simba_pci_bridge_realize;
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    k->exit = pci_bridge_exitfn;
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    k->vendor_id = PCI_VENDOR_ID_SUN;
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    k->device_id = PCI_DEVICE_ID_SUN_SIMBA;
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    k->revision = 0x11;
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    k->config_write = pci_bridge_write_config;
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    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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    dc->reset = pci_bridge_reset;
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    dc->vmsd = &vmstate_pci_device;
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}
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static const TypeInfo simba_pci_bridge_info = {
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    .name          = TYPE_SIMBA_PCI_BRIDGE,
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    .parent        = TYPE_PCI_BRIDGE,
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    .class_init    = simba_pci_bridge_class_init,
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    .instance_size = sizeof(SimbaPCIBridge),
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    .interfaces = (InterfaceInfo[]) {
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        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
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        { },
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    },
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};
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static void simba_register_types(void)
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{
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    type_register_static(&simba_pci_bridge_info);
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}
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type_init(simba_register_types)
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