qemu

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/*
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 * QEMU Generic PCIE-PCI Bridge
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 *
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 * Copyright (c) 2017 Aleksandr Bezzubikov
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 *
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 * This work is licensed under the terms of the GNU GPL, version 2 or later.
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 * See the COPYING file in the top-level directory.
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 */
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/shpc.h"
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#include "hw/pci/slotid_cap.h"
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#include "hw/qdev-properties.h"
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#include "qom/object.h"
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struct PCIEPCIBridge {
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    /*< private >*/
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    PCIBridge parent_obj;
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    OnOffAuto msi;
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    MemoryRegion shpc_bar;
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    /*< public >*/
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};
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#define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge"
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OBJECT_DECLARE_SIMPLE_TYPE(PCIEPCIBridge, PCIE_PCI_BRIDGE_DEV)
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static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp)
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{
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    PCIBridge *br = PCI_BRIDGE(d);
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    PCIEPCIBridge *pcie_br = PCIE_PCI_BRIDGE_DEV(d);
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    int rc, pos;
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    pci_bridge_initfn(d, TYPE_PCI_BUS);
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    d->config[PCI_INTERRUPT_PIN] = 0x1;
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    memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar",
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                       shpc_bar_size(d));
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    rc = shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp);
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    if (rc) {
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        goto error;
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    }
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    rc = pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp);
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    if (rc < 0) {
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        goto cap_error;
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    }
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    pos = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp);
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    if (pos < 0) {
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        goto pm_error;
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    }
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    d->exp.pm_cap = pos;
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    pci_set_word(d->config + pos + PCI_PM_PMC, 0x3);
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    pcie_cap_arifwd_init(d);
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    pcie_cap_deverr_init(d);
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    rc = pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, errp);
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    if (rc < 0) {
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        goto aer_error;
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    }
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    Error *local_err = NULL;
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    if (pcie_br->msi != ON_OFF_AUTO_OFF) {
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        rc = msi_init(d, 0, 1, true, true, &local_err);
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        if (rc < 0) {
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            assert(rc == -ENOTSUP);
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            if (pcie_br->msi != ON_OFF_AUTO_ON) {
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                error_free(local_err);
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            } else {
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                /* failed to satisfy user's explicit request for MSI */
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                error_propagate(errp, local_err);
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                goto msi_error;
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            }
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        }
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    }
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    pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
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                     PCI_BASE_ADDRESS_MEM_TYPE_64, &pcie_br->shpc_bar);
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    return;
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msi_error:
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    pcie_aer_exit(d);
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aer_error:
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pm_error:
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    pcie_cap_exit(d);
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cap_error:
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    shpc_cleanup(d, &pcie_br->shpc_bar);
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error:
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    pci_bridge_exitfn(d);
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}
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static void pcie_pci_bridge_exit(PCIDevice *d)
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{
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    PCIEPCIBridge *bridge_dev = PCIE_PCI_BRIDGE_DEV(d);
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    pcie_cap_exit(d);
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    shpc_cleanup(d, &bridge_dev->shpc_bar);
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    pci_bridge_exitfn(d);
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}
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static void pcie_pci_bridge_reset(DeviceState *qdev)
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{
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    PCIDevice *d = PCI_DEVICE(qdev);
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    pci_bridge_reset(qdev);
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    if (msi_present(d)) {
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        msi_reset(d);
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    }
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    shpc_reset(d);
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}
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static void pcie_pci_bridge_write_config(PCIDevice *d,
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        uint32_t address, uint32_t val, int len)
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{
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    pci_bridge_write_config(d, address, val, len);
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    if (msi_present(d)) {
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        msi_write_config(d, address, val, len);
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    }
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    shpc_cap_write_config(d, address, val, len);
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}
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static Property pcie_pci_bridge_dev_properties[] = {
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        DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_AUTO),
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        DEFINE_PROP_END_OF_LIST(),
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};
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static const VMStateDescription pcie_pci_bridge_dev_vmstate = {
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        .name = TYPE_PCIE_PCI_BRIDGE_DEV,
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        .priority = MIG_PRI_PCI_BUS,
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        .fields = (const VMStateField[]) {
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            VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
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            SHPC_VMSTATE(shpc, PCIDevice, NULL),
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            VMSTATE_END_OF_LIST()
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        }
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};
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static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data)
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{
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    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
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    k->vendor_id = PCI_VENDOR_ID_REDHAT;
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    k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE;
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    k->realize = pcie_pci_bridge_realize;
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    k->exit = pcie_pci_bridge_exit;
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    k->config_write = pcie_pci_bridge_write_config;
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    dc->vmsd = &pcie_pci_bridge_dev_vmstate;
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    device_class_set_props(dc, pcie_pci_bridge_dev_properties);
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    dc->reset = &pcie_pci_bridge_reset;
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    set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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    hc->plug = pci_bridge_dev_plug_cb;
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    hc->unplug = pci_bridge_dev_unplug_cb;
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    hc->unplug_request = pci_bridge_dev_unplug_request_cb;
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}
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static const TypeInfo pcie_pci_bridge_info = {
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        .name = TYPE_PCIE_PCI_BRIDGE_DEV,
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        .parent = TYPE_PCI_BRIDGE,
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        .instance_size = sizeof(PCIEPCIBridge),
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        .class_init = pcie_pci_bridge_class_init,
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        .interfaces = (InterfaceInfo[]) {
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            { TYPE_HOTPLUG_HANDLER },
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            { INTERFACE_PCIE_DEVICE },
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            { },
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        }
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};
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static void pciepci_register(void)
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{
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    type_register_static(&pcie_pci_bridge_info);
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}
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type_init(pciepci_register);
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