qemu

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/*
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 * ioh3420.c
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 * Intel X58 north bridge IOH
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 * PCI Express root port device id 3420
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 *
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 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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 *                    VA Linux Systems Japan K.K.
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 *
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 * This program is free software; you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "qemu/osdep.h"
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#include "hw/pci/pci_ids.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pcie.h"
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#include "hw/pci/pcie_port.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#define PCI_DEVICE_ID_IOH_EPORT         0x3420  /* D0:F0 express mode */
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#define PCI_DEVICE_ID_IOH_REV           0x2
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#define IOH_EP_SSVID_OFFSET             0x40
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#define IOH_EP_SSVID_SVID               PCI_VENDOR_ID_INTEL
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#define IOH_EP_SSVID_SSID               0
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#define IOH_EP_MSI_OFFSET               0x60
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#define IOH_EP_MSI_SUPPORTED_FLAGS      PCI_MSI_FLAGS_MASKBIT
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#define IOH_EP_MSI_NR_VECTOR            2
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#define IOH_EP_EXP_OFFSET               0x90
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#define IOH_EP_AER_OFFSET               0x100
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/*
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 * If two MSI vector are allocated, Advanced Error Interrupt Message Number
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 * is 1. otherwise 0.
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 * 17.12.5.10 RPERRSTS,  32:27 bit Advanced Error Interrupt Message Number.
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 */
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static uint8_t ioh3420_aer_vector(const PCIDevice *d)
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{
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    switch (msi_nr_vectors_allocated(d)) {
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    case 1:
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        return 0;
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    case 2:
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        return 1;
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    case 4:
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    case 8:
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    case 16:
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    case 32:
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    default:
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        break;
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    }
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    abort();
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    return 0;
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}
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static int ioh3420_interrupts_init(PCIDevice *d, Error **errp)
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{
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    int rc;
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    rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
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                  IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
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                  IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
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                  errp);
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    if (rc < 0) {
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        assert(rc == -ENOTSUP);
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    }
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    return rc;
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}
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static void ioh3420_interrupts_uninit(PCIDevice *d)
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{
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    msi_uninit(d);
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}
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static const VMStateDescription vmstate_ioh3420 = {
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    .name = "ioh-3240-express-root-port",
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    .priority = MIG_PRI_PCI_BUS,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .post_load = pcie_cap_slot_post_load,
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    .fields = (const VMStateField[]) {
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        VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
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        VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
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                       PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void ioh3420_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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    PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
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    k->vendor_id = PCI_VENDOR_ID_INTEL;
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    k->device_id = PCI_DEVICE_ID_IOH_EPORT;
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    k->revision = PCI_DEVICE_ID_IOH_REV;
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    dc->desc = "Intel IOH device id 3420 PCIE Root Port";
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    dc->vmsd = &vmstate_ioh3420;
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    rpc->aer_vector = ioh3420_aer_vector;
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    rpc->interrupts_init = ioh3420_interrupts_init;
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    rpc->interrupts_uninit = ioh3420_interrupts_uninit;
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    rpc->exp_offset = IOH_EP_EXP_OFFSET;
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    rpc->aer_offset = IOH_EP_AER_OFFSET;
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    rpc->ssvid_offset = IOH_EP_SSVID_OFFSET;
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    rpc->ssid = IOH_EP_SSVID_SSID;
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}
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static const TypeInfo ioh3420_info = {
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    .name          = "ioh3420",
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    .parent        = TYPE_PCIE_ROOT_PORT,
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    .class_init    = ioh3420_class_init,
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};
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static void ioh3420_register_types(void)
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{
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    type_register_static(&ioh3420_info);
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}
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type_init(ioh3420_register_types)
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