qemu

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/*
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 * CXL 2.0 Root Port Implementation
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 *
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 * Copyright(C) 2020 Intel Corporation.
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/range.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pcie_port.h"
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#include "hw/pci/msi.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "qapi/error.h"
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#include "hw/cxl/cxl.h"
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#define CXL_ROOT_PORT_DID 0x7075
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#define CXL_RP_MSI_OFFSET               0x60
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#define CXL_RP_MSI_SUPPORTED_FLAGS      PCI_MSI_FLAGS_MASKBIT
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#define CXL_RP_MSI_NR_VECTOR            2
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/* Copied from the gen root port which we derive */
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#define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
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#define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
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    (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
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#define CXL_ROOT_PORT_DVSEC_OFFSET \
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    (GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF)
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typedef struct CXLRootPort {
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    /*< private >*/
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    PCIESlot parent_obj;
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    CXLComponentState cxl_cstate;
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    PCIResReserve res_reserve;
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} CXLRootPort;
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#define TYPE_CXL_ROOT_PORT "cxl-rp"
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DECLARE_INSTANCE_CHECKER(CXLRootPort, CXL_ROOT_PORT, TYPE_CXL_ROOT_PORT)
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/*
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 * If two MSI vector are allocated, Advanced Error Interrupt Message Number
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 * is 1. otherwise 0.
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 * 17.12.5.10 RPERRSTS,  32:27 bit Advanced Error Interrupt Message Number.
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 */
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static uint8_t cxl_rp_aer_vector(const PCIDevice *d)
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{
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    switch (msi_nr_vectors_allocated(d)) {
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    case 1:
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        return 0;
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    case 2:
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        return 1;
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    case 4:
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    case 8:
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    case 16:
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    case 32:
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    default:
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        break;
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    }
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    abort();
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    return 0;
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}
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static int cxl_rp_interrupts_init(PCIDevice *d, Error **errp)
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{
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    int rc;
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    rc = msi_init(d, CXL_RP_MSI_OFFSET, CXL_RP_MSI_NR_VECTOR,
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                  CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
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                  CXL_RP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
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                  errp);
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    if (rc < 0) {
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        assert(rc == -ENOTSUP);
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    }
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    return rc;
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}
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static void cxl_rp_interrupts_uninit(PCIDevice *d)
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{
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    msi_uninit(d);
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}
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static void latch_registers(CXLRootPort *crp)
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{
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    uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers;
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    uint32_t *write_msk = crp->cxl_cstate.crb.cache_mem_regs_write_mask;
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    cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT);
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}
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static void build_dvsecs(CXLComponentState *cxl)
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{
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    uint8_t *dvsec;
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    dvsec = (uint8_t *)&(CXLDVSECPortExt){ 0 };
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    cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
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                               EXTENSIONS_PORT_DVSEC_LENGTH,
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                               EXTENSIONS_PORT_DVSEC,
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                               EXTENSIONS_PORT_DVSEC_REVID, dvsec);
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    dvsec = (uint8_t *)&(CXLDVSECPortGPF){
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        .rsvd        = 0,
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        .phase1_ctrl = 1, /* 1μs timeout */
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        .phase2_ctrl = 1, /* 1μs timeout */
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    };
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    cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
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                               GPF_PORT_DVSEC_LENGTH, GPF_PORT_DVSEC,
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                               GPF_PORT_DVSEC_REVID, dvsec);
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    dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
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        .cap                     = 0x26, /* IO, Mem, non-MLD */
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        .ctrl                    = 0x2,
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        .status                  = 0x26, /* same */
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        .rcvd_mod_ts_data_phase1 = 0xef,
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    };
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    cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
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                               PCIE_CXL3_FLEXBUS_PORT_DVSEC_LENGTH,
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                               PCIE_FLEXBUS_PORT_DVSEC,
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                               PCIE_CXL3_FLEXBUS_PORT_DVSEC_REVID, dvsec);
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    dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
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        .rsvd         = 0,
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        .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
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        .reg0_base_hi = 0,
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    };
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    cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
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                               REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
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                               REG_LOC_DVSEC_REVID, dvsec);
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}
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static void cxl_rp_realize(DeviceState *dev, Error **errp)
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{
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    PCIDevice *pci_dev     = PCI_DEVICE(dev);
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    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
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    CXLRootPort *crp       = CXL_ROOT_PORT(dev);
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    CXLComponentState *cxl_cstate = &crp->cxl_cstate;
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    ComponentRegisters *cregs = &cxl_cstate->crb;
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    MemoryRegion *component_bar = &cregs->component_registers;
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    Error *local_err = NULL;
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    rpc->parent_realize(dev, &local_err);
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    if (local_err) {
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        error_propagate(errp, local_err);
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        return;
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    }
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    int rc =
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        pci_bridge_qemu_reserve_cap_init(pci_dev, 0, crp->res_reserve, errp);
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    if (rc < 0) {
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        rpc->parent_class.exit(pci_dev);
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        return;
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    }
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    if (!crp->res_reserve.io || crp->res_reserve.io == -1) {
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        pci_word_test_and_clear_mask(pci_dev->wmask + PCI_COMMAND,
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                                     PCI_COMMAND_IO);
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        pci_dev->wmask[PCI_IO_BASE]  = 0;
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        pci_dev->wmask[PCI_IO_LIMIT] = 0;
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    }
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    cxl_cstate->dvsec_offset = CXL_ROOT_PORT_DVSEC_OFFSET;
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    cxl_cstate->pdev = pci_dev;
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    build_dvsecs(cxl_cstate);
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    cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate,
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                                      TYPE_CXL_ROOT_PORT);
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    pci_register_bar(pci_dev, CXL_COMPONENT_REG_BAR_IDX,
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                     PCI_BASE_ADDRESS_SPACE_MEMORY |
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                         PCI_BASE_ADDRESS_MEM_TYPE_64,
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                     component_bar);
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}
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static void cxl_rp_reset_hold(Object *obj, ResetType type)
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{
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    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(obj);
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    CXLRootPort *crp = CXL_ROOT_PORT(obj);
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    if (rpc->parent_phases.hold) {
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        rpc->parent_phases.hold(obj, type);
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    }
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    latch_registers(crp);
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}
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static Property gen_rp_props[] = {
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    DEFINE_PROP_UINT32("bus-reserve", CXLRootPort, res_reserve.bus, -1),
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    DEFINE_PROP_SIZE("io-reserve", CXLRootPort, res_reserve.io, -1),
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    DEFINE_PROP_SIZE("mem-reserve", CXLRootPort, res_reserve.mem_non_pref, -1),
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    DEFINE_PROP_SIZE("pref32-reserve", CXLRootPort, res_reserve.mem_pref_32,
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                     -1),
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    DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_64,
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                     -1),
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    DEFINE_PROP_END_OF_LIST()
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};
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static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
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                                      uint32_t val, int len)
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{
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    CXLRootPort *crp = CXL_ROOT_PORT(dev);
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    if (range_contains(&crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) {
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        uint8_t *reg = &dev->config[addr];
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        addr -= crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob;
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        if (addr == PORT_CONTROL_OFFSET) {
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            if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) {
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                /* unmask SBR */
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                qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n");
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            }
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            if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) {
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                /* Alt Memory & ID Space Enable */
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                qemu_log_mask(LOG_UNIMP,
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                              "Alt Memory & ID space is not supported\n");
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            }
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        }
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    }
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}
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static void cxl_rp_aer_vector_update(PCIDevice *d)
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{
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    PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
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    if (rpc->aer_vector) {
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        pcie_aer_root_set_vector(d, rpc->aer_vector(d));
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    }
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}
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static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t val,
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                                int len)
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{
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    uint16_t slt_ctl, slt_sta;
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    uint32_t root_cmd =
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        pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
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    pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
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    pci_bridge_write_config(d, address, val, len);
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    cxl_rp_aer_vector_update(d);
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    pcie_cap_flr_write_config(d, address, val, len);
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    pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
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    pcie_aer_write_config(d, address, val, len);
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    pcie_aer_root_write_config(d, address, val, len, root_cmd);
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    cxl_rp_dvsec_write_config(d, address, val, len);
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}
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static void cxl_root_port_class_init(ObjectClass *oc, void *data)
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{
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    DeviceClass *dc        = DEVICE_CLASS(oc);
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    PCIDeviceClass *k      = PCI_DEVICE_CLASS(oc);
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    ResettableClass *rc    = RESETTABLE_CLASS(oc);
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    PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc);
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    k->vendor_id = PCI_VENDOR_ID_INTEL;
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    k->device_id = CXL_ROOT_PORT_DID;
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    dc->desc     = "CXL Root Port";
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    k->revision  = 0;
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    device_class_set_props(dc, gen_rp_props);
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    k->config_write = cxl_rp_write_config;
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    device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize);
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    resettable_class_set_parent_phases(rc, NULL, cxl_rp_reset_hold, NULL,
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                                       &rpc->parent_phases);
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    rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
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    rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
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    rpc->aer_vector = cxl_rp_aer_vector;
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    rpc->interrupts_init = cxl_rp_interrupts_init;
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    rpc->interrupts_uninit = cxl_rp_interrupts_uninit;
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    dc->hotpluggable = false;
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}
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static const TypeInfo cxl_root_port_info = {
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    .name = TYPE_CXL_ROOT_PORT,
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    .parent = TYPE_PCIE_ROOT_PORT,
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    .instance_size = sizeof(CXLRootPort),
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    .class_init = cxl_root_port_class_init,
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    .interfaces = (InterfaceInfo[]) {
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        { INTERFACE_CXL_DEVICE },
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        { }
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    },
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};
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static void cxl_register(void)
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{
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    type_register_static(&cxl_root_port_info);
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}
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type_init(cxl_register);
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