qemu

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/*
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 * QEMU model of the EFuse_Cache
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 *
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 * Copyright (c) 2017 Xilinx Inc.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/nvram/xlnx-versal-efuse.h"
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#include "qemu/log.h"
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#include "hw/qdev-properties.h"
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#define MR_SIZE 0xC00
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static uint64_t efuse_cache_read(void *opaque, hwaddr addr, unsigned size)
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{
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    XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(opaque);
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    unsigned int w0 = QEMU_ALIGN_DOWN(addr * 8, 32);
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    unsigned int w1 = QEMU_ALIGN_DOWN((addr + size - 1) * 8, 32);
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    uint64_t ret;
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    assert(w0 == w1 || (w0 + 32) == w1);
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    ret = xlnx_versal_efuse_read_row(s->efuse, w1, NULL);
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    if (w0 < w1) {
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        ret <<= 32;
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        ret |= xlnx_versal_efuse_read_row(s->efuse, w0, NULL);
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    }
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    /* If 'addr' unaligned, the guest is always assumed to be little-endian. */
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    addr &= 3;
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    if (addr) {
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        ret >>= 8 * addr;
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    }
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    return ret;
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}
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static void efuse_cache_write(void *opaque, hwaddr addr, uint64_t value,
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                              unsigned size)
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{
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    /* No Register Writes allowed */
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    qemu_log_mask(LOG_GUEST_ERROR, "%s: efuse cache registers are read-only",
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                  __func__);
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}
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static const MemoryRegionOps efuse_cache_ops = {
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    .read = efuse_cache_read,
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    .write = efuse_cache_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 4,
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    },
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};
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static void efuse_cache_init(Object *obj)
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{
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    XlnxVersalEFuseCache *s = XLNX_VERSAL_EFUSE_CACHE(obj);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    memory_region_init_io(&s->iomem, obj, &efuse_cache_ops, s,
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                          TYPE_XLNX_VERSAL_EFUSE_CACHE, MR_SIZE);
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    sysbus_init_mmio(sbd, &s->iomem);
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}
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static Property efuse_cache_props[] = {
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    DEFINE_PROP_LINK("efuse",
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                     XlnxVersalEFuseCache, efuse,
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                     TYPE_XLNX_EFUSE, XlnxEFuse *),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void efuse_cache_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    device_class_set_props(dc, efuse_cache_props);
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}
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static const TypeInfo efuse_cache_info = {
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    .name          = TYPE_XLNX_VERSAL_EFUSE_CACHE,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(XlnxVersalEFuseCache),
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    .class_init    = efuse_cache_class_init,
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    .instance_init = efuse_cache_init,
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};
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static void efuse_cache_register_types(void)
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{
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    type_register_static(&efuse_cache_info);
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}
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type_init(efuse_cache_register_types)
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