qemu

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/*
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 * QEMU model of the ZynqMP APU Control.
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 *
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 * Copyright (c) 2013-2022 Xilinx Inc
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 *
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 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
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 * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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 */
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "migration/vmstate.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/register.h"
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#include "qemu/bitops.h"
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#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
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#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG
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#define XILINX_ZYNQMP_APU_ERR_DEBUG 0
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#endif
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static void update_wfi_out(void *opaque)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
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    unsigned int i, wfi_pending;
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    wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi;
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    for (i = 0; i < APU_MAX_CPU; i++) {
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        qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i)));
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    }
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}
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static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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    int i;
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    for (i = 0; i < APU_MAX_CPU; ++i) {
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        uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] +
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                         ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32);
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        if (s->cpus[i]) {
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            object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar,
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                                    &error_abort);
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        }
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    }
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}
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static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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    unsigned int i, new;
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    for (i = 0; i < APU_MAX_CPU; i++) {
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        new = val & (1 << i);
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        /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */
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        if (new != (s->cpu_pwrdwn_req & (1 << i))) {
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            qemu_set_irq(s->cpu_power_status[i], !!new);
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        }
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        s->cpu_pwrdwn_req &= ~(1 << i);
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        s->cpu_pwrdwn_req |= new;
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    }
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    update_wfi_out(s);
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}
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static void imr_update_irq(XlnxZynqMPAPUCtrl *s)
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{
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    bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
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    qemu_set_irq(s->irq_imr, pending);
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}
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static void isr_postw(RegisterInfo *reg, uint64_t val64)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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    imr_update_irq(s);
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}
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static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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    uint32_t val = val64;
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    s->regs[R_IMR] &= ~val;
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    imr_update_irq(s);
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    return 0;
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}
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static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
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    uint32_t val = val64;
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    s->regs[R_IMR] |= val;
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    imr_update_irq(s);
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    return 0;
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}
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static const RegisterAccessInfo zynqmp_apu_regs_info[] = {
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#define RVBAR_REGDEF(n) \
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    {   .name = "RVBAR CPU " #n " Low",  .addr = A_RVBARADDR ## n ## L,    \
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            .reset = 0xffff0000ul,                                         \
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            .post_write = zynqmp_apu_rvbar_post_write,                     \
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    },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H,    \
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            .post_write = zynqmp_apu_rvbar_post_write,                     \
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    }
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    {   .name = "ERR_CTRL",  .addr = A_APU_ERR_CTRL,
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    },{ .name = "ISR",  .addr = A_ISR,
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        .w1c = 0x1,
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        .post_write = isr_postw,
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    },{ .name = "IMR",  .addr = A_IMR,
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        .reset = 0x1,
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        .ro = 0x1,
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    },{ .name = "IEN",  .addr = A_IEN,
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        .pre_write = ien_prew,
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    },{ .name = "IDS",  .addr = A_IDS,
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        .pre_write = ids_prew,
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    },{ .name = "CONFIG_0",  .addr = A_CONFIG_0,
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        .reset = 0xf0f,
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    },{ .name = "CONFIG_1",  .addr = A_CONFIG_1,
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    },
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    RVBAR_REGDEF(0),
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    RVBAR_REGDEF(1),
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    RVBAR_REGDEF(2),
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    RVBAR_REGDEF(3),
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    { .name = "ACE_CTRL",  .addr = A_ACE_CTRL,
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        .reset = 0xf000f,
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    },{ .name = "SNOOP_CTRL",  .addr = A_SNOOP_CTRL,
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    },{ .name = "PWRCTL",  .addr = A_PWRCTL,
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        .post_write = zynqmp_apu_pwrctl_post_write,
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    },{ .name = "PWRSTAT",  .addr = A_PWRSTAT,
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        .ro = 0x3000f,
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    }
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};
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static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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    int i;
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    for (i = 0; i < APU_R_MAX; ++i) {
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        register_reset(&s->regs_info[i]);
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    }
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    s->cpu_pwrdwn_req = 0;
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    s->cpu_in_wfi = 0;
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}
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static void zynqmp_apu_reset_hold(Object *obj, ResetType type)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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    update_wfi_out(s);
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    imr_update_irq(s);
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}
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static const MemoryRegionOps zynqmp_apu_ops = {
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    .read = register_read_memory,
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    .write = register_write_memory,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    }
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};
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static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
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    s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level);
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    update_wfi_out(s);
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}
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static void zynqmp_apu_init(Object *obj)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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    int i;
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    s->reg_array =
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        register_init_block32(DEVICE(obj), zynqmp_apu_regs_info,
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                              ARRAY_SIZE(zynqmp_apu_regs_info),
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                              s->regs_info, s->regs,
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                              &zynqmp_apu_ops,
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                              XILINX_ZYNQMP_APU_ERR_DEBUG,
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                              APU_R_MAX * 4);
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    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem);
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    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);
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    for (i = 0; i < APU_MAX_CPU; ++i) {
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        g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i);
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        object_property_add_link(obj, prop_name, TYPE_ARM_CPU,
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                                 (Object **)&s->cpus[i],
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                                 qdev_prop_allow_set_link_before_realize,
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                                 OBJ_PROP_LINK_STRONG);
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    }
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    /* wfi_out is used to connect to PMU GPIs. */
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    qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
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    /* CPU_POWER_STATUS is used to connect to INTC redirect. */
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    qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
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                             "CPU_POWER_STATUS", 4);
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    /* wfi_in is used as input from CPUs as wfi request. */
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    qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4);
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}
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static void zynqmp_apu_finalize(Object *obj)
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{
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    XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
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    register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_zynqmp_apu = {
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    .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX),
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        VMSTATE_END_OF_LIST(),
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    }
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};
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static void zynqmp_apu_class_init(ObjectClass *klass, void *data)
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{
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    ResettableClass *rc = RESETTABLE_CLASS(klass);
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->vmsd = &vmstate_zynqmp_apu;
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    rc->phases.enter = zynqmp_apu_reset_enter;
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    rc->phases.hold = zynqmp_apu_reset_hold;
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}
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static const TypeInfo zynqmp_apu_info = {
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    .name              = TYPE_XLNX_ZYNQMP_APU_CTRL,
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    .parent            = TYPE_SYS_BUS_DEVICE,
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    .instance_size     = sizeof(XlnxZynqMPAPUCtrl),
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    .class_init        = zynqmp_apu_class_init,
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    .instance_init     = zynqmp_apu_init,
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    .instance_finalize = zynqmp_apu_finalize,
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};
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static void zynqmp_apu_register_types(void)
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{
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    type_register_static(&zynqmp_apu_info);
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}
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type_init(zynqmp_apu_register_types)
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