qemu

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/*
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 * QEMU model of the Xilinx XRAM Controller.
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 *
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 * Copyright (c) 2021 Xilinx Inc.
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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 */
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "hw/qdev-properties.h"
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#include "hw/irq.h"
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#include "hw/misc/xlnx-versal-xramc.h"
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#ifndef XLNX_XRAM_CTRL_ERR_DEBUG
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#define XLNX_XRAM_CTRL_ERR_DEBUG 0
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#endif
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static void xram_update_irq(XlnxXramCtrl *s)
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{
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    bool pending = s->regs[R_XRAM_ISR] & ~s->regs[R_XRAM_IMR];
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    qemu_set_irq(s->irq, pending);
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}
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static void xram_isr_postw(RegisterInfo *reg, uint64_t val64)
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{
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    XlnxXramCtrl *s = XLNX_XRAM_CTRL(reg->opaque);
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    xram_update_irq(s);
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}
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static uint64_t xram_ien_prew(RegisterInfo *reg, uint64_t val64)
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{
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    XlnxXramCtrl *s = XLNX_XRAM_CTRL(reg->opaque);
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    uint32_t val = val64;
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    s->regs[R_XRAM_IMR] &= ~val;
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    xram_update_irq(s);
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    return 0;
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}
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static uint64_t xram_ids_prew(RegisterInfo *reg, uint64_t val64)
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{
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    XlnxXramCtrl *s = XLNX_XRAM_CTRL(reg->opaque);
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    uint32_t val = val64;
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    s->regs[R_XRAM_IMR] |= val;
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    xram_update_irq(s);
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    return 0;
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}
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static const RegisterAccessInfo xram_ctrl_regs_info[] = {
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    {   .name = "XRAM_ERR_CTRL",  .addr = A_XRAM_ERR_CTRL,
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        .reset = 0xf,
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        .rsvd = 0xfffffff0,
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    },{ .name = "XRAM_ISR",  .addr = A_XRAM_ISR,
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        .rsvd = 0xfffff800,
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        .w1c = 0x7ff,
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        .post_write = xram_isr_postw,
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    },{ .name = "XRAM_IMR",  .addr = A_XRAM_IMR,
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        .reset = 0x7ff,
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        .rsvd = 0xfffff800,
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        .ro = 0x7ff,
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    },{ .name = "XRAM_IEN",  .addr = A_XRAM_IEN,
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        .rsvd = 0xfffff800,
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        .pre_write = xram_ien_prew,
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    },{ .name = "XRAM_IDS",  .addr = A_XRAM_IDS,
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        .rsvd = 0xfffff800,
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        .pre_write = xram_ids_prew,
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    },{ .name = "XRAM_ECC_CNTL",  .addr = A_XRAM_ECC_CNTL,
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        .rsvd = 0xfffffff8,
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    },{ .name = "XRAM_CLR_EXE",  .addr = A_XRAM_CLR_EXE,
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        .rsvd = 0xffffff00,
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    },{ .name = "XRAM_CE_FFA",  .addr = A_XRAM_CE_FFA,
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        .rsvd = 0xfff00000,
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        .ro = 0xfffff,
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    },{ .name = "XRAM_CE_FFD0",  .addr = A_XRAM_CE_FFD0,
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        .ro = 0xffffffff,
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    },{ .name = "XRAM_CE_FFD1",  .addr = A_XRAM_CE_FFD1,
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        .ro = 0xffffffff,
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    },{ .name = "XRAM_CE_FFD2",  .addr = A_XRAM_CE_FFD2,
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        .ro = 0xffffffff,
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    },{ .name = "XRAM_CE_FFD3",  .addr = A_XRAM_CE_FFD3,
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        .ro = 0xffffffff,
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    },{ .name = "XRAM_CE_FFE",  .addr = A_XRAM_CE_FFE,
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        .rsvd = 0xffff0000,
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        .ro = 0xffff,
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    },{ .name = "XRAM_UE_FFA",  .addr = A_XRAM_UE_FFA,
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        .rsvd = 0xfff00000,
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        .ro = 0xfffff,
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    },{ .name = "XRAM_UE_FFD0",  .addr = A_XRAM_UE_FFD0,
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        .ro = 0xffffffff,
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    },{ .name = "XRAM_UE_FFD1",  .addr = A_XRAM_UE_FFD1,
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        .ro = 0xffffffff,
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    },{ .name = "XRAM_UE_FFD2",  .addr = A_XRAM_UE_FFD2,
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        .ro = 0xffffffff,
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    },{ .name = "XRAM_UE_FFD3",  .addr = A_XRAM_UE_FFD3,
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        .ro = 0xffffffff,
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    },{ .name = "XRAM_UE_FFE",  .addr = A_XRAM_UE_FFE,
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        .rsvd = 0xffff0000,
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        .ro = 0xffff,
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    },{ .name = "XRAM_FI_D0",  .addr = A_XRAM_FI_D0,
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    },{ .name = "XRAM_FI_D1",  .addr = A_XRAM_FI_D1,
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    },{ .name = "XRAM_FI_D2",  .addr = A_XRAM_FI_D2,
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    },{ .name = "XRAM_FI_D3",  .addr = A_XRAM_FI_D3,
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    },{ .name = "XRAM_FI_SY",  .addr = A_XRAM_FI_SY,
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        .rsvd = 0xffff0000,
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    },{ .name = "XRAM_RMW_UE_FFA",  .addr = A_XRAM_RMW_UE_FFA,
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        .rsvd = 0xfff00000,
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        .ro = 0xfffff,
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    },{ .name = "XRAM_FI_CNTR",  .addr = A_XRAM_FI_CNTR,
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        .rsvd = 0xff000000,
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    },{ .name = "XRAM_IMP",  .addr = A_XRAM_IMP,
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        .reset = 0x4,
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        .rsvd = 0xfffffff0,
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        .ro = 0xf,
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    },{ .name = "XRAM_PRDY_DBG",  .addr = A_XRAM_PRDY_DBG,
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        .reset = 0xffff,
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        .rsvd = 0xffff0000,
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        .ro = 0xffff,
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    },{ .name = "XRAM_SAFETY_CHK",  .addr = A_XRAM_SAFETY_CHK,
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    }
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};
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static void xram_ctrl_reset_enter(Object *obj, ResetType type)
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{
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    XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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    unsigned int i;
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    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
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        register_reset(&s->regs_info[i]);
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    }
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    ARRAY_FIELD_DP32(s->regs, XRAM_IMP, SIZE, s->cfg.encoded_size);
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}
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static void xram_ctrl_reset_hold(Object *obj, ResetType type)
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{
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    XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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    xram_update_irq(s);
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}
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static const MemoryRegionOps xram_ctrl_ops = {
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    .read = register_read_memory,
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    .write = register_write_memory,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    },
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};
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static void xram_ctrl_realize(DeviceState *dev, Error **errp)
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{
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    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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    XlnxXramCtrl *s = XLNX_XRAM_CTRL(dev);
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    switch (s->cfg.size) {
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    case 64 * KiB:
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        s->cfg.encoded_size = 0;
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        break;
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    case 128 * KiB:
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        s->cfg.encoded_size = 1;
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        break;
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    case 256 * KiB:
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        s->cfg.encoded_size = 2;
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        break;
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    case 512 * KiB:
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        s->cfg.encoded_size = 3;
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        break;
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    case 1 * MiB:
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        s->cfg.encoded_size = 4;
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        break;
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    default:
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        error_setg(errp, "Unsupported XRAM size %" PRId64, s->cfg.size);
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        return;
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    }
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    memory_region_init_ram(&s->ram, OBJECT(s),
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                           object_get_canonical_path_component(OBJECT(s)),
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                           s->cfg.size, &error_fatal);
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    sysbus_init_mmio(sbd, &s->ram);
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}
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static void xram_ctrl_init(Object *obj)
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{
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    XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    s->reg_array =
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        register_init_block32(DEVICE(obj), xram_ctrl_regs_info,
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                              ARRAY_SIZE(xram_ctrl_regs_info),
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                              s->regs_info, s->regs,
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                              &xram_ctrl_ops,
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                              XLNX_XRAM_CTRL_ERR_DEBUG,
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                              XRAM_CTRL_R_MAX * 4);
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    sysbus_init_mmio(sbd, &s->reg_array->mem);
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    sysbus_init_irq(sbd, &s->irq);
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}
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static void xram_ctrl_finalize(Object *obj)
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{
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    XlnxXramCtrl *s = XLNX_XRAM_CTRL(obj);
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    register_finalize_block(s->reg_array);
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}
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static const VMStateDescription vmstate_xram_ctrl = {
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    .name = TYPE_XLNX_XRAM_CTRL,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32_ARRAY(regs, XlnxXramCtrl, XRAM_CTRL_R_MAX),
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        VMSTATE_END_OF_LIST(),
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    }
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};
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static Property xram_ctrl_properties[] = {
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    DEFINE_PROP_UINT64("size", XlnxXramCtrl, cfg.size, 1 * MiB),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void xram_ctrl_class_init(ObjectClass *klass, void *data)
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{
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    ResettableClass *rc = RESETTABLE_CLASS(klass);
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->realize = xram_ctrl_realize;
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    dc->vmsd = &vmstate_xram_ctrl;
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    device_class_set_props(dc, xram_ctrl_properties);
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    rc->phases.enter = xram_ctrl_reset_enter;
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    rc->phases.hold = xram_ctrl_reset_hold;
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}
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static const TypeInfo xram_ctrl_info = {
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    .name              = TYPE_XLNX_XRAM_CTRL,
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    .parent            = TYPE_SYS_BUS_DEVICE,
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    .instance_size     = sizeof(XlnxXramCtrl),
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    .class_init        = xram_ctrl_class_init,
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    .instance_init     = xram_ctrl_init,
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    .instance_finalize = xram_ctrl_finalize,
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};
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static void xram_ctrl_register_types(void)
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{
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    type_register_static(&xram_ctrl_info);
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}
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type_init(xram_ctrl_register_types)
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