qemu

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/*
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 * STM32F4xx SYSCFG
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 *
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 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/misc/stm32f4xx_syscfg.h"
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static void stm32f4xx_syscfg_reset(DeviceState *dev)
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{
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    STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(dev);
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    s->syscfg_memrmp = 0x00000000;
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    s->syscfg_pmc = 0x00000000;
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    s->syscfg_exticr[0] = 0x00000000;
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    s->syscfg_exticr[1] = 0x00000000;
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    s->syscfg_exticr[2] = 0x00000000;
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    s->syscfg_exticr[3] = 0x00000000;
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    s->syscfg_cmpcr = 0x00000000;
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}
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static void stm32f4xx_syscfg_set_irq(void *opaque, int irq, int level)
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{
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    STM32F4xxSyscfgState *s = opaque;
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    int icrreg = irq / 4;
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    int startbit = (irq & 3) * 4;
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    uint8_t config = irq / 16;
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    trace_stm32f4xx_syscfg_set_irq(irq / 16, irq % 16, level);
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    g_assert(icrreg < SYSCFG_NUM_EXTICR);
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    if (extract32(s->syscfg_exticr[icrreg], startbit, 4) == config) {
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        qemu_set_irq(s->gpio_out[irq], level);
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        trace_stm32f4xx_pulse_exti(irq);
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   }
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}
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static uint64_t stm32f4xx_syscfg_read(void *opaque, hwaddr addr,
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                                     unsigned int size)
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{
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    STM32F4xxSyscfgState *s = opaque;
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    trace_stm32f4xx_syscfg_read(addr);
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    switch (addr) {
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    case SYSCFG_MEMRMP:
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        return s->syscfg_memrmp;
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    case SYSCFG_PMC:
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        return s->syscfg_pmc;
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    case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
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        return s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4];
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    case SYSCFG_CMPCR:
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        return s->syscfg_cmpcr;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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        return 0;
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    }
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}
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static void stm32f4xx_syscfg_write(void *opaque, hwaddr addr,
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                       uint64_t val64, unsigned int size)
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{
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    STM32F4xxSyscfgState *s = opaque;
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    uint32_t value = val64;
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    trace_stm32f4xx_syscfg_write(value, addr);
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    switch (addr) {
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    case SYSCFG_MEMRMP:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: Changing the memory mapping isn't supported " \
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                      "in QEMU\n", __func__);
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        return;
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    case SYSCFG_PMC:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: Changing the memory mapping isn't supported " \
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                      "in QEMU\n", __func__);
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        return;
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    case SYSCFG_EXTICR1...SYSCFG_EXTICR4:
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        s->syscfg_exticr[addr / 4 - SYSCFG_EXTICR1 / 4] = (value & 0xFFFF);
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        return;
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    case SYSCFG_CMPCR:
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        s->syscfg_cmpcr = value;
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        return;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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    }
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}
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static const MemoryRegionOps stm32f4xx_syscfg_ops = {
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    .read = stm32f4xx_syscfg_read,
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    .write = stm32f4xx_syscfg_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void stm32f4xx_syscfg_init(Object *obj)
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{
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    STM32F4xxSyscfgState *s = STM32F4XX_SYSCFG(obj);
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    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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    memory_region_init_io(&s->mmio, obj, &stm32f4xx_syscfg_ops, s,
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                          TYPE_STM32F4XX_SYSCFG, 0x400);
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    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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    qdev_init_gpio_in(DEVICE(obj), stm32f4xx_syscfg_set_irq, 16 * 9);
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    qdev_init_gpio_out(DEVICE(obj), s->gpio_out, 16);
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}
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static const VMStateDescription vmstate_stm32f4xx_syscfg = {
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    .name = TYPE_STM32F4XX_SYSCFG,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(syscfg_memrmp, STM32F4xxSyscfgState),
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        VMSTATE_UINT32(syscfg_pmc, STM32F4xxSyscfgState),
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        VMSTATE_UINT32_ARRAY(syscfg_exticr, STM32F4xxSyscfgState,
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                             SYSCFG_NUM_EXTICR),
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        VMSTATE_UINT32(syscfg_cmpcr, STM32F4xxSyscfgState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void stm32f4xx_syscfg_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->reset = stm32f4xx_syscfg_reset;
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    dc->vmsd = &vmstate_stm32f4xx_syscfg;
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}
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static const TypeInfo stm32f4xx_syscfg_info = {
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    .name          = TYPE_STM32F4XX_SYSCFG,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(STM32F4xxSyscfgState),
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    .instance_init = stm32f4xx_syscfg_init,
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    .class_init    = stm32f4xx_syscfg_class_init,
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};
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static void stm32f4xx_syscfg_register_types(void)
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{
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    type_register_static(&stm32f4xx_syscfg_info);
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}
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type_init(stm32f4xx_syscfg_register_types)
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