qemu

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/*
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 * STM32F4XX EXTI
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 *
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 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "hw/misc/stm32f4xx_exti.h"
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static void stm32f4xx_exti_reset(DeviceState *dev)
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{
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    STM32F4xxExtiState *s = STM32F4XX_EXTI(dev);
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    s->exti_imr = 0x00000000;
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    s->exti_emr = 0x00000000;
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    s->exti_rtsr = 0x00000000;
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    s->exti_ftsr = 0x00000000;
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    s->exti_swier = 0x00000000;
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    s->exti_pr = 0x00000000;
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}
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static void stm32f4xx_exti_set_irq(void *opaque, int irq, int level)
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{
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    STM32F4xxExtiState *s = opaque;
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    trace_stm32f4xx_exti_set_irq(irq, level);
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    if (((1 << irq) & s->exti_rtsr) && level) {
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        /* Rising Edge */
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        s->exti_pr |= 1 << irq;
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    }
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    if (((1 << irq) & s->exti_ftsr) && !level) {
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        /* Falling Edge */
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        s->exti_pr |= 1 << irq;
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    }
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    if (!((1 << irq) & s->exti_imr)) {
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        /* Interrupt is masked */
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        return;
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    }
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    qemu_irq_pulse(s->irq[irq]);
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}
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static uint64_t stm32f4xx_exti_read(void *opaque, hwaddr addr,
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                                     unsigned int size)
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{
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    STM32F4xxExtiState *s = opaque;
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    trace_stm32f4xx_exti_read(addr);
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    switch (addr) {
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    case EXTI_IMR:
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        return s->exti_imr;
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    case EXTI_EMR:
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        return s->exti_emr;
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    case EXTI_RTSR:
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        return s->exti_rtsr;
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    case EXTI_FTSR:
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        return s->exti_ftsr;
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    case EXTI_SWIER:
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        return s->exti_swier;
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    case EXTI_PR:
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        return s->exti_pr;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "STM32F4XX_exti_read: Bad offset %x\n", (int)addr);
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        return 0;
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    }
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    return 0;
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}
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static void stm32f4xx_exti_write(void *opaque, hwaddr addr,
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                       uint64_t val64, unsigned int size)
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{
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    STM32F4xxExtiState *s = opaque;
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    uint32_t value = (uint32_t) val64;
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    trace_stm32f4xx_exti_write(addr, value);
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    switch (addr) {
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    case EXTI_IMR:
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        s->exti_imr = value;
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        return;
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    case EXTI_EMR:
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        s->exti_emr = value;
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        return;
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    case EXTI_RTSR:
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        s->exti_rtsr = value;
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        return;
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    case EXTI_FTSR:
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        s->exti_ftsr = value;
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        return;
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    case EXTI_SWIER:
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        s->exti_swier = value;
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        return;
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    case EXTI_PR:
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        /* This bit is cleared by writing a 1 to it */
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        s->exti_pr &= ~value;
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        return;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "STM32F4XX_exti_write: Bad offset %x\n", (int)addr);
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    }
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}
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static const MemoryRegionOps stm32f4xx_exti_ops = {
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    .read = stm32f4xx_exti_read,
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    .write = stm32f4xx_exti_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void stm32f4xx_exti_init(Object *obj)
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{
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    STM32F4xxExtiState *s = STM32F4XX_EXTI(obj);
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    int i;
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    for (i = 0; i < NUM_INTERRUPT_OUT_LINES; i++) {
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        sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
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    }
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    memory_region_init_io(&s->mmio, obj, &stm32f4xx_exti_ops, s,
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                          TYPE_STM32F4XX_EXTI, 0x400);
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    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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    qdev_init_gpio_in(DEVICE(obj), stm32f4xx_exti_set_irq,
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                      NUM_GPIO_EVENT_IN_LINES);
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}
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static const VMStateDescription vmstate_stm32f4xx_exti = {
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    .name = TYPE_STM32F4XX_EXTI,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(exti_imr, STM32F4xxExtiState),
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        VMSTATE_UINT32(exti_emr, STM32F4xxExtiState),
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        VMSTATE_UINT32(exti_rtsr, STM32F4xxExtiState),
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        VMSTATE_UINT32(exti_ftsr, STM32F4xxExtiState),
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        VMSTATE_UINT32(exti_swier, STM32F4xxExtiState),
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        VMSTATE_UINT32(exti_pr, STM32F4xxExtiState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void stm32f4xx_exti_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->reset = stm32f4xx_exti_reset;
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    dc->vmsd = &vmstate_stm32f4xx_exti;
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}
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static const TypeInfo stm32f4xx_exti_info = {
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    .name          = TYPE_STM32F4XX_EXTI,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(STM32F4xxExtiState),
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    .instance_init = stm32f4xx_exti_init,
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    .class_init    = stm32f4xx_exti_class_init,
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};
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static void stm32f4xx_exti_register_types(void)
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{
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    type_register_static(&stm32f4xx_exti_info);
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}
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type_init(stm32f4xx_exti_register_types)
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