qemu

1
/*
2
 * STM32F2XX SYSCFG
3
 *
4
 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24

25
#include "qemu/osdep.h"
26
#include "hw/misc/stm32f2xx_syscfg.h"
27
#include "qemu/log.h"
28
#include "qemu/module.h"
29

30
#ifndef STM_SYSCFG_ERR_DEBUG
31
#define STM_SYSCFG_ERR_DEBUG 0
32
#endif
33

34
#define DB_PRINT_L(lvl, fmt, args...) do { \
35
    if (STM_SYSCFG_ERR_DEBUG >= lvl) { \
36
        qemu_log("%s: " fmt, __func__, ## args); \
37
    } \
38
} while (0)
39

40
#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
41

42
static void stm32f2xx_syscfg_reset(DeviceState *dev)
43
{
44
    STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(dev);
45

46
    s->syscfg_memrmp = 0x00000000;
47
    s->syscfg_pmc = 0x00000000;
48
    s->syscfg_exticr1 = 0x00000000;
49
    s->syscfg_exticr2 = 0x00000000;
50
    s->syscfg_exticr3 = 0x00000000;
51
    s->syscfg_exticr4 = 0x00000000;
52
    s->syscfg_cmpcr = 0x00000000;
53
}
54

55
static uint64_t stm32f2xx_syscfg_read(void *opaque, hwaddr addr,
56
                                     unsigned int size)
57
{
58
    STM32F2XXSyscfgState *s = opaque;
59

60
    DB_PRINT("0x%"HWADDR_PRIx"\n", addr);
61

62
    switch (addr) {
63
    case SYSCFG_MEMRMP:
64
        return s->syscfg_memrmp;
65
    case SYSCFG_PMC:
66
        return s->syscfg_pmc;
67
    case SYSCFG_EXTICR1:
68
        return s->syscfg_exticr1;
69
    case SYSCFG_EXTICR2:
70
        return s->syscfg_exticr2;
71
    case SYSCFG_EXTICR3:
72
        return s->syscfg_exticr3;
73
    case SYSCFG_EXTICR4:
74
        return s->syscfg_exticr4;
75
    case SYSCFG_CMPCR:
76
        return s->syscfg_cmpcr;
77
    default:
78
        qemu_log_mask(LOG_GUEST_ERROR,
79
                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
80
        return 0;
81
    }
82

83
    return 0;
84
}
85

86
static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
87
                       uint64_t val64, unsigned int size)
88
{
89
    STM32F2XXSyscfgState *s = opaque;
90
    uint32_t value = val64;
91

92
    DB_PRINT("0x%x, 0x%"HWADDR_PRIx"\n", value, addr);
93

94
    switch (addr) {
95
    case SYSCFG_MEMRMP:
96
        qemu_log_mask(LOG_UNIMP,
97
                      "%s: Changing the memory mapping isn't supported " \
98
                      "in QEMU\n", __func__);
99
        return;
100
    case SYSCFG_PMC:
101
        qemu_log_mask(LOG_UNIMP,
102
                      "%s: Changing the memory mapping isn't supported " \
103
                      "in QEMU\n", __func__);
104
        return;
105
    case SYSCFG_EXTICR1:
106
        s->syscfg_exticr1 = (value & 0xFFFF);
107
        return;
108
    case SYSCFG_EXTICR2:
109
        s->syscfg_exticr2 = (value & 0xFFFF);
110
        return;
111
    case SYSCFG_EXTICR3:
112
        s->syscfg_exticr3 = (value & 0xFFFF);
113
        return;
114
    case SYSCFG_EXTICR4:
115
        s->syscfg_exticr4 = (value & 0xFFFF);
116
        return;
117
    case SYSCFG_CMPCR:
118
        s->syscfg_cmpcr = value;
119
        return;
120
    default:
121
        qemu_log_mask(LOG_GUEST_ERROR,
122
                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
123
    }
124
}
125

126
static const MemoryRegionOps stm32f2xx_syscfg_ops = {
127
    .read = stm32f2xx_syscfg_read,
128
    .write = stm32f2xx_syscfg_write,
129
    .endianness = DEVICE_NATIVE_ENDIAN,
130
};
131

132
static void stm32f2xx_syscfg_init(Object *obj)
133
{
134
    STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
135

136
    memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
137
                          TYPE_STM32F2XX_SYSCFG, 0x400);
138
    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
139
}
140

141
static void stm32f2xx_syscfg_class_init(ObjectClass *klass, void *data)
142
{
143
    DeviceClass *dc = DEVICE_CLASS(klass);
144

145
    dc->reset = stm32f2xx_syscfg_reset;
146
}
147

148
static const TypeInfo stm32f2xx_syscfg_info = {
149
    .name          = TYPE_STM32F2XX_SYSCFG,
150
    .parent        = TYPE_SYS_BUS_DEVICE,
151
    .instance_size = sizeof(STM32F2XXSyscfgState),
152
    .instance_init = stm32f2xx_syscfg_init,
153
    .class_init    = stm32f2xx_syscfg_class_init,
154
};
155

156
static void stm32f2xx_syscfg_register_types(void)
157
{
158
    type_register_static(&stm32f2xx_syscfg_info);
159
}
160

161
type_init(stm32f2xx_syscfg_register_types)
162