qemu

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/*
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 * QEMU Sparc SLAVIO aux io port emulation
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 *
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 * Copyright (c) 2005 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "sysemu/runstate.h"
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#include "trace.h"
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#include "qom/object.h"
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/*
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 * This is the auxio port, chip control and system control part of
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 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
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 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
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 *
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 * This also includes the PMC CPU idle controller.
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 */
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#define TYPE_SLAVIO_MISC "slavio_misc"
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OBJECT_DECLARE_SIMPLE_TYPE(MiscState, SLAVIO_MISC)
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struct MiscState {
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    SysBusDevice parent_obj;
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    MemoryRegion cfg_iomem;
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    MemoryRegion diag_iomem;
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    MemoryRegion mdm_iomem;
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    MemoryRegion led_iomem;
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    MemoryRegion sysctrl_iomem;
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    MemoryRegion aux1_iomem;
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    MemoryRegion aux2_iomem;
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    qemu_irq irq;
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    qemu_irq fdc_tc;
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    uint32_t dummy;
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    uint8_t config;
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    uint8_t aux1, aux2;
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    uint8_t diag, mctrl;
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    uint8_t sysctrl;
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    uint16_t leds;
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};
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#define TYPE_APC "apc"
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typedef struct APCState APCState;
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DECLARE_INSTANCE_CHECKER(APCState, APC,
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                         TYPE_APC)
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struct APCState {
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    SysBusDevice parent_obj;
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    MemoryRegion iomem;
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    qemu_irq cpu_halt;
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};
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#define MISC_SIZE 1
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#define LED_SIZE 2
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#define SYSCTRL_SIZE 4
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#define AUX1_TC        0x02
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#define AUX2_PWROFF    0x01
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#define AUX2_PWRINTCLR 0x02
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#define AUX2_PWRFAIL   0x20
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#define CFG_PWRINTEN   0x08
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#define SYS_RESET      0x01
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#define SYS_RESETSTAT  0x02
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static void slavio_misc_update_irq(void *opaque)
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{
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    MiscState *s = opaque;
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    if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
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        trace_slavio_misc_update_irq_raise();
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        qemu_irq_raise(s->irq);
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    } else {
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        trace_slavio_misc_update_irq_lower();
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        qemu_irq_lower(s->irq);
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    }
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}
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static void slavio_misc_reset(DeviceState *d)
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{
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    MiscState *s = SLAVIO_MISC(d);
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    // Diagnostic and system control registers not cleared in reset
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    s->config = s->aux1 = s->aux2 = s->mctrl = 0;
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}
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static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
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{
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    MiscState *s = opaque;
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    trace_slavio_set_power_fail(power_failing, s->config);
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    if (power_failing && (s->config & CFG_PWRINTEN)) {
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        s->aux2 |= AUX2_PWRFAIL;
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    } else {
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        s->aux2 &= ~AUX2_PWRFAIL;
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    }
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    slavio_misc_update_irq(s);
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}
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static void slavio_cfg_mem_writeb(void *opaque, hwaddr addr,
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                                  uint64_t val, unsigned size)
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{
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    MiscState *s = opaque;
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    trace_slavio_cfg_mem_writeb(val & 0xff);
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    s->config = val & 0xff;
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    slavio_misc_update_irq(s);
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}
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static uint64_t slavio_cfg_mem_readb(void *opaque, hwaddr addr,
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                                     unsigned size)
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{
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    MiscState *s = opaque;
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    uint32_t ret = 0;
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    ret = s->config;
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    trace_slavio_cfg_mem_readb(ret);
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    return ret;
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}
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static const MemoryRegionOps slavio_cfg_mem_ops = {
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    .read = slavio_cfg_mem_readb,
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    .write = slavio_cfg_mem_writeb,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    },
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};
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static void slavio_diag_mem_writeb(void *opaque, hwaddr addr,
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                                   uint64_t val, unsigned size)
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{
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    MiscState *s = opaque;
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    trace_slavio_diag_mem_writeb(val & 0xff);
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    s->diag = val & 0xff;
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}
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static uint64_t slavio_diag_mem_readb(void *opaque, hwaddr addr,
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                                      unsigned size)
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{
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    MiscState *s = opaque;
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    uint32_t ret = 0;
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    ret = s->diag;
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    trace_slavio_diag_mem_readb(ret);
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    return ret;
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}
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static const MemoryRegionOps slavio_diag_mem_ops = {
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    .read = slavio_diag_mem_readb,
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    .write = slavio_diag_mem_writeb,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    },
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};
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static void slavio_mdm_mem_writeb(void *opaque, hwaddr addr,
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                                  uint64_t val, unsigned size)
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{
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    MiscState *s = opaque;
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    trace_slavio_mdm_mem_writeb(val & 0xff);
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    s->mctrl = val & 0xff;
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}
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static uint64_t slavio_mdm_mem_readb(void *opaque, hwaddr addr,
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                                     unsigned size)
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{
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    MiscState *s = opaque;
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    uint32_t ret = 0;
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    ret = s->mctrl;
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    trace_slavio_mdm_mem_readb(ret);
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    return ret;
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}
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static const MemoryRegionOps slavio_mdm_mem_ops = {
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    .read = slavio_mdm_mem_readb,
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    .write = slavio_mdm_mem_writeb,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    },
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};
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static void slavio_aux1_mem_writeb(void *opaque, hwaddr addr,
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                                   uint64_t val, unsigned size)
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{
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    MiscState *s = opaque;
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    trace_slavio_aux1_mem_writeb(val & 0xff);
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    if (val & AUX1_TC) {
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        // Send a pulse to floppy terminal count line
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        if (s->fdc_tc) {
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            qemu_irq_raise(s->fdc_tc);
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            qemu_irq_lower(s->fdc_tc);
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        }
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        val &= ~AUX1_TC;
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    }
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    s->aux1 = val & 0xff;
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}
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static uint64_t slavio_aux1_mem_readb(void *opaque, hwaddr addr,
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                                      unsigned size)
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{
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    MiscState *s = opaque;
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    uint32_t ret = 0;
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    ret = s->aux1;
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    trace_slavio_aux1_mem_readb(ret);
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    return ret;
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}
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static const MemoryRegionOps slavio_aux1_mem_ops = {
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    .read = slavio_aux1_mem_readb,
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    .write = slavio_aux1_mem_writeb,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    },
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};
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static void slavio_aux2_mem_writeb(void *opaque, hwaddr addr,
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                                   uint64_t val, unsigned size)
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{
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    MiscState *s = opaque;
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    val &= AUX2_PWRINTCLR | AUX2_PWROFF;
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    trace_slavio_aux2_mem_writeb(val & 0xff);
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    val |= s->aux2 & AUX2_PWRFAIL;
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    if (val & AUX2_PWRINTCLR) // Clear Power Fail int
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        val &= AUX2_PWROFF;
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    s->aux2 = val;
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    if (val & AUX2_PWROFF)
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        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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    slavio_misc_update_irq(s);
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}
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static uint64_t slavio_aux2_mem_readb(void *opaque, hwaddr addr,
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                                      unsigned size)
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{
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    MiscState *s = opaque;
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    uint32_t ret = 0;
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    ret = s->aux2;
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    trace_slavio_aux2_mem_readb(ret);
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    return ret;
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}
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static const MemoryRegionOps slavio_aux2_mem_ops = {
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    .read = slavio_aux2_mem_readb,
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    .write = slavio_aux2_mem_writeb,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    },
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};
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static void apc_mem_writeb(void *opaque, hwaddr addr,
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                           uint64_t val, unsigned size)
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{
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    APCState *s = opaque;
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    trace_apc_mem_writeb(val & 0xff);
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    qemu_irq_raise(s->cpu_halt);
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}
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static uint64_t apc_mem_readb(void *opaque, hwaddr addr,
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                              unsigned size)
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{
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    uint32_t ret = 0;
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    trace_apc_mem_readb(ret);
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    return ret;
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}
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static const MemoryRegionOps apc_mem_ops = {
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    .read = apc_mem_readb,
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    .write = apc_mem_writeb,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    }
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};
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static uint64_t slavio_sysctrl_mem_readl(void *opaque, hwaddr addr,
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                                         unsigned size)
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{
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    MiscState *s = opaque;
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    uint32_t ret = 0;
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    switch (addr) {
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    case 0:
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        ret = s->sysctrl;
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        break;
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    default:
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        break;
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    }
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    trace_slavio_sysctrl_mem_readl(ret);
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    return ret;
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}
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static void slavio_sysctrl_mem_writel(void *opaque, hwaddr addr,
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                                      uint64_t val, unsigned size)
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{
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    MiscState *s = opaque;
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    trace_slavio_sysctrl_mem_writel(val);
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    switch (addr) {
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    case 0:
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        if (val & SYS_RESET) {
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            s->sysctrl = SYS_RESETSTAT;
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            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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        }
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        break;
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    default:
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        break;
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    }
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}
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static const MemoryRegionOps slavio_sysctrl_mem_ops = {
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    .read = slavio_sysctrl_mem_readl,
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    .write = slavio_sysctrl_mem_writel,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    },
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};
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static uint64_t slavio_led_mem_readw(void *opaque, hwaddr addr,
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                                     unsigned size)
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{
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    MiscState *s = opaque;
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    uint32_t ret = 0;
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    switch (addr) {
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    case 0:
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        ret = s->leds;
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        break;
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    default:
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        break;
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    }
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    trace_slavio_led_mem_readw(ret);
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    return ret;
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}
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static void slavio_led_mem_writew(void *opaque, hwaddr addr,
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                                  uint64_t val, unsigned size)
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{
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    MiscState *s = opaque;
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    trace_slavio_led_mem_writew(val & 0xffff);
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    switch (addr) {
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    case 0:
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        s->leds = val;
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        break;
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    default:
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        break;
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    }
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}
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static const MemoryRegionOps slavio_led_mem_ops = {
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    .read = slavio_led_mem_readw,
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    .write = slavio_led_mem_writew,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 2,
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        .max_access_size = 2,
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    },
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};
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static const VMStateDescription vmstate_misc = {
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    .name ="slavio_misc",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(dummy, MiscState),
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        VMSTATE_UINT8(config, MiscState),
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        VMSTATE_UINT8(aux1, MiscState),
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        VMSTATE_UINT8(aux2, MiscState),
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        VMSTATE_UINT8(diag, MiscState),
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        VMSTATE_UINT8(mctrl, MiscState),
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        VMSTATE_UINT8(sysctrl, MiscState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void apc_init(Object *obj)
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{
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    APCState *s = APC(obj);
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    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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    sysbus_init_irq(dev, &s->cpu_halt);
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    /* Power management (APC) XXX: not a Slavio device */
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    memory_region_init_io(&s->iomem, obj, &apc_mem_ops, s,
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                          "apc", MISC_SIZE);
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    sysbus_init_mmio(dev, &s->iomem);
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}
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static void slavio_misc_init(Object *obj)
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{
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    DeviceState *dev = DEVICE(obj);
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    MiscState *s = SLAVIO_MISC(obj);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    sysbus_init_irq(sbd, &s->irq);
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    sysbus_init_irq(sbd, &s->fdc_tc);
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    /* 8 bit registers */
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    /* Slavio control */
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    memory_region_init_io(&s->cfg_iomem, obj, &slavio_cfg_mem_ops, s,
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                          "configuration", MISC_SIZE);
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    sysbus_init_mmio(sbd, &s->cfg_iomem);
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    /* Diagnostics */
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    memory_region_init_io(&s->diag_iomem, obj, &slavio_diag_mem_ops, s,
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                          "diagnostic", MISC_SIZE);
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    sysbus_init_mmio(sbd, &s->diag_iomem);
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    /* Modem control */
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    memory_region_init_io(&s->mdm_iomem, obj, &slavio_mdm_mem_ops, s,
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                          "modem", MISC_SIZE);
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    sysbus_init_mmio(sbd, &s->mdm_iomem);
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    /* 16 bit registers */
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    /* ss600mp diag LEDs */
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    memory_region_init_io(&s->led_iomem, obj, &slavio_led_mem_ops, s,
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                          "leds", LED_SIZE);
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    sysbus_init_mmio(sbd, &s->led_iomem);
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    /* 32 bit registers */
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    /* System control */
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    memory_region_init_io(&s->sysctrl_iomem, obj, &slavio_sysctrl_mem_ops, s,
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                          "system-control", SYSCTRL_SIZE);
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    sysbus_init_mmio(sbd, &s->sysctrl_iomem);
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    /* AUX 1 (Misc System Functions) */
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    memory_region_init_io(&s->aux1_iomem, obj, &slavio_aux1_mem_ops, s,
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                          "misc-system-functions", MISC_SIZE);
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    sysbus_init_mmio(sbd, &s->aux1_iomem);
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    /* AUX 2 (Software Powerdown Control) */
479
    memory_region_init_io(&s->aux2_iomem, obj, &slavio_aux2_mem_ops, s,
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                          "software-powerdown-control", MISC_SIZE);
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    sysbus_init_mmio(sbd, &s->aux2_iomem);
482

483
    qdev_init_gpio_in(dev, slavio_set_power_fail, 1);
484
}
485

486
static void slavio_misc_class_init(ObjectClass *klass, void *data)
487
{
488
    DeviceClass *dc = DEVICE_CLASS(klass);
489

490
    dc->reset = slavio_misc_reset;
491
    dc->vmsd = &vmstate_misc;
492
}
493

494
static const TypeInfo slavio_misc_info = {
495
    .name          = TYPE_SLAVIO_MISC,
496
    .parent        = TYPE_SYS_BUS_DEVICE,
497
    .instance_size = sizeof(MiscState),
498
    .instance_init = slavio_misc_init,
499
    .class_init    = slavio_misc_class_init,
500
};
501

502
static const TypeInfo apc_info = {
503
    .name          = TYPE_APC,
504
    .parent        = TYPE_SYS_BUS_DEVICE,
505
    .instance_size = sizeof(MiscState),
506
    .instance_init = apc_init,
507
};
508

509
static void slavio_misc_register_types(void)
510
{
511
    type_register_static(&slavio_misc_info);
512
    type_register_static(&apc_info);
513
}
514

515
type_init(slavio_misc_register_types)
516