qemu

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/*
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 * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt)
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 *
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 * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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 *
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 * Simple model of the PRCI to emulate register reads made by the SDK BSP
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms and conditions of the GNU General Public License,
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 * version 2 or later, as published by the Free Software Foundation.
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 *
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 * This program is distributed in the hope it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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 * more details.
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 *
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 * You should have received a copy of the GNU General Public License along with
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 * this program.  If not, see <http://www.gnu.org/licenses/>.
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 */
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/misc/sifive_u_prci.h"
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static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size)
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{
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    SiFiveUPRCIState *s = opaque;
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    switch (addr) {
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    case SIFIVE_U_PRCI_HFXOSCCFG:
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        return s->hfxosccfg;
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    case SIFIVE_U_PRCI_COREPLLCFG0:
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        return s->corepllcfg0;
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    case SIFIVE_U_PRCI_DDRPLLCFG0:
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        return s->ddrpllcfg0;
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    case SIFIVE_U_PRCI_DDRPLLCFG1:
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        return s->ddrpllcfg1;
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    case SIFIVE_U_PRCI_GEMGXLPLLCFG0:
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        return s->gemgxlpllcfg0;
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    case SIFIVE_U_PRCI_GEMGXLPLLCFG1:
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        return s->gemgxlpllcfg1;
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    case SIFIVE_U_PRCI_CORECLKSEL:
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        return s->coreclksel;
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    case SIFIVE_U_PRCI_DEVICESRESET:
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        return s->devicesreset;
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    case SIFIVE_U_PRCI_CLKMUXSTATUS:
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        return s->clkmuxstatus;
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    }
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    qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
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                  __func__, addr);
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    return 0;
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}
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static void sifive_u_prci_write(void *opaque, hwaddr addr,
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                                uint64_t val64, unsigned int size)
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{
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    SiFiveUPRCIState *s = opaque;
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    uint32_t val32 = (uint32_t)val64;
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    switch (addr) {
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    case SIFIVE_U_PRCI_HFXOSCCFG:
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        s->hfxosccfg = val32;
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        /* OSC stays ready */
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        s->hfxosccfg |= SIFIVE_U_PRCI_HFXOSCCFG_RDY;
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        break;
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    case SIFIVE_U_PRCI_COREPLLCFG0:
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        s->corepllcfg0 = val32;
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        /* internal feedback */
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        s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
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        /* PLL stays locked */
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        s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
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        break;
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    case SIFIVE_U_PRCI_DDRPLLCFG0:
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        s->ddrpllcfg0 = val32;
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        /* internal feedback */
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        s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
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        /* PLL stays locked */
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        s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
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        break;
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    case SIFIVE_U_PRCI_DDRPLLCFG1:
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        s->ddrpllcfg1 = val32;
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        break;
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    case SIFIVE_U_PRCI_GEMGXLPLLCFG0:
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        s->gemgxlpllcfg0 = val32;
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        /* internal feedback */
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        s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE;
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        /* PLL stays locked */
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        s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK;
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        break;
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    case SIFIVE_U_PRCI_GEMGXLPLLCFG1:
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        s->gemgxlpllcfg1 = val32;
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        break;
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    case SIFIVE_U_PRCI_CORECLKSEL:
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        s->coreclksel = val32;
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        break;
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    case SIFIVE_U_PRCI_DEVICESRESET:
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        s->devicesreset = val32;
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        break;
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    case SIFIVE_U_PRCI_CLKMUXSTATUS:
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        s->clkmuxstatus = val32;
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
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                      " v=0x%x\n", __func__, addr, val32);
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    }
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}
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static const MemoryRegionOps sifive_u_prci_ops = {
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    .read = sifive_u_prci_read,
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    .write = sifive_u_prci_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4
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    }
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};
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static void sifive_u_prci_realize(DeviceState *dev, Error **errp)
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{
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    SiFiveUPRCIState *s = SIFIVE_U_PRCI(dev);
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    memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_prci_ops, s,
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                          TYPE_SIFIVE_U_PRCI, SIFIVE_U_PRCI_REG_SIZE);
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    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
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}
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static void sifive_u_prci_reset(DeviceState *dev)
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{
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    SiFiveUPRCIState *s = SIFIVE_U_PRCI(dev);
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    /* Initialize register to power-on-reset values */
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    s->hfxosccfg = SIFIVE_U_PRCI_HFXOSCCFG_RDY | SIFIVE_U_PRCI_HFXOSCCFG_EN;
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    s->corepllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF |
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                     SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE |
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                     SIFIVE_U_PRCI_PLLCFG0_LOCK;
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    s->ddrpllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF |
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                    SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE |
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                    SIFIVE_U_PRCI_PLLCFG0_LOCK;
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    s->gemgxlpllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF |
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                       SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE |
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                       SIFIVE_U_PRCI_PLLCFG0_LOCK;
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    s->coreclksel = SIFIVE_U_PRCI_CORECLKSEL_HFCLK;
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}
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static void sifive_u_prci_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->realize = sifive_u_prci_realize;
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    dc->reset = sifive_u_prci_reset;
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}
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static const TypeInfo sifive_u_prci_info = {
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    .name          = TYPE_SIFIVE_U_PRCI,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(SiFiveUPRCIState),
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    .class_init    = sifive_u_prci_class_init,
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};
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static void sifive_u_prci_register_types(void)
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{
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    type_register_static(&sifive_u_prci_info);
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}
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type_init(sifive_u_prci_register_types)
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