qemu

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/*
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 * nRF51 Random Number Generator
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 *
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 * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
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 *
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 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
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 *
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 * This code is licensed under the GPL version 2 or later.  See
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 * the COPYING file in the top-level directory.
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "hw/arm/nrf51.h"
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#include "hw/irq.h"
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#include "hw/misc/nrf51_rng.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qemu/guest-random.h"
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static void update_irq(NRF51RNGState *s)
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{
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    bool irq = s->interrupt_enabled && s->event_valrdy;
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    qemu_set_irq(s->irq, irq);
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}
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static uint64_t rng_read(void *opaque, hwaddr offset, unsigned int size)
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{
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    NRF51RNGState *s = NRF51_RNG(opaque);
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    uint64_t r = 0;
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    switch (offset) {
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    case NRF51_RNG_EVENT_VALRDY:
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        r = s->event_valrdy;
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        break;
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    case NRF51_RNG_REG_SHORTS:
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        r = s->shortcut_stop_on_valrdy;
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        break;
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    case NRF51_RNG_REG_INTEN:
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    case NRF51_RNG_REG_INTENSET:
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    case NRF51_RNG_REG_INTENCLR:
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        r = s->interrupt_enabled;
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        break;
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    case NRF51_RNG_REG_CONFIG:
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        r = s->filter_enabled;
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        break;
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    case NRF51_RNG_REG_VALUE:
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        r = s->value;
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: bad read offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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    }
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    return r;
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}
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static int64_t calc_next_timeout(NRF51RNGState *s)
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{
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    int64_t timeout = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL);
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    if (s->filter_enabled) {
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        timeout += s->period_filtered_us;
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    } else {
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        timeout += s->period_unfiltered_us;
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    }
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    return timeout;
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}
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static void rng_update_timer(NRF51RNGState *s)
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{
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    if (s->active) {
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        timer_mod(&s->timer, calc_next_timeout(s));
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    } else {
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        timer_del(&s->timer);
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    }
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}
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static void rng_write(void *opaque, hwaddr offset,
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                       uint64_t value, unsigned int size)
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{
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    NRF51RNGState *s = NRF51_RNG(opaque);
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    switch (offset) {
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    case NRF51_RNG_TASK_START:
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        if (value == NRF51_TRIGGER_TASK) {
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            s->active = 1;
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            rng_update_timer(s);
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        }
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        break;
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    case NRF51_RNG_TASK_STOP:
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        if (value == NRF51_TRIGGER_TASK) {
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            s->active = 0;
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            rng_update_timer(s);
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        }
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        break;
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    case NRF51_RNG_EVENT_VALRDY:
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        if (value == NRF51_EVENT_CLEAR) {
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            s->event_valrdy = 0;
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        }
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        break;
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    case NRF51_RNG_REG_SHORTS:
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        s->shortcut_stop_on_valrdy =
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                (value & BIT_MASK(NRF51_RNG_REG_SHORTS_VALRDY_STOP)) ? 1 : 0;
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        break;
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    case NRF51_RNG_REG_INTEN:
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        s->interrupt_enabled =
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                (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) ? 1 : 0;
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        break;
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    case NRF51_RNG_REG_INTENSET:
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        if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) {
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            s->interrupt_enabled = 1;
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        }
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        break;
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    case NRF51_RNG_REG_INTENCLR:
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        if (value & BIT_MASK(NRF51_RNG_REG_INTEN_VALRDY)) {
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            s->interrupt_enabled = 0;
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        }
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        break;
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    case NRF51_RNG_REG_CONFIG:
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        s->filter_enabled =
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                      (value & BIT_MASK(NRF51_RNG_REG_CONFIG_DECEN)) ? 1 : 0;
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: bad write offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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    }
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    update_irq(s);
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}
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static const MemoryRegionOps rng_ops = {
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    .read =  rng_read,
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    .write = rng_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .impl.min_access_size = 4,
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    .impl.max_access_size = 4
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};
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static void nrf51_rng_timer_expire(void *opaque)
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{
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    NRF51RNGState *s = NRF51_RNG(opaque);
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    qemu_guest_getrandom_nofail(&s->value, 1);
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    s->event_valrdy = 1;
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    qemu_set_irq(s->eep_valrdy, 1);
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    if (s->shortcut_stop_on_valrdy) {
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        s->active = 0;
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    }
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    rng_update_timer(s);
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    update_irq(s);
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}
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static void nrf51_rng_tep_start(void *opaque, int n, int level)
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{
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    NRF51RNGState *s = NRF51_RNG(opaque);
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    if (level) {
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        s->active = 1;
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        rng_update_timer(s);
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    }
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}
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static void nrf51_rng_tep_stop(void *opaque, int n, int level)
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{
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    NRF51RNGState *s = NRF51_RNG(opaque);
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    if (level) {
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        s->active = 0;
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        rng_update_timer(s);
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    }
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}
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static void nrf51_rng_init(Object *obj)
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{
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    NRF51RNGState *s = NRF51_RNG(obj);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    memory_region_init_io(&s->mmio, obj, &rng_ops, s,
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            TYPE_NRF51_RNG, NRF51_RNG_SIZE);
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    sysbus_init_mmio(sbd, &s->mmio);
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    timer_init_us(&s->timer, QEMU_CLOCK_VIRTUAL, nrf51_rng_timer_expire, s);
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    sysbus_init_irq(sbd, &s->irq);
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    /* Tasks */
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    qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_start, "tep_start", 1);
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    qdev_init_gpio_in_named(DEVICE(s), nrf51_rng_tep_stop, "tep_stop", 1);
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    /* Events */
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    qdev_init_gpio_out_named(DEVICE(s), &s->eep_valrdy, "eep_valrdy", 1);
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}
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static void nrf51_rng_reset(DeviceState *dev)
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{
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    NRF51RNGState *s = NRF51_RNG(dev);
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    s->value = 0;
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    s->active = 0;
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    s->event_valrdy = 0;
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    s->shortcut_stop_on_valrdy = 0;
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    s->interrupt_enabled = 0;
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    s->filter_enabled = 0;
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    rng_update_timer(s);
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}
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static Property nrf51_rng_properties[] = {
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    DEFINE_PROP_UINT16("period_unfiltered_us", NRF51RNGState,
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            period_unfiltered_us, 167),
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    DEFINE_PROP_UINT16("period_filtered_us", NRF51RNGState,
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            period_filtered_us, 660),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static const VMStateDescription vmstate_rng = {
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    .name = "nrf51_soc.rng",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(active, NRF51RNGState),
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        VMSTATE_UINT32(event_valrdy, NRF51RNGState),
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        VMSTATE_UINT32(shortcut_stop_on_valrdy, NRF51RNGState),
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        VMSTATE_UINT32(interrupt_enabled, NRF51RNGState),
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        VMSTATE_UINT32(filter_enabled, NRF51RNGState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void nrf51_rng_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    device_class_set_props(dc, nrf51_rng_properties);
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    dc->vmsd = &vmstate_rng;
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    dc->reset = nrf51_rng_reset;
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}
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static const TypeInfo nrf51_rng_info = {
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    .name = TYPE_NRF51_RNG,
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    .parent = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(NRF51RNGState),
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    .instance_init = nrf51_rng_init,
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    .class_init = nrf51_rng_class_init
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};
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static void nrf51_rng_register_types(void)
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{
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    type_register_static(&nrf51_rng_info);
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}
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type_init(nrf51_rng_register_types)
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