qemu

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/*
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 * Nuvoton NPCM7xx Random Number Generator.
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 *
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 * Copyright 2020 Google LLC
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 *
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 * This program is free software; you can redistribute it and/or modify it
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 * under the terms of the GNU General Public License as published by the
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 * Free Software Foundation; either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful, but WITHOUT
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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 * for more details.
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 */
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#include "qemu/osdep.h"
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#include "hw/misc/npcm7xx_rng.h"
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#include "migration/vmstate.h"
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#include "qemu/bitops.h"
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#include "qemu/guest-random.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "trace.h"
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#define NPCM7XX_RNG_REGS_SIZE   (4 * KiB)
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#define NPCM7XX_RNGCS           (0x00)
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#define NPCM7XX_RNGCS_CLKP(rv)      extract32(rv, 2, 4)
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#define NPCM7XX_RNGCS_DVALID        BIT(1)
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#define NPCM7XX_RNGCS_RNGE          BIT(0)
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#define NPCM7XX_RNGD            (0x04)
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#define NPCM7XX_RNGMODE         (0x08)
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#define NPCM7XX_RNGMODE_NORMAL      (0x02)
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static bool npcm7xx_rng_is_enabled(NPCM7xxRNGState *s)
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{
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    return (s->rngcs & NPCM7XX_RNGCS_RNGE) &&
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        (s->rngmode == NPCM7XX_RNGMODE_NORMAL);
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}
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static uint64_t npcm7xx_rng_read(void *opaque, hwaddr offset, unsigned size)
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{
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    NPCM7xxRNGState *s = opaque;
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    uint64_t value = 0;
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    switch (offset) {
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    case NPCM7XX_RNGCS:
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        /*
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         * If the RNG is enabled, but we don't have any valid random data, try
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         * obtaining some and update the DVALID bit accordingly.
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         */
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        if (!npcm7xx_rng_is_enabled(s)) {
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            s->rngcs &= ~NPCM7XX_RNGCS_DVALID;
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        } else if (!(s->rngcs & NPCM7XX_RNGCS_DVALID)) {
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            uint8_t byte = 0;
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            if (qemu_guest_getrandom(&byte, sizeof(byte), NULL) == 0) {
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                s->rngd = byte;
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                s->rngcs |= NPCM7XX_RNGCS_DVALID;
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            }
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        }
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        value = s->rngcs;
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        break;
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    case NPCM7XX_RNGD:
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        if (npcm7xx_rng_is_enabled(s) && s->rngcs & NPCM7XX_RNGCS_DVALID) {
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            s->rngcs &= ~NPCM7XX_RNGCS_DVALID;
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            value = s->rngd;
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            s->rngd = 0;
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        }
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        break;
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    case NPCM7XX_RNGMODE:
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        value = s->rngmode;
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: read from invalid offset 0x%" HWADDR_PRIx "\n",
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                      DEVICE(s)->canonical_path, offset);
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        break;
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    }
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    trace_npcm7xx_rng_read(offset, value, size);
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    return value;
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}
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static void npcm7xx_rng_write(void *opaque, hwaddr offset, uint64_t value,
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                              unsigned size)
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{
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    NPCM7xxRNGState *s = opaque;
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    trace_npcm7xx_rng_write(offset, value, size);
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    switch (offset) {
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    case NPCM7XX_RNGCS:
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        s->rngcs &= NPCM7XX_RNGCS_DVALID;
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        s->rngcs |= value & ~NPCM7XX_RNGCS_DVALID;
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        break;
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    case NPCM7XX_RNGD:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: write to read-only register @ 0x%" HWADDR_PRIx "\n",
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                      DEVICE(s)->canonical_path, offset);
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        break;
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    case NPCM7XX_RNGMODE:
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        s->rngmode = value;
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: write to invalid offset 0x%" HWADDR_PRIx "\n",
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                      DEVICE(s)->canonical_path, offset);
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        break;
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    }
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}
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static const MemoryRegionOps npcm7xx_rng_ops = {
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    .read = npcm7xx_rng_read,
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    .write = npcm7xx_rng_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 4,
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        .unaligned = false,
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    },
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};
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static void npcm7xx_rng_enter_reset(Object *obj, ResetType type)
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{
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    NPCM7xxRNGState *s = NPCM7XX_RNG(obj);
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    s->rngcs = 0;
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    s->rngd = 0;
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    s->rngmode = 0;
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}
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static void npcm7xx_rng_init(Object *obj)
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{
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    NPCM7xxRNGState *s = NPCM7XX_RNG(obj);
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    memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
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                          NPCM7XX_RNG_REGS_SIZE);
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    sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
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}
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static const VMStateDescription vmstate_npcm7xx_rng = {
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    .name = "npcm7xx-rng",
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    .version_id = 0,
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    .minimum_version_id = 0,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT8(rngcs, NPCM7xxRNGState),
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        VMSTATE_UINT8(rngd, NPCM7xxRNGState),
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        VMSTATE_UINT8(rngmode, NPCM7xxRNGState),
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        VMSTATE_END_OF_LIST(),
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    },
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};
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static void npcm7xx_rng_class_init(ObjectClass *klass, void *data)
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{
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    ResettableClass *rc = RESETTABLE_CLASS(klass);
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->desc = "NPCM7xx Random Number Generator";
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    dc->vmsd = &vmstate_npcm7xx_rng;
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    rc->phases.enter = npcm7xx_rng_enter_reset;
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}
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static const TypeInfo npcm7xx_rng_types[] = {
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    {
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        .name = TYPE_NPCM7XX_RNG,
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        .parent = TYPE_SYS_BUS_DEVICE,
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        .instance_size = sizeof(NPCM7xxRNGState),
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        .class_init = npcm7xx_rng_class_init,
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        .instance_init = npcm7xx_rng_init,
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    },
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};
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DEFINE_TYPES(npcm7xx_rng_types);
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