qemu

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/*
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 * Microchip PolarFire SoC SYSREG module emulation
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 *
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 * Copyright (c) 2020 Wind River Systems, Inc.
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 *
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 * Author:
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 *   Bin Meng <bin.meng@windriver.com>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "hw/misc/mchp_pfsoc_sysreg.h"
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#define ENVM_CR         0xb8
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#define MESSAGE_INT     0x118c
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static uint64_t mchp_pfsoc_sysreg_read(void *opaque, hwaddr offset,
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                                       unsigned size)
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{
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    uint32_t val = 0;
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    switch (offset) {
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    case ENVM_CR:
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        /* Indicate the eNVM is running at the configured divider rate */
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        val = BIT(6);
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        break;
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    default:
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        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
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                      "(size %d, offset 0x%" HWADDR_PRIx ")\n",
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                      __func__, size, offset);
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        break;
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    }
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    return val;
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}
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static void mchp_pfsoc_sysreg_write(void *opaque, hwaddr offset,
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                                    uint64_t value, unsigned size)
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{
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    MchpPfSoCSysregState *s = opaque;
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    switch (offset) {
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    case MESSAGE_INT:
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        qemu_irq_lower(s->irq);
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        break;
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    default:
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        qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
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                      "(size %d, value 0x%" PRIx64
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                      ", offset 0x%" HWADDR_PRIx ")\n",
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                      __func__, size, value, offset);
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    }
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}
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static const MemoryRegionOps mchp_pfsoc_sysreg_ops = {
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    .read = mchp_pfsoc_sysreg_read,
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    .write = mchp_pfsoc_sysreg_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void mchp_pfsoc_sysreg_realize(DeviceState *dev, Error **errp)
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{
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    MchpPfSoCSysregState *s = MCHP_PFSOC_SYSREG(dev);
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    memory_region_init_io(&s->sysreg, OBJECT(dev),
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                          &mchp_pfsoc_sysreg_ops, s,
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                          "mchp.pfsoc.sysreg",
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                          MCHP_PFSOC_SYSREG_REG_SIZE);
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    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->sysreg);
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    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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}
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static void mchp_pfsoc_sysreg_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->desc = "Microchip PolarFire SoC SYSREG module";
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    dc->realize = mchp_pfsoc_sysreg_realize;
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}
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static const TypeInfo mchp_pfsoc_sysreg_info = {
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    .name          = TYPE_MCHP_PFSOC_SYSREG,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(MchpPfSoCSysregState),
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    .class_init    = mchp_pfsoc_sysreg_class_init,
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};
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static void mchp_pfsoc_sysreg_register_types(void)
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{
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    type_register_static(&mchp_pfsoc_sysreg_info);
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}
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type_init(mchp_pfsoc_sysreg_register_types)
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