qemu

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/*
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 * PowerMac NewWorld MacIO GPIO emulation
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 *
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 * Copyright (c) 2016 Benjamin Herrenschmidt
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 * Copyright (c) 2018 Mark Cave-Ayland
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "hw/misc/macio/macio.h"
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#include "hw/misc/macio/gpio.h"
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#include "hw/irq.h"
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#include "hw/nmi.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "trace.h"
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void macio_set_gpio(MacIOGPIOState *s, uint32_t gpio, bool state)
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{
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    uint8_t new_reg;
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    trace_macio_set_gpio(gpio, state);
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    if (s->gpio_regs[gpio] & 4) {
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "GPIO: Setting GPIO %d while it's an output\n", gpio);
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    }
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    new_reg = s->gpio_regs[gpio] & ~2;
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    if (state) {
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        new_reg |= 2;
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    }
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    if (new_reg == s->gpio_regs[gpio]) {
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        return;
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    }
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    s->gpio_regs[gpio] = new_reg;
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    /*
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     * Note that we probably need to get access to the MPIC config to
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     * decode polarity since qemu always use "raise" regardless.
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     *
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     * For now, we hard wire known GPIOs
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     */
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    switch (gpio) {
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    case 1:
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        /* Level low */
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        if (!state) {
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            trace_macio_gpio_irq_assert(gpio);
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            qemu_irq_raise(s->gpio_extirqs[gpio]);
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        } else {
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            trace_macio_gpio_irq_deassert(gpio);
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            qemu_irq_lower(s->gpio_extirqs[gpio]);
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        }
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        break;
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    case 9:
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        /* Edge, triggered by NMI below */
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        if (state) {
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            trace_macio_gpio_irq_assert(gpio);
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            qemu_irq_raise(s->gpio_extirqs[gpio]);
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        } else {
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            trace_macio_gpio_irq_deassert(gpio);
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            qemu_irq_lower(s->gpio_extirqs[gpio]);
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        }
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        break;
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    default:
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        qemu_log_mask(LOG_UNIMP, "GPIO: setting unimplemented GPIO %d", gpio);
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    }
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}
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static void macio_gpio_write(void *opaque, hwaddr addr, uint64_t value,
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                             unsigned size)
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{
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    MacIOGPIOState *s = opaque;
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    uint8_t ibit;
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    trace_macio_gpio_write(addr, value);
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    /* Levels regs are read-only */
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    if (addr < 8) {
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        return;
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    }
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    addr -= 8;
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    if (addr < 36) {
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        value &= ~2;
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        if (value & 4) {
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            ibit = (value & 1) << 1;
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        } else {
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            ibit = s->gpio_regs[addr] & 2;
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        }
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        s->gpio_regs[addr] = value | ibit;
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    }
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}
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static uint64_t macio_gpio_read(void *opaque, hwaddr addr, unsigned size)
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{
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    MacIOGPIOState *s = opaque;
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    uint64_t val = 0;
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    /* Levels regs */
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    if (addr < 8) {
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        val = s->gpio_levels[addr];
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    } else {
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        addr -= 8;
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        if (addr < 36) {
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            val = s->gpio_regs[addr];
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        }
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    }
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    trace_macio_gpio_write(addr, val);
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    return val;
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}
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static const MemoryRegionOps macio_gpio_ops = {
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    .read = macio_gpio_read,
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    .write = macio_gpio_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .impl = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    },
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};
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static void macio_gpio_init(Object *obj)
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{
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    MacIOGPIOState *s = MACIO_GPIO(obj);
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    int i;
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    for (i = 0; i < 10; i++) {
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        sysbus_init_irq(sbd, &s->gpio_extirqs[i]);
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    }
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    memory_region_init_io(&s->gpiomem, OBJECT(s), &macio_gpio_ops, obj,
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                          "gpio", 0x30);
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    sysbus_init_mmio(sbd, &s->gpiomem);
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}
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static const VMStateDescription vmstate_macio_gpio = {
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    .name = "macio_gpio",
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    .version_id = 0,
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    .minimum_version_id = 0,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT8_ARRAY(gpio_levels, MacIOGPIOState, 8),
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        VMSTATE_UINT8_ARRAY(gpio_regs, MacIOGPIOState, 36),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void macio_gpio_reset(DeviceState *dev)
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{
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    MacIOGPIOState *s = MACIO_GPIO(dev);
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    /* GPIO 1 is up by default */
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    macio_set_gpio(s, 1, true);
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}
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static void macio_gpio_nmi(NMIState *n, int cpu_index, Error **errp)
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{
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    macio_set_gpio(MACIO_GPIO(n), 9, true);
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    macio_set_gpio(MACIO_GPIO(n), 9, false);
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}
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static void macio_gpio_class_init(ObjectClass *oc, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(oc);
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    NMIClass *nc = NMI_CLASS(oc);
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    dc->reset = macio_gpio_reset;
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    dc->vmsd = &vmstate_macio_gpio;
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    nc->nmi_monitor_handler = macio_gpio_nmi;
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}
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static const TypeInfo macio_gpio_init_info = {
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    .name          = TYPE_MACIO_GPIO,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(MacIOGPIOState),
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    .instance_init = macio_gpio_init,
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    .class_init    = macio_gpio_class_init,
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    .interfaces = (InterfaceInfo[]) {
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        { TYPE_NMI },
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        { }
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    },
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};
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static void macio_gpio_register_types(void)
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{
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    type_register_static(&macio_gpio_init_info);
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}
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type_init(macio_gpio_register_types)
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