qemu

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/*
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 * IMX7 System Reset Controller
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 *
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 * Copyright (c) 2023 Jean-Christophe Dubois <jcd@tribudubois.net>
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 *
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 * This work is licensed under the terms of the GNU GPL, version 2 or later.
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 * See the COPYING file in the top-level directory.
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 *
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 */
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#include "qemu/osdep.h"
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#include "hw/misc/imx7_src.h"
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#include "migration/vmstate.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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#include "qemu/module.h"
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#include "target/arm/arm-powerctl.h"
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#include "hw/core/cpu.h"
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#include "hw/registerfields.h"
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#include "trace.h"
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static const char *imx7_src_reg_name(uint32_t reg)
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{
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    static char unknown[20];
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    switch (reg) {
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    case SRC_SCR:
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        return "SRC_SCR";
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    case SRC_A7RCR0:
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        return "SRC_A7RCR0";
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    case SRC_A7RCR1:
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        return "SRC_A7RCR1";
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    case SRC_M4RCR:
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        return "SRC_M4RCR";
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    case SRC_ERCR:
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        return "SRC_ERCR";
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    case SRC_HSICPHY_RCR:
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        return "SRC_HSICPHY_RCR";
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    case SRC_USBOPHY1_RCR:
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        return "SRC_USBOPHY1_RCR";
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    case SRC_USBOPHY2_RCR:
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        return "SRC_USBOPHY2_RCR";
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    case SRC_PCIEPHY_RCR:
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        return "SRC_PCIEPHY_RCR";
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    case SRC_SBMR1:
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        return "SRC_SBMR1";
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    case SRC_SRSR:
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        return "SRC_SRSR";
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    case SRC_SISR:
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        return "SRC_SISR";
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    case SRC_SIMR:
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        return "SRC_SIMR";
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    case SRC_SBMR2:
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        return "SRC_SBMR2";
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    case SRC_GPR1:
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        return "SRC_GPR1";
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    case SRC_GPR2:
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        return "SRC_GPR2";
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    case SRC_GPR3:
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        return "SRC_GPR3";
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    case SRC_GPR4:
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        return "SRC_GPR4";
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    case SRC_GPR5:
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        return "SRC_GPR5";
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    case SRC_GPR6:
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        return "SRC_GPR6";
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    case SRC_GPR7:
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        return "SRC_GPR7";
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    case SRC_GPR8:
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        return "SRC_GPR8";
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    case SRC_GPR9:
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        return "SRC_GPR9";
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    case SRC_GPR10:
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        return "SRC_GPR10";
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    default:
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        snprintf(unknown, sizeof(unknown), "%u ?", reg);
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        return unknown;
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    }
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}
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static const VMStateDescription vmstate_imx7_src = {
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    .name = TYPE_IMX7_SRC,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32_ARRAY(regs, IMX7SRCState, SRC_MAX),
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        VMSTATE_END_OF_LIST()
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    },
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};
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static void imx7_src_reset(DeviceState *dev)
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{
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    IMX7SRCState *s = IMX7_SRC(dev);
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    memset(s->regs, 0, sizeof(s->regs));
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    /* Set reset values */
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    s->regs[SRC_SCR] = 0xA0;
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    s->regs[SRC_SRSR] = 0x1;
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    s->regs[SRC_SIMR] = 0x1F;
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}
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static uint64_t imx7_src_read(void *opaque, hwaddr offset, unsigned size)
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{
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    uint32_t value = 0;
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    IMX7SRCState *s = (IMX7SRCState *)opaque;
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    uint32_t index = offset >> 2;
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    if (index < SRC_MAX) {
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        value = s->regs[index];
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    } else {
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        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
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    }
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    trace_imx7_src_read(imx7_src_reg_name(index), value);
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    return value;
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}
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/*
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 * The reset is asynchronous so we need to defer clearing the reset
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 * bit until the work is completed.
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 */
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struct SRCSCRResetInfo {
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    IMX7SRCState *s;
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    uint32_t reset_bit;
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};
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static void imx7_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
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{
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    struct SRCSCRResetInfo *ri = data.host_ptr;
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    IMX7SRCState *s = ri->s;
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    assert(bql_locked());
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    s->regs[SRC_A7RCR0] = deposit32(s->regs[SRC_A7RCR0], ri->reset_bit, 1, 0);
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    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
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    g_free(ri);
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}
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static void imx7_defer_clear_reset_bit(uint32_t cpuid,
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                                       IMX7SRCState *s,
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                                       uint32_t reset_shift)
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{
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    struct SRCSCRResetInfo *ri;
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    CPUState *cpu = arm_get_cpu_by_id(cpuid);
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    if (!cpu) {
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        return;
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    }
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    ri = g_new(struct SRCSCRResetInfo, 1);
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    ri->s = s;
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    ri->reset_bit = reset_shift;
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    async_run_on_cpu(cpu, imx7_clear_reset_bit, RUN_ON_CPU_HOST_PTR(ri));
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}
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static void imx7_src_write(void *opaque, hwaddr offset, uint64_t value,
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                           unsigned size)
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{
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    IMX7SRCState *s = (IMX7SRCState *)opaque;
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    uint32_t index = offset >> 2;
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    long unsigned int change_mask;
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    uint32_t current_value = value;
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    if (index >= SRC_MAX) {
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        qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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                      HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset);
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        return;
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    }
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    trace_imx7_src_write(imx7_src_reg_name(SRC_A7RCR0), s->regs[SRC_A7RCR0]);
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    change_mask = s->regs[index] ^ (uint32_t)current_value;
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    switch (index) {
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    case SRC_A7RCR0:
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        if (FIELD_EX32(change_mask, CORE0, RST)) {
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            arm_reset_cpu(0);
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            imx7_defer_clear_reset_bit(0, s, R_CORE0_RST_SHIFT);
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        }
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        if (FIELD_EX32(change_mask, CORE1, RST)) {
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            arm_reset_cpu(1);
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            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
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        }
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        s->regs[index] = current_value;
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        break;
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    case SRC_A7RCR1:
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        /*
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         * On real hardware when the system reset controller starts a
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         * secondary CPU it runs through some boot ROM code which reads
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         * the SRC_GPRX registers controlling the start address and branches
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         * to it.
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         * Here we are taking a short cut and branching directly to the
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         * requested address (we don't want to run the boot ROM code inside
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         * QEMU)
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         */
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        if (FIELD_EX32(change_mask, CORE1, ENABLE)) {
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            if (FIELD_EX32(current_value, CORE1, ENABLE)) {
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                /* CORE 1 is brought up */
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                arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
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                               3, false);
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            } else {
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                /* CORE 1 is shut down */
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                arm_set_cpu_off(1);
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            }
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            /* We clear the reset bits as the processor changed state */
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            imx7_defer_clear_reset_bit(1, s, R_CORE1_RST_SHIFT);
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            clear_bit(R_CORE1_RST_SHIFT, &change_mask);
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        }
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        s->regs[index] = current_value;
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        break;
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    default:
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        s->regs[index] = current_value;
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        break;
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    }
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}
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static const struct MemoryRegionOps imx7_src_ops = {
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    .read = imx7_src_read,
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    .write = imx7_src_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        /*
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         * Our device would not work correctly if the guest was doing
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         * unaligned access. This might not be a limitation on the real
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         * device but in practice there is no reason for a guest to access
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         * this device unaligned.
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         */
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        .min_access_size = 4,
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        .max_access_size = 4,
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        .unaligned = false,
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    },
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};
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static void imx7_src_realize(DeviceState *dev, Error **errp)
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{
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    IMX7SRCState *s = IMX7_SRC(dev);
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    memory_region_init_io(&s->iomem, OBJECT(dev), &imx7_src_ops, s,
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                          TYPE_IMX7_SRC, 0x1000);
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    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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}
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static void imx7_src_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->realize = imx7_src_realize;
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    dc->reset = imx7_src_reset;
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    dc->vmsd = &vmstate_imx7_src;
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    dc->desc = "i.MX6 System Reset Controller";
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}
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static const TypeInfo imx7_src_info = {
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    .name          = TYPE_IMX7_SRC,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(IMX7SRCState),
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    .class_init    = imx7_src_class_init,
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};
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static void imx7_src_register_types(void)
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{
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    type_register_static(&imx7_src_info);
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}
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type_init(imx7_src_register_types)
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