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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "qemu/timer.h"
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#include "migration/vmstate.h"
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#include "hw/misc/imx7_snvs.h"
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#include "qemu/cutils.h"
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#include "qemu/module.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/rtc.h"
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#include "sysemu/runstate.h"
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#define RTC_FREQ 32768ULL
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static const VMStateDescription vmstate_imx7_snvs = {
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.name = TYPE_IMX7_SNVS,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT64(tick_offset, IMX7SNVSState),
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VMSTATE_UINT64(lpcr, IMX7SNVSState),
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static uint64_t imx7_snvs_get_count(IMX7SNVSState *s)
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uint64_t ticks = muldiv64(qemu_clock_get_ns(rtc_clock), RTC_FREQ,
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NANOSECONDS_PER_SECOND);
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return s->tick_offset + ticks;
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static uint64_t imx7_snvs_read(void *opaque, hwaddr offset, unsigned size)
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IMX7SNVSState *s = IMX7_SNVS(opaque);
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ret = extract64(imx7_snvs_get_count(s), 32, 15);
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ret = extract64(imx7_snvs_get_count(s), 0, 32);
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trace_imx7_snvs_read(offset, ret, size);
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static void imx7_snvs_reset(DeviceState *dev)
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IMX7SNVSState *s = IMX7_SNVS(dev);
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static void imx7_snvs_write(void *opaque, hwaddr offset,
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uint64_t v, unsigned size)
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trace_imx7_snvs_write(offset, v, size);
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IMX7SNVSState *s = IMX7_SNVS(opaque);
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uint64_t new_value = 0, snvs_count = 0;
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if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) {
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snvs_count = imx7_snvs_get_count(s);
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new_value = deposit64(snvs_count, 32, 32, v);
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new_value = deposit64(snvs_count, 0, 32, v);
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const uint32_t mask = SNVS_LPCR_TOP | SNVS_LPCR_DP_EN;
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if ((v & mask) == mask) {
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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if (offset == SNVS_LPSRTCMR || offset == SNVS_LPSRTCLR) {
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s->tick_offset += new_value - snvs_count;
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static const struct MemoryRegionOps imx7_snvs_ops = {
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.read = imx7_snvs_read,
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.write = imx7_snvs_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.min_access_size = 4,
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.max_access_size = 4,
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static void imx7_snvs_init(Object *obj)
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SysBusDevice *sd = SYS_BUS_DEVICE(obj);
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IMX7SNVSState *s = IMX7_SNVS(obj);
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memory_region_init_io(&s->mmio, obj, &imx7_snvs_ops, s,
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TYPE_IMX7_SNVS, 0x1000);
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sysbus_init_mmio(sd, &s->mmio);
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qemu_get_timedate(&tm, 0);
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s->tick_offset = mktimegm(&tm) -
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qemu_clock_get_ns(rtc_clock) / NANOSECONDS_PER_SECOND;
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static void imx7_snvs_class_init(ObjectClass *klass, void *data)
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = imx7_snvs_reset;
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dc->vmsd = &vmstate_imx7_snvs;
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dc->desc = "i.MX7 Secure Non-Volatile Storage Module";
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static const TypeInfo imx7_snvs_info = {
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.name = TYPE_IMX7_SNVS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMX7SNVSState),
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.instance_init = imx7_snvs_init,
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.class_init = imx7_snvs_class_init,
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static void imx7_snvs_register_type(void)
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type_register_static(&imx7_snvs_info);
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type_init(imx7_snvs_register_type)