2
* IMX31 Clock Control Module
4
* Copyright (C) 2012 NICTA
5
* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
7
* This work is licensed under the terms of the GNU GPL, version 2 or later.
8
* See the COPYING file in the top-level directory.
10
* To get the timer frequencies right, we need to emulate at least part of
14
#include "qemu/osdep.h"
15
#include "hw/misc/imx31_ccm.h"
16
#include "migration/vmstate.h"
18
#include "qemu/module.h"
20
#define CKIH_FREQ 26000000 /* 26MHz crystal input */
22
#ifndef DEBUG_IMX31_CCM
23
#define DEBUG_IMX31_CCM 0
26
#define DPRINTF(fmt, args...) \
28
if (DEBUG_IMX31_CCM) { \
29
fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX31_CCM, \
34
static const char *imx31_ccm_reg_name(uint32_t reg)
36
static char unknown[20];
39
case IMX31_CCM_CCMR_REG:
41
case IMX31_CCM_PDR0_REG:
43
case IMX31_CCM_PDR1_REG:
45
case IMX31_CCM_RCSR_REG:
47
case IMX31_CCM_MPCTL_REG:
49
case IMX31_CCM_UPCTL_REG:
51
case IMX31_CCM_SPCTL_REG:
53
case IMX31_CCM_COSR_REG:
55
case IMX31_CCM_CGR0_REG:
57
case IMX31_CCM_CGR1_REG:
59
case IMX31_CCM_CGR2_REG:
61
case IMX31_CCM_WIMR_REG:
63
case IMX31_CCM_LDC_REG:
65
case IMX31_CCM_DCVR0_REG:
67
case IMX31_CCM_DCVR1_REG:
69
case IMX31_CCM_DCVR2_REG:
71
case IMX31_CCM_DCVR3_REG:
73
case IMX31_CCM_LTR0_REG:
75
case IMX31_CCM_LTR1_REG:
77
case IMX31_CCM_LTR2_REG:
79
case IMX31_CCM_LTR3_REG:
81
case IMX31_CCM_LTBR0_REG:
83
case IMX31_CCM_LTBR1_REG:
85
case IMX31_CCM_PMCR0_REG:
87
case IMX31_CCM_PMCR1_REG:
89
case IMX31_CCM_PDR2_REG:
92
snprintf(unknown, sizeof(unknown), "[%u ?]", reg);
97
static const VMStateDescription vmstate_imx31_ccm = {
98
.name = TYPE_IMX31_CCM,
100
.minimum_version_id = 2,
101
.fields = (const VMStateField[]) {
102
VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
103
VMSTATE_END_OF_LIST()
107
static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
110
IMX31CCMState *s = IMX31_CCM(dev);
112
if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
113
if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
115
if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
123
DPRINTF("freq = %u\n", freq);
128
static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
131
IMX31CCMState *s = IMX31_CCM(dev);
133
freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
134
imx31_ccm_get_pll_ref_clk(dev));
136
DPRINTF("freq = %u\n", freq);
141
static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
144
IMX31CCMState *s = IMX31_CCM(dev);
146
if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) ||
147
!(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
148
freq = imx31_ccm_get_pll_ref_clk(dev);
150
freq = imx31_ccm_get_mpll_clk(dev);
153
DPRINTF("freq = %u\n", freq);
158
static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
161
IMX31CCMState *s = IMX31_CCM(dev);
163
freq = imx31_ccm_get_mcu_main_clk(dev)
164
/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
166
DPRINTF("freq = %u\n", freq);
171
static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
174
IMX31CCMState *s = IMX31_CCM(dev);
176
freq = imx31_ccm_get_hclk_clk(dev)
177
/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
179
DPRINTF("freq = %u\n", freq);
184
static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
193
freq = imx31_ccm_get_ipg_clk(dev);
199
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
200
TYPE_IMX31_CCM, __func__, clock);
204
DPRINTF("Clock = %d) = %u\n", clock, freq);
209
static void imx31_ccm_reset(DeviceState *dev)
211
IMX31CCMState *s = IMX31_CCM(dev);
215
memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);
217
s->reg[IMX31_CCM_CCMR_REG] = 0x074b0b7d;
218
s->reg[IMX31_CCM_PDR0_REG] = 0xff870b48;
219
s->reg[IMX31_CCM_PDR1_REG] = 0x49fcfe7f;
220
s->reg[IMX31_CCM_RCSR_REG] = 0x007f0000;
221
s->reg[IMX31_CCM_MPCTL_REG] = 0x04001800;
222
s->reg[IMX31_CCM_UPCTL_REG] = 0x04051c03;
223
s->reg[IMX31_CCM_SPCTL_REG] = 0x04043001;
224
s->reg[IMX31_CCM_COSR_REG] = 0x00000280;
225
s->reg[IMX31_CCM_CGR0_REG] = 0xffffffff;
226
s->reg[IMX31_CCM_CGR1_REG] = 0xffffffff;
227
s->reg[IMX31_CCM_CGR2_REG] = 0xffffffff;
228
s->reg[IMX31_CCM_WIMR_REG] = 0xffffffff;
229
s->reg[IMX31_CCM_LTR1_REG] = 0x00004040;
230
s->reg[IMX31_CCM_PMCR0_REG] = 0x80209828;
231
s->reg[IMX31_CCM_PMCR1_REG] = 0x00aa0000;
232
s->reg[IMX31_CCM_PDR2_REG] = 0x00000285;
235
static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
238
IMX31CCMState *s = (IMX31CCMState *)opaque;
240
if ((offset >> 2) < IMX31_CCM_MAX_REG) {
241
value = s->reg[offset >> 2];
243
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
244
HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
247
DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
250
return (uint64_t)value;
253
static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
256
IMX31CCMState *s = (IMX31CCMState *)opaque;
258
DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
261
switch (offset >> 2) {
262
case IMX31_CCM_CCMR_REG:
263
s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff);
265
case IMX31_CCM_PDR0_REG:
266
s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
268
case IMX31_CCM_PDR1_REG:
269
s->reg[IMX31_CCM_PDR1_REG] = value;
271
case IMX31_CCM_MPCTL_REG:
272
s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
274
case IMX31_CCM_SPCTL_REG:
275
s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
277
case IMX31_CCM_CGR0_REG:
278
s->reg[IMX31_CCM_CGR0_REG] = value;
280
case IMX31_CCM_CGR1_REG:
281
s->reg[IMX31_CCM_CGR1_REG] = value;
283
case IMX31_CCM_CGR2_REG:
284
s->reg[IMX31_CCM_CGR2_REG] = value;
287
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
288
HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
293
static const struct MemoryRegionOps imx31_ccm_ops = {
294
.read = imx31_ccm_read,
295
.write = imx31_ccm_write,
296
.endianness = DEVICE_NATIVE_ENDIAN,
299
* Our device would not work correctly if the guest was doing
300
* unaligned access. This might not be a limitation on the real
301
* device but in practice there is no reason for a guest to access
302
* this device unaligned.
304
.min_access_size = 4,
305
.max_access_size = 4,
311
static void imx31_ccm_init(Object *obj)
313
DeviceState *dev = DEVICE(obj);
314
SysBusDevice *sd = SYS_BUS_DEVICE(obj);
315
IMX31CCMState *s = IMX31_CCM(obj);
317
memory_region_init_io(&s->iomem, OBJECT(dev), &imx31_ccm_ops, s,
318
TYPE_IMX31_CCM, 0x1000);
319
sysbus_init_mmio(sd, &s->iomem);
322
static void imx31_ccm_class_init(ObjectClass *klass, void *data)
324
DeviceClass *dc = DEVICE_CLASS(klass);
325
IMXCCMClass *ccm = IMX_CCM_CLASS(klass);
327
dc->reset = imx31_ccm_reset;
328
dc->vmsd = &vmstate_imx31_ccm;
329
dc->desc = "i.MX31 Clock Control Module";
331
ccm->get_clock_frequency = imx31_ccm_get_clock_frequency;
334
static const TypeInfo imx31_ccm_info = {
335
.name = TYPE_IMX31_CCM,
336
.parent = TYPE_IMX_CCM,
337
.instance_size = sizeof(IMX31CCMState),
338
.instance_init = imx31_ccm_init,
339
.class_init = imx31_ccm_class_init,
342
static void imx31_ccm_register_types(void)
344
type_register_static(&imx31_ccm_info);
347
type_init(imx31_ccm_register_types)