qemu

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/*
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 *  Exynos4210 Pseudo Random Number Generator Emulation
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 *
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 *  Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
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 *
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 *  This program is free software; you can redistribute it and/or modify it
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 *  under the terms of the GNU General Public License as published by the
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 *  Free Software Foundation; either version 2 of the License, or
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 *  (at your option) any later version.
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 *
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 *  This program is distributed in the hope that it will be useful, but WITHOUT
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 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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 *  for more details.
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 *
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 *  You should have received a copy of the GNU General Public License along
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 *  with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/guest-random.h"
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#include "qemu/module.h"
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#include "qom/object.h"
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#define DEBUG_EXYNOS_RNG 0
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#define DPRINTF(fmt, ...) \
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    do { \
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        if (DEBUG_EXYNOS_RNG) { \
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            printf("exynos4210_rng: " fmt, ## __VA_ARGS__); \
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        } \
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    } while (0)
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#define TYPE_EXYNOS4210_RNG             "exynos4210.rng"
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OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210RngState, EXYNOS4210_RNG)
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/*
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 * Exynos4220, PRNG, only polling mode is supported.
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 */
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/* RNG_CONTROL_1 register bitfields, reset value: 0x0 */
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#define EXYNOS4210_RNG_CONTROL_1_PRNG           0x8
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#define EXYNOS4210_RNG_CONTROL_1_START_INIT     BIT(4)
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/* RNG_STATUS register bitfields, reset value: 0x1 */
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#define EXYNOS4210_RNG_STATUS_PRNG_ERROR        BIT(7)
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#define EXYNOS4210_RNG_STATUS_PRNG_DONE         BIT(5)
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#define EXYNOS4210_RNG_STATUS_MSG_DONE          BIT(4)
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#define EXYNOS4210_RNG_STATUS_PARTIAL_DONE      BIT(3)
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#define EXYNOS4210_RNG_STATUS_PRNG_BUSY         BIT(2)
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#define EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE BIT(1)
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#define EXYNOS4210_RNG_STATUS_BUFFER_READY      BIT(0)
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#define EXYNOS4210_RNG_STATUS_WRITE_MASK   (EXYNOS4210_RNG_STATUS_PRNG_DONE \
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                                           | EXYNOS4210_RNG_STATUS_MSG_DONE \
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                                           | EXYNOS4210_RNG_STATUS_PARTIAL_DONE)
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#define EXYNOS4210_RNG_CONTROL_1                  0x0
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#define EXYNOS4210_RNG_STATUS                    0x10
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#define EXYNOS4210_RNG_SEED_IN                  0x140
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#define EXYNOS4210_RNG_SEED_IN_OFFSET(n)   (EXYNOS4210_RNG_SEED_IN + (n * 0x4))
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#define EXYNOS4210_RNG_PRNG                     0x160
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#define EXYNOS4210_RNG_PRNG_OFFSET(n)      (EXYNOS4210_RNG_PRNG + (n * 0x4))
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#define EXYNOS4210_RNG_PRNG_NUM                 5
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#define EXYNOS4210_RNG_REGS_MEM_SIZE            0x200
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struct Exynos4210RngState {
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    SysBusDevice parent_obj;
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    MemoryRegion iomem;
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    int32_t randr_value[EXYNOS4210_RNG_PRNG_NUM];
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    /* bits from 0 to EXYNOS4210_RNG_PRNG_NUM if given seed register was set */
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    uint32_t seed_set;
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    /* Register values */
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    uint32_t reg_control;
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    uint32_t reg_status;
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};
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static bool exynos4210_rng_seed_ready(const Exynos4210RngState *s)
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{
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    uint32_t mask = MAKE_64BIT_MASK(0, EXYNOS4210_RNG_PRNG_NUM);
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    /* Return true if all the seed-set bits are set. */
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    return (s->seed_set & mask) == mask;
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}
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static void exynos4210_rng_set_seed(Exynos4210RngState *s, unsigned int i,
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                                    uint64_t val)
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{
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    /*
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     * We actually ignore the seed and always generate true random numbers.
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     * Theoretically this should not match the device as Exynos has
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     * a Pseudo Random Number Generator but testing shown that it always
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     * generates random numbers regardless of the seed value.
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     */
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    s->seed_set |= BIT(i);
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    /* If all seeds were written, update the status to reflect it */
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    if (exynos4210_rng_seed_ready(s)) {
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        s->reg_status |= EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
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    } else {
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        s->reg_status &= ~EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
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    }
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}
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static void exynos4210_rng_run_engine(Exynos4210RngState *s)
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{
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    Error *err = NULL;
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    /* Seed set? */
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    if ((s->reg_status & EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE) == 0) {
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        goto out;
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    }
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    /* PRNG engine chosen? */
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    if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_PRNG) == 0) {
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        goto out;
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    }
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    /* PRNG engine started? */
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    if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_START_INIT) == 0) {
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        goto out;
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    }
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    /* Get randoms */
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    if (qemu_guest_getrandom(s->randr_value, sizeof(s->randr_value), &err)) {
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        error_report_err(err);
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    } else {
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        /* Notify that PRNG is ready */
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        s->reg_status |= EXYNOS4210_RNG_STATUS_PRNG_DONE;
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    }
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out:
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    /* Always clear start engine bit */
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    s->reg_control &= ~EXYNOS4210_RNG_CONTROL_1_START_INIT;
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}
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static uint64_t exynos4210_rng_read(void *opaque, hwaddr offset,
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                                    unsigned size)
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{
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    Exynos4210RngState *s = (Exynos4210RngState *)opaque;
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    uint32_t val = 0;
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    assert(size == 4);
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    switch (offset) {
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    case EXYNOS4210_RNG_CONTROL_1:
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        val = s->reg_control;
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        break;
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    case EXYNOS4210_RNG_STATUS:
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        val = s->reg_status;
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        break;
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    case EXYNOS4210_RNG_PRNG_OFFSET(0):
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    case EXYNOS4210_RNG_PRNG_OFFSET(1):
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    case EXYNOS4210_RNG_PRNG_OFFSET(2):
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    case EXYNOS4210_RNG_PRNG_OFFSET(3):
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    case EXYNOS4210_RNG_PRNG_OFFSET(4):
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        val = s->randr_value[(offset - EXYNOS4210_RNG_PRNG_OFFSET(0)) / 4];
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        DPRINTF("returning random @0x%" HWADDR_PRIx ": 0x%" PRIx32 "\n",
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                offset, val);
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: bad read offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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    }
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    return val;
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}
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static void exynos4210_rng_write(void *opaque, hwaddr offset,
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                                 uint64_t val, unsigned size)
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{
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    Exynos4210RngState *s = (Exynos4210RngState *)opaque;
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    assert(size == 4);
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    switch (offset) {
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    case EXYNOS4210_RNG_CONTROL_1:
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        DPRINTF("RNG_CONTROL_1 = 0x%" PRIx64 "\n", val);
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        s->reg_control = val;
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        exynos4210_rng_run_engine(s);
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        break;
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    case EXYNOS4210_RNG_STATUS:
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        /* For clearing status fields */
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        s->reg_status &= ~EXYNOS4210_RNG_STATUS_WRITE_MASK;
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        s->reg_status |= val & EXYNOS4210_RNG_STATUS_WRITE_MASK;
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        break;
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    case EXYNOS4210_RNG_SEED_IN_OFFSET(0):
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    case EXYNOS4210_RNG_SEED_IN_OFFSET(1):
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    case EXYNOS4210_RNG_SEED_IN_OFFSET(2):
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    case EXYNOS4210_RNG_SEED_IN_OFFSET(3):
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    case EXYNOS4210_RNG_SEED_IN_OFFSET(4):
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        exynos4210_rng_set_seed(s,
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                                (offset - EXYNOS4210_RNG_SEED_IN_OFFSET(0)) / 4,
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                                val);
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: bad write offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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    }
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}
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static const MemoryRegionOps exynos4210_rng_ops = {
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    .read = exynos4210_rng_read,
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    .write = exynos4210_rng_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid.min_access_size = 4,
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    .valid.max_access_size = 4,
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};
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static void exynos4210_rng_reset(DeviceState *dev)
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{
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    Exynos4210RngState *s = EXYNOS4210_RNG(dev);
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    s->reg_control = 0;
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    s->reg_status = EXYNOS4210_RNG_STATUS_BUFFER_READY;
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    memset(s->randr_value, 0, sizeof(s->randr_value));
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    s->seed_set = 0;
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}
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static void exynos4210_rng_init(Object *obj)
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{
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    Exynos4210RngState *s = EXYNOS4210_RNG(obj);
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    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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    memory_region_init_io(&s->iomem, obj, &exynos4210_rng_ops, s,
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                          TYPE_EXYNOS4210_RNG, EXYNOS4210_RNG_REGS_MEM_SIZE);
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    sysbus_init_mmio(dev, &s->iomem);
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}
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static const VMStateDescription exynos4210_rng_vmstate = {
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    .name = TYPE_EXYNOS4210_RNG,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_INT32_ARRAY(randr_value, Exynos4210RngState,
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                            EXYNOS4210_RNG_PRNG_NUM),
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        VMSTATE_UINT32(seed_set, Exynos4210RngState),
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        VMSTATE_UINT32(reg_status, Exynos4210RngState),
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        VMSTATE_UINT32(reg_control, Exynos4210RngState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void exynos4210_rng_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->reset = exynos4210_rng_reset;
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    dc->vmsd = &exynos4210_rng_vmstate;
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}
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static const TypeInfo exynos4210_rng_info = {
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    .name          = TYPE_EXYNOS4210_RNG,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(Exynos4210RngState),
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    .instance_init = exynos4210_rng_init,
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    .class_init    = exynos4210_rng_class_init,
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};
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static void exynos4210_rng_register(void)
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{
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    type_register_static(&exynos4210_rng_info);
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}
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type_init(exynos4210_rng_register)
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