qemu

1
/*
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 *  Exynos4210 Power Management Unit (PMU) Emulation
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 *
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 *  Copyright (C) 2011 Samsung Electronics Co Ltd.
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 *    Maksim Kozlov <m.kozlov@samsung.com>
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 *
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 *  This program is free software; you can redistribute it and/or modify it
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 *  under the terms of the GNU General Public License as published by the
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 *  Free Software Foundation; either version 2 of the License, or
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 *  (at your option) any later version.
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 *
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 *  This program is distributed in the hope that it will be useful, but WITHOUT
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 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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 *  for more details.
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 *
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 *  You should have received a copy of the GNU General Public License along
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 *  with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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/*
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 * This model implements PMU registers just as a bulk of memory. Currently,
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 * the only reason this device exists is that secondary CPU boot loader
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 * uses PMU INFORM5 register as a holding pen.
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 */
26

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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "sysemu/runstate.h"
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#include "qom/object.h"
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#ifndef DEBUG_PMU
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#define DEBUG_PMU           0
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#endif
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#ifndef DEBUG_PMU_EXTEND
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#define DEBUG_PMU_EXTEND    0
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#endif
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#if DEBUG_PMU
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#define  PRINT_DEBUG(fmt, args...)  \
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        do { \
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            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
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        } while (0)
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#if DEBUG_PMU_EXTEND
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#define  PRINT_DEBUG_EXTEND(fmt, args...) \
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        do { \
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            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
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        } while (0)
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#else
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#define  PRINT_DEBUG_EXTEND(fmt, args...)  do {} while (0)
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#endif /* EXTEND */
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#else
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#define  PRINT_DEBUG(fmt, args...)   do {} while (0)
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#define  PRINT_DEBUG_EXTEND(fmt, args...)  do {} while (0)
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#endif
61

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/*
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 *  Offsets for PMU registers
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 */
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#define OM_STAT                  0x0000 /* OM status register */
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#define RTC_CLKO_SEL             0x000C /* Controls RTCCLKOUT */
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#define GNSS_RTC_OUT_CTRL        0x0010 /* Controls GNSS_RTC_OUT */
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/* Decides whether system-level low-power mode is used. */
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#define SYSTEM_POWER_DOWN_CTRL   0x0200
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/* Sets control options for CENTRAL_SEQ */
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#define SYSTEM_POWER_DOWN_OPTION 0x0208
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#define SWRESET                  0x0400 /* Generate software reset */
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#define RST_STAT                 0x0404 /* Reset status register */
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#define WAKEUP_STAT              0x0600 /* Wakeup status register  */
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#define EINT_WAKEUP_MASK         0x0604 /* Configure External INTerrupt mask */
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#define WAKEUP_MASK              0x0608 /* Configure wakeup source mask */
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#define HDMI_PHY_CONTROL         0x0700 /* HDMI PHY control register */
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#define USBDEVICE_PHY_CONTROL    0x0704 /* USB Device PHY control register */
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#define USBHOST_PHY_CONTROL      0x0708 /* USB HOST PHY control register */
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#define DAC_PHY_CONTROL          0x070C /* DAC control register  */
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#define MIPI_PHY0_CONTROL        0x0710 /* MIPI PHY control register */
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#define MIPI_PHY1_CONTROL        0x0714 /* MIPI PHY control register */
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#define ADC_PHY_CONTROL          0x0718 /* TS-ADC control register */
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#define PCIe_PHY_CONTROL         0x071C /* TS-PCIe control register */
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#define SATA_PHY_CONTROL         0x0720 /* TS-SATA control register */
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#define INFORM0                  0x0800 /* Information register 0  */
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#define INFORM1                  0x0804 /* Information register 1  */
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#define INFORM2                  0x0808 /* Information register 2  */
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#define INFORM3                  0x080C /* Information register 3  */
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#define INFORM4                  0x0810 /* Information register 4  */
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#define INFORM5                  0x0814 /* Information register 5  */
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#define INFORM6                  0x0818 /* Information register 6  */
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#define INFORM7                  0x081C /* Information register 7  */
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#define PMU_DEBUG                0x0A00 /* PMU debug register */
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/* Registers to set system-level low-power option */
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#define ARM_CORE0_SYS_PWR_REG              0x1000
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#define ARM_CORE1_SYS_PWR_REG              0x1010
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#define ARM_COMMON_SYS_PWR_REG             0x1080
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#define ARM_CPU_L2_0_SYS_PWR_REG           0x10C0
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#define ARM_CPU_L2_1_SYS_PWR_REG           0x10C4
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#define CMU_ACLKSTOP_SYS_PWR_REG           0x1100
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#define CMU_SCLKSTOP_SYS_PWR_REG           0x1104
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#define CMU_RESET_SYS_PWR_REG              0x110C
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#define APLL_SYSCLK_SYS_PWR_REG            0x1120
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#define MPLL_SYSCLK_SYS_PWR_REG            0x1124
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#define VPLL_SYSCLK_SYS_PWR_REG            0x1128
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#define EPLL_SYSCLK_SYS_PWR_REG            0x112C
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#define CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG  0x1138
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#define CMU_RESET_GPS_ALIVE_SYS_PWR_REG    0x113C
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#define CMU_CLKSTOP_CAM_SYS_PWR_REG        0x1140
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#define CMU_CLKSTOP_TV_SYS_PWR_REG         0x1144
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#define CMU_CLKSTOP_MFC_SYS_PWR_REG        0x1148
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#define CMU_CLKSTOP_G3D_SYS_PWR_REG        0x114C
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#define CMU_CLKSTOP_LCD0_SYS_PWR_REG       0x1150
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#define CMU_CLKSTOP_LCD1_SYS_PWR_REG       0x1154
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#define CMU_CLKSTOP_MAUDIO_SYS_PWR_REG     0x1158
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#define CMU_CLKSTOP_GPS_SYS_PWR_REG        0x115C
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#define CMU_RESET_CAM_SYS_PWR_REG          0x1160
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#define CMU_RESET_TV_SYS_PWR_REG           0x1164
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#define CMU_RESET_MFC_SYS_PWR_REG          0x1168
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#define CMU_RESET_G3D_SYS_PWR_REG          0x116C
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#define CMU_RESET_LCD0_SYS_PWR_REG         0x1170
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#define CMU_RESET_LCD1_SYS_PWR_REG         0x1174
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#define CMU_RESET_MAUDIO_SYS_PWR_REG       0x1178
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#define CMU_RESET_GPS_SYS_PWR_REG          0x117C
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#define TOP_BUS_SYS_PWR_REG                0x1180
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#define TOP_RETENTION_SYS_PWR_REG          0x1184
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#define TOP_PWR_SYS_PWR_REG                0x1188
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#define LOGIC_RESET_SYS_PWR_REG            0x11A0
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#define OneNANDXL_MEM_SYS_PWR_REG          0x11C0
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#define MODEMIF_MEM_SYS_PWR_REG            0x11C4
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#define USBDEVICE_MEM_SYS_PWR_REG          0x11CC
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#define SDMMC_MEM_SYS_PWR_REG              0x11D0
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#define CSSYS_MEM_SYS_PWR_REG              0x11D4
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#define SECSS_MEM_SYS_PWR_REG              0x11D8
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#define PCIe_MEM_SYS_PWR_REG               0x11E0
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#define SATA_MEM_SYS_PWR_REG               0x11E4
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#define PAD_RETENTION_DRAM_SYS_PWR_REG     0x1200
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#define PAD_RETENTION_MAUDIO_SYS_PWR_REG   0x1204
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#define PAD_RETENTION_GPIO_SYS_PWR_REG     0x1220
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#define PAD_RETENTION_UART_SYS_PWR_REG     0x1224
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#define PAD_RETENTION_MMCA_SYS_PWR_REG     0x1228
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#define PAD_RETENTION_MMCB_SYS_PWR_REG     0x122C
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#define PAD_RETENTION_EBIA_SYS_PWR_REG     0x1230
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#define PAD_RETENTION_EBIB_SYS_PWR_REG     0x1234
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#define PAD_ISOLATION_SYS_PWR_REG          0x1240
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#define PAD_ALV_SEL_SYS_PWR_REG            0x1260
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#define XUSBXTI_SYS_PWR_REG                0x1280
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#define XXTI_SYS_PWR_REG                   0x1284
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#define EXT_REGULATOR_SYS_PWR_REG          0x12C0
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#define GPIO_MODE_SYS_PWR_REG              0x1300
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#define GPIO_MODE_MAUDIO_SYS_PWR_REG       0x1340
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#define CAM_SYS_PWR_REG                    0x1380
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#define TV_SYS_PWR_REG                     0x1384
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#define MFC_SYS_PWR_REG                    0x1388
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#define G3D_SYS_PWR_REG                    0x138C
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#define LCD0_SYS_PWR_REG                   0x1390
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#define LCD1_SYS_PWR_REG                   0x1394
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#define MAUDIO_SYS_PWR_REG                 0x1398
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#define GPS_SYS_PWR_REG                    0x139C
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#define GPS_ALIVE_SYS_PWR_REG              0x13A0
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#define ARM_CORE0_CONFIGURATION 0x2000 /* Configure power mode of ARM_CORE0 */
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#define ARM_CORE0_STATUS        0x2004 /* Check power mode of ARM_CORE0 */
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#define ARM_CORE0_OPTION        0x2008 /* Sets control options for ARM_CORE0 */
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#define ARM_CORE1_CONFIGURATION 0x2080 /* Configure power mode of ARM_CORE1 */
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#define ARM_CORE1_STATUS        0x2084 /* Check power mode of ARM_CORE1 */
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#define ARM_CORE1_OPTION        0x2088 /* Sets control options for ARM_CORE0 */
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#define ARM_COMMON_OPTION       0x2408 /* Sets control options for ARM_COMMON */
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/* Configure power mode of ARM_CPU_L2_0 */
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#define ARM_CPU_L2_0_CONFIGURATION 0x2600
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#define ARM_CPU_L2_0_STATUS        0x2604 /* Check power mode of ARM_CPU_L2_0 */
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/* Configure power mode of ARM_CPU_L2_1 */
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#define ARM_CPU_L2_1_CONFIGURATION 0x2620
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#define ARM_CPU_L2_1_STATUS        0x2624 /* Check power mode of ARM_CPU_L2_1 */
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/* Sets control options for PAD_RETENTION_MAUDIO */
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#define PAD_RETENTION_MAUDIO_OPTION 0x3028
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/* Sets control options for PAD_RETENTION_GPIO */
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#define PAD_RETENTION_GPIO_OPTION   0x3108
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/* Sets control options for PAD_RETENTION_UART */
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#define PAD_RETENTION_UART_OPTION   0x3128
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/* Sets control options for PAD_RETENTION_MMCA */
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#define PAD_RETENTION_MMCA_OPTION   0x3148
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/* Sets control options for PAD_RETENTION_MMCB */
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#define PAD_RETENTION_MMCB_OPTION   0x3168
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/* Sets control options for PAD_RETENTION_EBIA */
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#define PAD_RETENTION_EBIA_OPTION   0x3188
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/* Sets control options for PAD_RETENTION_EBIB */
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#define PAD_RETENTION_EBIB_OPTION   0x31A8
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#define PS_HOLD_CONTROL         0x330C /* PS_HOLD control register */
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#define XUSBXTI_CONFIGURATION   0x3400 /* Configure the pad of XUSBXTI */
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#define XUSBXTI_STATUS          0x3404 /* Check the pad of XUSBXTI */
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/* Sets time required for XUSBXTI to be stabilized */
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#define XUSBXTI_DURATION        0x341C
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#define XXTI_CONFIGURATION      0x3420 /* Configure the pad of XXTI */
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#define XXTI_STATUS             0x3424 /* Check the pad of XXTI */
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/* Sets time required for XXTI to be stabilized */
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#define XXTI_DURATION           0x343C
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/* Sets time required for EXT_REGULATOR to be stabilized */
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#define EXT_REGULATOR_DURATION  0x361C
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#define CAM_CONFIGURATION       0x3C00 /* Configure power mode of CAM */
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#define CAM_STATUS              0x3C04 /* Check power mode of CAM */
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#define CAM_OPTION              0x3C08 /* Sets control options for CAM */
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#define TV_CONFIGURATION        0x3C20 /* Configure power mode of TV */
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#define TV_STATUS               0x3C24 /* Check power mode of TV */
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#define TV_OPTION               0x3C28 /* Sets control options for TV */
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#define MFC_CONFIGURATION       0x3C40 /* Configure power mode of MFC */
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#define MFC_STATUS              0x3C44 /* Check power mode of MFC */
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#define MFC_OPTION              0x3C48 /* Sets control options for MFC */
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#define G3D_CONFIGURATION       0x3C60 /* Configure power mode of G3D */
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#define G3D_STATUS              0x3C64 /* Check power mode of G3D */
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#define G3D_OPTION              0x3C68 /* Sets control options for G3D */
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#define LCD0_CONFIGURATION      0x3C80 /* Configure power mode of LCD0 */
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#define LCD0_STATUS             0x3C84 /* Check power mode of LCD0 */
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#define LCD0_OPTION             0x3C88 /* Sets control options for LCD0 */
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#define LCD1_CONFIGURATION      0x3CA0 /* Configure power mode of LCD1 */
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#define LCD1_STATUS             0x3CA4 /* Check power mode of LCD1 */
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#define LCD1_OPTION             0x3CA8 /* Sets control options for LCD1 */
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#define GPS_CONFIGURATION       0x3CE0 /* Configure power mode of GPS */
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#define GPS_STATUS              0x3CE4 /* Check power mode of GPS */
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#define GPS_OPTION              0x3CE8 /* Sets control options for GPS */
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#define GPS_ALIVE_CONFIGURATION 0x3D00 /* Configure power mode of GPS */
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#define GPS_ALIVE_STATUS        0x3D04 /* Check power mode of GPS */
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#define GPS_ALIVE_OPTION        0x3D08 /* Sets control options for GPS */
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#define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c
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typedef struct Exynos4210PmuReg {
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    const char  *name; /* for debug only */
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    uint32_t     offset;
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    uint32_t     reset_value;
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} Exynos4210PmuReg;
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static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
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    {"OM_STAT", OM_STAT, 0x00000000},
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    {"RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000},
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    {"GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001},
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    {"SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000},
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    {"SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000},
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    {"SWRESET", SWRESET, 0x00000000},
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    {"RST_STAT", RST_STAT, 0x00000000},
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    {"WAKEUP_STAT", WAKEUP_STAT, 0x00000000},
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    {"EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000},
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    {"WAKEUP_MASK", WAKEUP_MASK, 0x00000000},
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    {"HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000},
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    {"USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000},
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    {"USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000},
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    {"DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000},
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    {"MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000},
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    {"MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000},
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    {"ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001},
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    {"PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000},
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    {"SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000},
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    {"INFORM0", INFORM0, 0x00000000},
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    {"INFORM1", INFORM1, 0x00000000},
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    {"INFORM2", INFORM2, 0x00000000},
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    {"INFORM3", INFORM3, 0x00000000},
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    {"INFORM4", INFORM4, 0x00000000},
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    {"INFORM5", INFORM5, 0x00000000},
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    {"INFORM6", INFORM6, 0x00000000},
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    {"INFORM7", INFORM7, 0x00000000},
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    {"PMU_DEBUG", PMU_DEBUG, 0x00000000},
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    {"ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF},
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    {"ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF},
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    {"ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF},
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    {"ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF},
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    {"ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF},
267
    {"CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
268
    {"CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
269
    {"CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF},
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    {"APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
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    {"MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
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    {"VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
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    {"EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
274
    {"CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG,
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            0xFFFFFFFF},
276
    {"CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG,
277
            0xFFFFFFFF},
278
    {"CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF},
279
    {"CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF},
280
    {"CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF},
281
    {"CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF},
282
    {"CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
283
    {"CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
284
    {"CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,
285
            0xFFFFFFFF},
286
    {"CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF},
287
    {"CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF},
288
    {"CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF},
289
    {"CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF},
290
    {"CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF},
291
    {"CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
292
    {"CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
293
    {"CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
294
    {"CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF},
295
    {"TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF},
296
    {"TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF},
297
    {"TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF},
298
    {"LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF},
299
    {"OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF},
300
    {"MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF},
301
    {"USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF},
302
    {"SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF},
303
    {"CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
304
    {"SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
305
    {"PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF},
306
    {"SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF},
307
    {"PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG,
308
            0xFFFFFFFF},
309
    {"PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG,
310
            0xFFFFFFFF},
311
    {"PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG,
312
            0xFFFFFFFF},
313
    {"PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG,
314
            0xFFFFFFFF},
315
    {"PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG,
316
            0xFFFFFFFF},
317
    {"PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG,
318
            0xFFFFFFFF},
319
    {"PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG,
320
            0xFFFFFFFF},
321
    {"PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG,
322
            0xFFFFFFFF},
323
    {"PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF},
324
    {"PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF},
325
    {"XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF},
326
    {"XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF},
327
    {"EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF},
328
    {"GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF},
329
    {"GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
330
    {"CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF},
331
    {"TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF},
332
    {"MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF},
333
    {"G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF},
334
    {"LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF},
335
    {"LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF},
336
    {"MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
337
    {"GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF},
338
    {"GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF},
339
    {"ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003},
340
    {"ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003},
341
    {"ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001},
342
    {"ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003},
343
    {"ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003},
344
    {"ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001},
345
    {"ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001},
346
    {"ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003},
347
    {"ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003},
348
    {"ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003},
349
    {"ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003},
350
    {"PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000},
351
    {"PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000},
352
    {"PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000},
353
    {"PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000},
354
    {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000},
355
    {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000},
356
    {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000},
357
    /*
358
     * PS_HOLD_CONTROL: reset value and manually toggle high the DATA bit.
359
     * DATA bit high, set usually by bootloader, keeps system on.
360
     */
361
    {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200 | BIT(8)},
362
    {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001},
363
    {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001},
364
    {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000},
365
    {"XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001},
366
    {"XXTI_STATUS", XXTI_STATUS, 0x00000001},
367
    {"XXTI_DURATION", XXTI_DURATION, 0xFFF00000},
368
    {"EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF},
369
    {"CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007},
370
    {"CAM_STATUS", CAM_STATUS, 0x00060007},
371
    {"CAM_OPTION", CAM_OPTION, 0x00000001},
372
    {"TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007},
373
    {"TV_STATUS", TV_STATUS, 0x00060007},
374
    {"TV_OPTION", TV_OPTION, 0x00000001},
375
    {"MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007},
376
    {"MFC_STATUS", MFC_STATUS, 0x00060007},
377
    {"MFC_OPTION", MFC_OPTION, 0x00000001},
378
    {"G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007},
379
    {"G3D_STATUS", G3D_STATUS, 0x00060007},
380
    {"G3D_OPTION", G3D_OPTION, 0x00000001},
381
    {"LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007},
382
    {"LCD0_STATUS", LCD0_STATUS, 0x00060007},
383
    {"LCD0_OPTION", LCD0_OPTION, 0x00000001},
384
    {"LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007},
385
    {"LCD1_STATUS", LCD1_STATUS, 0x00060007},
386
    {"LCD1_OPTION", LCD1_OPTION, 0x00000001},
387
    {"GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007},
388
    {"GPS_STATUS", GPS_STATUS, 0x00060007},
389
    {"GPS_OPTION", GPS_OPTION, 0x00000001},
390
    {"GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007},
391
    {"GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007},
392
    {"GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001},
393
};
394

395
#define PMU_NUM_OF_REGISTERS ARRAY_SIZE(exynos4210_pmu_regs)
396

397
#define TYPE_EXYNOS4210_PMU "exynos4210.pmu"
398
OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210PmuState, EXYNOS4210_PMU)
399

400
struct Exynos4210PmuState {
401
    SysBusDevice parent_obj;
402

403
    MemoryRegion iomem;
404
    uint32_t reg[PMU_NUM_OF_REGISTERS];
405
};
406

407
static void exynos4210_pmu_poweroff(void)
408
{
409
    PRINT_DEBUG("QEMU PMU: PS_HOLD bit down, powering off\n");
410
    qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
411
}
412

413
static uint64_t exynos4210_pmu_read(void *opaque, hwaddr offset,
414
                                    unsigned size)
415
{
416
    Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
417
    const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
418
    unsigned int i;
419

420
    for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
421
        if (reg_p->offset == offset) {
422
            PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name,
423
                                   (uint32_t)offset, s->reg[i]);
424
            return s->reg[i];
425
        }
426
        reg_p++;
427
    }
428
    PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset);
429
    return 0;
430
}
431

432
static void exynos4210_pmu_write(void *opaque, hwaddr offset,
433
                                 uint64_t val, unsigned size)
434
{
435
    Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
436
    const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
437
    unsigned int i;
438

439
    for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
440
        if (reg_p->offset == offset) {
441
            PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
442
                    (uint32_t)offset, (uint32_t)val);
443
            s->reg[i] = val;
444
            if ((offset == PS_HOLD_CONTROL) && ((val & BIT(8)) == 0)) {
445
                /*
446
                 * We are interested only in setting data bit
447
                 * of PS_HOLD_CONTROL register to indicate power off request.
448
                 */
449
                exynos4210_pmu_poweroff();
450
            }
451
            return;
452
        }
453
        reg_p++;
454
    }
455
    PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset);
456
}
457

458
static const MemoryRegionOps exynos4210_pmu_ops = {
459
    .read = exynos4210_pmu_read,
460
    .write = exynos4210_pmu_write,
461
    .endianness = DEVICE_NATIVE_ENDIAN,
462
    .valid = {
463
        .min_access_size = 4,
464
        .max_access_size = 4,
465
        .unaligned = false
466
    }
467
};
468

469
static void exynos4210_pmu_reset(DeviceState *dev)
470
{
471
    Exynos4210PmuState *s = EXYNOS4210_PMU(dev);
472
    unsigned i;
473

474
    /* Set default values for registers */
475
    for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) {
476
        s->reg[i] = exynos4210_pmu_regs[i].reset_value;
477
    }
478
}
479

480
static void exynos4210_pmu_init(Object *obj)
481
{
482
    Exynos4210PmuState *s = EXYNOS4210_PMU(obj);
483
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
484

485
    /* memory mapping */
486
    memory_region_init_io(&s->iomem, obj, &exynos4210_pmu_ops, s,
487
                          "exynos4210.pmu", EXYNOS4210_PMU_REGS_MEM_SIZE);
488
    sysbus_init_mmio(dev, &s->iomem);
489
}
490

491
static const VMStateDescription exynos4210_pmu_vmstate = {
492
    .name = "exynos4210.pmu",
493
    .version_id = 1,
494
    .minimum_version_id = 1,
495
    .fields = (const VMStateField[]) {
496
        VMSTATE_UINT32_ARRAY(reg, Exynos4210PmuState, PMU_NUM_OF_REGISTERS),
497
        VMSTATE_END_OF_LIST()
498
    }
499
};
500

501
static void exynos4210_pmu_class_init(ObjectClass *klass, void *data)
502
{
503
    DeviceClass *dc = DEVICE_CLASS(klass);
504

505
    dc->reset = exynos4210_pmu_reset;
506
    dc->vmsd = &exynos4210_pmu_vmstate;
507
}
508

509
static const TypeInfo exynos4210_pmu_info = {
510
    .name          = TYPE_EXYNOS4210_PMU,
511
    .parent        = TYPE_SYS_BUS_DEVICE,
512
    .instance_size = sizeof(Exynos4210PmuState),
513
    .instance_init = exynos4210_pmu_init,
514
    .class_init    = exynos4210_pmu_class_init,
515
};
516

517
static void exynos4210_pmu_register(void)
518
{
519
    type_register_static(&exynos4210_pmu_info);
520
}
521

522
type_init(exynos4210_pmu_register)
523