qemu

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/*
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 * QEMU Sparc Sun4m ECC memory controller emulation
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 *
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 * Copyright (c) 2007 Robert Reif
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "trace.h"
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#include "qom/object.h"
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/* There are 3 versions of this chip used in SMP sun4m systems:
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 * MCC (version 0, implementation 0) SS-600MP
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 * EMC (version 0, implementation 1) SS-10
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 * SMC (version 0, implementation 2) SS-10SX and SS-20
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 *
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 * Chipset docs:
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 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
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 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
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 */
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#define ECC_MCC        0x00000000
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#define ECC_EMC        0x10000000
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#define ECC_SMC        0x20000000
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/* Register indexes */
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#define ECC_MER        0               /* Memory Enable Register */
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#define ECC_MDR        1               /* Memory Delay Register */
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#define ECC_MFSR       2               /* Memory Fault Status Register */
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#define ECC_VCR        3               /* Video Configuration Register */
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#define ECC_MFAR0      4               /* Memory Fault Address Register 0 */
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#define ECC_MFAR1      5               /* Memory Fault Address Register 1 */
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#define ECC_DR         6               /* Diagnostic Register */
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#define ECC_ECR0       7               /* Event Count Register 0 */
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#define ECC_ECR1       8               /* Event Count Register 1 */
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/* ECC fault control register */
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#define ECC_MER_EE     0x00000001      /* Enable ECC checking */
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#define ECC_MER_EI     0x00000002      /* Enable Interrupts on
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                                          correctable errors */
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#define ECC_MER_MRR0   0x00000004      /* SIMM 0 */
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#define ECC_MER_MRR1   0x00000008      /* SIMM 1 */
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#define ECC_MER_MRR2   0x00000010      /* SIMM 2 */
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#define ECC_MER_MRR3   0x00000020      /* SIMM 3 */
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#define ECC_MER_MRR4   0x00000040      /* SIMM 4 */
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#define ECC_MER_MRR5   0x00000080      /* SIMM 5 */
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#define ECC_MER_MRR6   0x00000100      /* SIMM 6 */
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#define ECC_MER_MRR7   0x00000200      /* SIMM 7 */
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#define ECC_MER_REU    0x00000100      /* Memory Refresh Enable (600MP) */
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#define ECC_MER_MRR    0x000003fc      /* MRR mask */
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#define ECC_MER_A      0x00000400      /* Memory controller addr map select */
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#define ECC_MER_DCI    0x00000800      /* Disables Coherent Invalidate ACK */
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#define ECC_MER_VER    0x0f000000      /* Version */
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#define ECC_MER_IMPL   0xf0000000      /* Implementation */
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#define ECC_MER_MASK_0 0x00000103      /* Version 0 (MCC) mask */
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#define ECC_MER_MASK_1 0x00000bff      /* Version 1 (EMC) mask */
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#define ECC_MER_MASK_2 0x00000bff      /* Version 2 (SMC) mask */
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/* ECC memory delay register */
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#define ECC_MDR_RRI    0x000003ff      /* Refresh Request Interval */
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#define ECC_MDR_MI     0x00001c00      /* MIH Delay */
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#define ECC_MDR_CI     0x0000e000      /* Coherent Invalidate Delay */
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#define ECC_MDR_MDL    0x001f0000      /* MBus Master arbitration delay */
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#define ECC_MDR_MDH    0x03e00000      /* MBus Master arbitration delay */
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#define ECC_MDR_GAD    0x7c000000      /* Graphics Arbitration Delay */
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#define ECC_MDR_RSC    0x80000000      /* Refresh load control */
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#define ECC_MDR_MASK   0x7fffffff
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/* ECC fault status register */
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#define ECC_MFSR_CE    0x00000001      /* Correctable error */
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#define ECC_MFSR_BS    0x00000002      /* C2 graphics bad slot access */
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#define ECC_MFSR_TO    0x00000004      /* Timeout on write */
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#define ECC_MFSR_UE    0x00000008      /* Uncorrectable error */
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#define ECC_MFSR_DW    0x000000f0      /* Index of double word in block */
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#define ECC_MFSR_SYND  0x0000ff00      /* Syndrome for correctable error */
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#define ECC_MFSR_ME    0x00010000      /* Multiple errors */
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#define ECC_MFSR_C2ERR 0x00020000      /* C2 graphics error */
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/* ECC fault address register 0 */
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#define ECC_MFAR0_PADDR 0x0000000f     /* PA[32-35] */
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#define ECC_MFAR0_TYPE  0x000000f0     /* Transaction type */
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#define ECC_MFAR0_SIZE  0x00000700     /* Transaction size */
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#define ECC_MFAR0_CACHE 0x00000800     /* Mapped cacheable */
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#define ECC_MFAR0_LOCK  0x00001000     /* Error occurred in atomic cycle */
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#define ECC_MFAR0_BMODE 0x00002000     /* Boot mode */
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#define ECC_MFAR0_VADDR 0x003fc000     /* VA[12-19] (superset bits) */
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#define ECC_MFAR0_S     0x08000000     /* Supervisor mode */
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#define ECC_MFARO_MID   0xf0000000     /* Module ID */
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/* ECC diagnostic register */
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#define ECC_DR_CBX     0x00000001
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#define ECC_DR_CB0     0x00000002
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#define ECC_DR_CB1     0x00000004
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#define ECC_DR_CB2     0x00000008
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#define ECC_DR_CB4     0x00000010
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#define ECC_DR_CB8     0x00000020
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#define ECC_DR_CB16    0x00000040
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#define ECC_DR_CB32    0x00000080
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#define ECC_DR_DMODE   0x00000c00
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#define ECC_NREGS      9
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#define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))
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#define ECC_DIAG_SIZE  4
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#define ECC_DIAG_MASK  (ECC_DIAG_SIZE - 1)
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#define TYPE_ECC_MEMCTL "eccmemctl"
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OBJECT_DECLARE_SIMPLE_TYPE(ECCState, ECC_MEMCTL)
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struct ECCState {
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    SysBusDevice parent_obj;
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    MemoryRegion iomem, iomem_diag;
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    qemu_irq irq;
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    uint32_t regs[ECC_NREGS];
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    uint8_t diag[ECC_DIAG_SIZE];
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    uint32_t version;
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};
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static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val,
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                          unsigned size)
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{
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    ECCState *s = opaque;
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    switch (addr >> 2) {
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    case ECC_MER:
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        if (s->version == ECC_MCC)
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            s->regs[ECC_MER] = (val & ECC_MER_MASK_0);
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        else if (s->version == ECC_EMC)
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            s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1);
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        else if (s->version == ECC_SMC)
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            s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2);
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        trace_ecc_mem_writel_mer(val);
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        break;
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    case ECC_MDR:
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        s->regs[ECC_MDR] =  val & ECC_MDR_MASK;
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        trace_ecc_mem_writel_mdr(val);
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        break;
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    case ECC_MFSR:
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        s->regs[ECC_MFSR] =  val;
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        qemu_irq_lower(s->irq);
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        trace_ecc_mem_writel_mfsr(val);
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        break;
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    case ECC_VCR:
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        s->regs[ECC_VCR] =  val;
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        trace_ecc_mem_writel_vcr(val);
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        break;
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    case ECC_DR:
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        s->regs[ECC_DR] =  val;
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        trace_ecc_mem_writel_dr(val);
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        break;
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    case ECC_ECR0:
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        s->regs[ECC_ECR0] =  val;
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        trace_ecc_mem_writel_ecr0(val);
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        break;
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    case ECC_ECR1:
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        s->regs[ECC_ECR0] =  val;
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        trace_ecc_mem_writel_ecr1(val);
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        break;
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    }
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}
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static uint64_t ecc_mem_read(void *opaque, hwaddr addr,
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                             unsigned size)
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{
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    ECCState *s = opaque;
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    uint32_t ret = 0;
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    switch (addr >> 2) {
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    case ECC_MER:
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        ret = s->regs[ECC_MER];
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        trace_ecc_mem_readl_mer(ret);
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        break;
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    case ECC_MDR:
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        ret = s->regs[ECC_MDR];
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        trace_ecc_mem_readl_mdr(ret);
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        break;
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    case ECC_MFSR:
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        ret = s->regs[ECC_MFSR];
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        trace_ecc_mem_readl_mfsr(ret);
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        break;
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    case ECC_VCR:
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        ret = s->regs[ECC_VCR];
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        trace_ecc_mem_readl_vcr(ret);
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        break;
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    case ECC_MFAR0:
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        ret = s->regs[ECC_MFAR0];
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        trace_ecc_mem_readl_mfar0(ret);
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        break;
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    case ECC_MFAR1:
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        ret = s->regs[ECC_MFAR1];
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        trace_ecc_mem_readl_mfar1(ret);
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        break;
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    case ECC_DR:
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        ret = s->regs[ECC_DR];
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        trace_ecc_mem_readl_dr(ret);
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        break;
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    case ECC_ECR0:
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        ret = s->regs[ECC_ECR0];
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        trace_ecc_mem_readl_ecr0(ret);
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        break;
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    case ECC_ECR1:
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        ret = s->regs[ECC_ECR0];
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        trace_ecc_mem_readl_ecr1(ret);
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        break;
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    }
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    return ret;
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}
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static const MemoryRegionOps ecc_mem_ops = {
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    .read = ecc_mem_read,
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    .write = ecc_mem_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    },
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};
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static void ecc_diag_mem_write(void *opaque, hwaddr addr,
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                               uint64_t val, unsigned size)
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{
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    ECCState *s = opaque;
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    trace_ecc_diag_mem_writeb(addr, val);
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    s->diag[addr & ECC_DIAG_MASK] = val;
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}
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static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr,
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                                  unsigned size)
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{
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    ECCState *s = opaque;
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    uint32_t ret = s->diag[(int)addr];
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    trace_ecc_diag_mem_readb(addr, ret);
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    return ret;
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}
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static const MemoryRegionOps ecc_diag_mem_ops = {
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    .read = ecc_diag_mem_read,
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    .write = ecc_diag_mem_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    },
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};
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static const VMStateDescription vmstate_ecc = {
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    .name ="ECC",
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    .version_id = 3,
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    .minimum_version_id = 3,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS),
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        VMSTATE_BUFFER(diag, ECCState),
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        VMSTATE_UINT32(version, ECCState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void ecc_reset(DeviceState *d)
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{
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    ECCState *s = ECC_MEMCTL(d);
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    if (s->version == ECC_MCC) {
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        s->regs[ECC_MER] &= ECC_MER_REU;
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    } else {
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        s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR |
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                             ECC_MER_DCI);
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    }
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    s->regs[ECC_MDR] = 0x20;
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    s->regs[ECC_MFSR] = 0;
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    s->regs[ECC_VCR] = 0;
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    s->regs[ECC_MFAR0] = 0x07c00000;
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    s->regs[ECC_MFAR1] = 0;
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    s->regs[ECC_DR] = 0;
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    s->regs[ECC_ECR0] = 0;
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    s->regs[ECC_ECR1] = 0;
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}
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static void ecc_init(Object *obj)
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{
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    ECCState *s = ECC_MEMCTL(obj);
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    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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    sysbus_init_irq(dev, &s->irq);
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    memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE);
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    sysbus_init_mmio(dev, &s->iomem);
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}
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static void ecc_realize(DeviceState *dev, Error **errp)
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{
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    ECCState *s = ECC_MEMCTL(dev);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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    s->regs[0] = s->version;
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    if (s->version == ECC_MCC) { // SS-600MP only
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        memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s,
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                              "ecc.diag", ECC_DIAG_SIZE);
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        sysbus_init_mmio(sbd, &s->iomem_diag);
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    }
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}
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static Property ecc_properties[] = {
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    DEFINE_PROP_UINT32("version", ECCState, version, -1),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void ecc_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->realize = ecc_realize;
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    dc->reset = ecc_reset;
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    dc->vmsd = &vmstate_ecc;
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    device_class_set_props(dc, ecc_properties);
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}
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static const TypeInfo ecc_info = {
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    .name          = TYPE_ECC_MEMCTL,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(ECCState),
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    .instance_init = ecc_init,
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    .class_init    = ecc_class_init,
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};
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static void ecc_register_types(void)
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{
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    type_register_static(&ecc_info);
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}
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type_init(ecc_register_types)
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