qemu

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/*
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 * AVR Power Reduction Management
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 *
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 * Copyright (c) 2019-2020 Michael Rolnik
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "hw/misc/avr_power.h"
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#include "qemu/log.h"
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#include "hw/qdev-properties.h"
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#include "hw/irq.h"
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#include "trace.h"
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static void avr_mask_reset(DeviceState *dev)
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{
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    AVRMaskState *s = AVR_MASK(dev);
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    s->val = 0x00;
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    for (int i = 0; i < 8; i++) {
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        qemu_set_irq(s->irq[i], 0);
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    }
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}
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static uint64_t avr_mask_read(void *opaque, hwaddr offset, unsigned size)
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{
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    assert(size == 1);
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    assert(offset == 0);
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    AVRMaskState *s = opaque;
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    trace_avr_power_read(s->val);
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    return (uint64_t)s->val;
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}
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static void avr_mask_write(void *opaque, hwaddr offset,
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                           uint64_t val64, unsigned size)
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{
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    assert(size == 1);
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    assert(offset == 0);
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    AVRMaskState *s = opaque;
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    uint8_t val8 = val64;
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    trace_avr_power_write(val8);
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    s->val = val8;
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    for (int i = 0; i < 8; i++) {
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        qemu_set_irq(s->irq[i], (val8 & (1 << i)) != 0);
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    }
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}
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static const MemoryRegionOps avr_mask_ops = {
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    .read = avr_mask_read,
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    .write = avr_mask_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .impl = {
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        .max_access_size = 1,
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    },
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};
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static void avr_mask_init(Object *dev)
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{
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    AVRMaskState *s = AVR_MASK(dev);
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    SysBusDevice *busdev = SYS_BUS_DEVICE(dev);
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    memory_region_init_io(&s->iomem, dev, &avr_mask_ops, s, TYPE_AVR_MASK,
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                          0x01);
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    sysbus_init_mmio(busdev, &s->iomem);
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    for (int i = 0; i < 8; i++) {
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        sysbus_init_irq(busdev, &s->irq[i]);
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    }
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    s->val = 0x00;
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}
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static void avr_mask_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->reset = avr_mask_reset;
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}
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static const TypeInfo avr_mask_info = {
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    .name          = TYPE_AVR_MASK,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(AVRMaskState),
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    .class_init    = avr_mask_class_init,
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    .instance_init = avr_mask_init,
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};
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static void avr_mask_register_types(void)
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{
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    type_register_static(&avr_mask_info);
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}
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type_init(avr_mask_register_types)
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