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qemu
/hw
/misc
/
aspeed_xdma.c 
245 строк · 7.4 Кб
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/*
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 * ASPEED XDMA Controller
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 * Eddie James <eajames@linux.ibm.com>
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 *
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 * Copyright (C) 2019 IBM Corp
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/irq.h"
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#include "hw/misc/aspeed_xdma.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "trace.h"
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#define XDMA_BMC_CMDQ_ADDR         0x10
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#define XDMA_BMC_CMDQ_ENDP         0x14
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#define XDMA_BMC_CMDQ_WRP          0x18
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#define  XDMA_BMC_CMDQ_W_MASK      0x0003FFFF
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#define XDMA_BMC_CMDQ_RDP          0x1C
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#define  XDMA_BMC_CMDQ_RDP_MAGIC   0xEE882266
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#define XDMA_IRQ_ENG_CTRL          0x20
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#define  XDMA_IRQ_ENG_CTRL_US_COMP BIT(4)
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#define  XDMA_IRQ_ENG_CTRL_DS_COMP BIT(5)
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#define  XDMA_IRQ_ENG_CTRL_W_MASK  0xBFEFF07F
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#define XDMA_IRQ_ENG_STAT          0x24
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#define  XDMA_IRQ_ENG_STAT_US_COMP BIT(4)
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#define  XDMA_IRQ_ENG_STAT_DS_COMP BIT(5)
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#define  XDMA_IRQ_ENG_STAT_RESET   0xF8000000
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#define XDMA_AST2600_BMC_CMDQ_ADDR   0x14
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#define XDMA_AST2600_BMC_CMDQ_ENDP   0x18
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#define XDMA_AST2600_BMC_CMDQ_WRP    0x1c
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#define XDMA_AST2600_BMC_CMDQ_RDP    0x20
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#define XDMA_AST2600_IRQ_CTRL        0x38
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#define  XDMA_AST2600_IRQ_CTRL_US_COMP    BIT(16)
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#define  XDMA_AST2600_IRQ_CTRL_DS_COMP    BIT(17)
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#define  XDMA_AST2600_IRQ_CTRL_W_MASK     0x017003FF
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#define XDMA_AST2600_IRQ_STATUS      0x3c
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#define  XDMA_AST2600_IRQ_STATUS_US_COMP  BIT(16)
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#define  XDMA_AST2600_IRQ_STATUS_DS_COMP  BIT(17)
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#define XDMA_MEM_SIZE              0x1000
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#define TO_REG(addr) ((addr) / sizeof(uint32_t))
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static uint64_t aspeed_xdma_read(void *opaque, hwaddr addr, unsigned int size)
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{
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    uint32_t val = 0;
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    AspeedXDMAState *xdma = opaque;
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    if (addr < ASPEED_XDMA_REG_SIZE) {
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        val = xdma->regs[TO_REG(addr)];
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    }
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    return (uint64_t)val;
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}
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static void aspeed_xdma_write(void *opaque, hwaddr addr, uint64_t val,
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                              unsigned int size)
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{
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    unsigned int idx;
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    uint32_t val32 = (uint32_t)val;
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    AspeedXDMAState *xdma = opaque;
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    AspeedXDMAClass *axc = ASPEED_XDMA_GET_CLASS(xdma);
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    if (addr >= ASPEED_XDMA_REG_SIZE) {
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        return;
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    }
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    if (addr == axc->cmdq_endp) {
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        xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK;
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    } else if (addr == axc->cmdq_wrp) {
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        idx = TO_REG(addr);
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        xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK;
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        xdma->regs[TO_REG(axc->cmdq_rdp)] = xdma->regs[idx];
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        trace_aspeed_xdma_write(addr, val);
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        if (xdma->bmc_cmdq_readp_set) {
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            xdma->bmc_cmdq_readp_set = 0;
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        } else {
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            xdma->regs[TO_REG(axc->intr_status)] |= axc->intr_complete;
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            if (xdma->regs[TO_REG(axc->intr_ctrl)] & axc->intr_complete) {
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                qemu_irq_raise(xdma->irq);
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            }
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        }
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    } else if (addr == axc->cmdq_rdp) {
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        trace_aspeed_xdma_write(addr, val);
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        if (val32 == XDMA_BMC_CMDQ_RDP_MAGIC) {
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            xdma->bmc_cmdq_readp_set = 1;
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        }
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    } else if (addr == axc->intr_ctrl) {
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        xdma->regs[TO_REG(addr)] = val32 & axc->intr_ctrl_mask;
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    } else if (addr == axc->intr_status) {
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        trace_aspeed_xdma_write(addr, val);
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        idx = TO_REG(addr);
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        if (val32 & axc->intr_complete) {
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            xdma->regs[idx] &= ~axc->intr_complete;
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            qemu_irq_lower(xdma->irq);
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        }
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    } else {
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        xdma->regs[TO_REG(addr)] = val32;
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    }
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}
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static const MemoryRegionOps aspeed_xdma_ops = {
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    .read = aspeed_xdma_read,
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    .write = aspeed_xdma_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid.min_access_size = 4,
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    .valid.max_access_size = 4,
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};
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static void aspeed_xdma_realize(DeviceState *dev, Error **errp)
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{
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    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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    AspeedXDMAState *xdma = ASPEED_XDMA(dev);
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    sysbus_init_irq(sbd, &xdma->irq);
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    memory_region_init_io(&xdma->iomem, OBJECT(xdma), &aspeed_xdma_ops, xdma,
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                          TYPE_ASPEED_XDMA, XDMA_MEM_SIZE);
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    sysbus_init_mmio(sbd, &xdma->iomem);
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}
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static void aspeed_xdma_reset(DeviceState *dev)
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{
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    AspeedXDMAState *xdma = ASPEED_XDMA(dev);
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    AspeedXDMAClass *axc = ASPEED_XDMA_GET_CLASS(xdma);
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    xdma->bmc_cmdq_readp_set = 0;
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    memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE);
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    xdma->regs[TO_REG(axc->intr_status)] = XDMA_IRQ_ENG_STAT_RESET;
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    qemu_irq_lower(xdma->irq);
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}
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static const VMStateDescription aspeed_xdma_vmstate = {
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    .name = TYPE_ASPEED_XDMA,
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    .version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32_ARRAY(regs, AspeedXDMAState, ASPEED_XDMA_NUM_REGS),
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        VMSTATE_END_OF_LIST(),
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    },
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};
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static void aspeed_2600_xdma_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    AspeedXDMAClass *axc = ASPEED_XDMA_CLASS(klass);
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    dc->desc = "ASPEED 2600 XDMA Controller";
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    axc->cmdq_endp = XDMA_AST2600_BMC_CMDQ_ENDP;
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    axc->cmdq_wrp = XDMA_AST2600_BMC_CMDQ_WRP;
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    axc->cmdq_rdp = XDMA_AST2600_BMC_CMDQ_RDP;
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    axc->intr_ctrl = XDMA_AST2600_IRQ_CTRL;
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    axc->intr_ctrl_mask = XDMA_AST2600_IRQ_CTRL_W_MASK;
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    axc->intr_status = XDMA_AST2600_IRQ_STATUS;
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    axc->intr_complete = XDMA_AST2600_IRQ_STATUS_US_COMP |
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        XDMA_AST2600_IRQ_STATUS_DS_COMP;
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}
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static const TypeInfo aspeed_2600_xdma_info = {
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    .name = TYPE_ASPEED_2600_XDMA,
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    .parent = TYPE_ASPEED_XDMA,
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    .class_init = aspeed_2600_xdma_class_init,
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};
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static void aspeed_2500_xdma_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    AspeedXDMAClass *axc = ASPEED_XDMA_CLASS(klass);
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    dc->desc = "ASPEED 2500 XDMA Controller";
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    axc->cmdq_endp = XDMA_BMC_CMDQ_ENDP;
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    axc->cmdq_wrp = XDMA_BMC_CMDQ_WRP;
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    axc->cmdq_rdp = XDMA_BMC_CMDQ_RDP;
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    axc->intr_ctrl = XDMA_IRQ_ENG_CTRL;
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    axc->intr_ctrl_mask = XDMA_IRQ_ENG_CTRL_W_MASK;
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    axc->intr_status = XDMA_IRQ_ENG_STAT;
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    axc->intr_complete = XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP;
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};
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static const TypeInfo aspeed_2500_xdma_info = {
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    .name = TYPE_ASPEED_2500_XDMA,
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    .parent = TYPE_ASPEED_XDMA,
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    .class_init = aspeed_2500_xdma_class_init,
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};
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static void aspeed_2400_xdma_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    AspeedXDMAClass *axc = ASPEED_XDMA_CLASS(klass);
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    dc->desc = "ASPEED 2400 XDMA Controller";
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    axc->cmdq_endp = XDMA_BMC_CMDQ_ENDP;
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    axc->cmdq_wrp = XDMA_BMC_CMDQ_WRP;
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    axc->cmdq_rdp = XDMA_BMC_CMDQ_RDP;
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    axc->intr_ctrl = XDMA_IRQ_ENG_CTRL;
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    axc->intr_ctrl_mask = XDMA_IRQ_ENG_CTRL_W_MASK;
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    axc->intr_status = XDMA_IRQ_ENG_STAT;
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    axc->intr_complete = XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP;
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};
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static const TypeInfo aspeed_2400_xdma_info = {
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    .name = TYPE_ASPEED_2400_XDMA,
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    .parent = TYPE_ASPEED_XDMA,
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    .class_init = aspeed_2400_xdma_class_init,
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};
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static void aspeed_xdma_class_init(ObjectClass *classp, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(classp);
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    dc->realize = aspeed_xdma_realize;
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    dc->reset = aspeed_xdma_reset;
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    dc->vmsd = &aspeed_xdma_vmstate;
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}
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static const TypeInfo aspeed_xdma_info = {
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    .name          = TYPE_ASPEED_XDMA,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(AspeedXDMAState),
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    .class_init    = aspeed_xdma_class_init,
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    .class_size    = sizeof(AspeedXDMAClass),
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    .abstract      = true,
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};
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static void aspeed_xdma_register_type(void)
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{
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    type_register_static(&aspeed_xdma_info);
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    type_register_static(&aspeed_2400_xdma_info);
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    type_register_static(&aspeed_2500_xdma_info);
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    type_register_static(&aspeed_2600_xdma_info);
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}
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type_init(aspeed_xdma_register_type);
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