qemu

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/*
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 * Aspeed PECI Controller
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 *
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 * Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com)
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 *
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 * This code is licensed under the GPL version 2 or later. See the COPYING
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 * file in the top-level directory.
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/misc/aspeed_peci.h"
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#include "hw/registerfields.h"
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#include "trace.h"
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#define ASPEED_PECI_CC_RSP_SUCCESS (0x40U)
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/* Command Register */
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REG32(PECI_CMD, 0x08)
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    FIELD(PECI_CMD, FIRE, 0, 1)
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/* Interrupt Control Register */
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REG32(PECI_INT_CTRL, 0x18)
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/* Interrupt Status Register */
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REG32(PECI_INT_STS, 0x1C)
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    FIELD(PECI_INT_STS, CMD_DONE, 0, 1)
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/* Rx/Tx Data Buffer Registers */
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REG32(PECI_WR_DATA0, 0x20)
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REG32(PECI_RD_DATA0, 0x30)
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static void aspeed_peci_raise_interrupt(AspeedPECIState *s, uint32_t status)
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{
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    trace_aspeed_peci_raise_interrupt(s->regs[R_PECI_INT_CTRL], status);
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    s->regs[R_PECI_INT_STS] = s->regs[R_PECI_INT_CTRL] & status;
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    if (!s->regs[R_PECI_INT_STS]) {
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        return;
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    }
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    qemu_irq_raise(s->irq);
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}
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static uint64_t aspeed_peci_read(void *opaque, hwaddr offset, unsigned size)
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{
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    AspeedPECIState *s = ASPEED_PECI(opaque);
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    uint64_t data;
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    if (offset >= ASPEED_PECI_NR_REGS << 2) {
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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        return 0;
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    }
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    data = s->regs[offset >> 2];
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    trace_aspeed_peci_read(offset, data);
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    return data;
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}
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static void aspeed_peci_write(void *opaque, hwaddr offset, uint64_t data,
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                              unsigned size)
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{
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    AspeedPECIState *s = ASPEED_PECI(opaque);
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    trace_aspeed_peci_write(offset, data);
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    if (offset >= ASPEED_PECI_NR_REGS << 2) {
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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        return;
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    }
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    switch (offset) {
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    case A_PECI_INT_STS:
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        s->regs[R_PECI_INT_STS] &= ~data;
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        if (!s->regs[R_PECI_INT_STS]) {
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            qemu_irq_lower(s->irq);
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        }
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        break;
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    case A_PECI_CMD:
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        /*
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         * Only the FIRE bit is writable. Once the command is complete, it
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         * should be cleared. Since we complete the command immediately, the
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         * value is not stored in the register array.
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         */
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        if (!FIELD_EX32(data, PECI_CMD, FIRE)) {
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            break;
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        }
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        if (s->regs[R_PECI_INT_STS]) {
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            qemu_log_mask(LOG_GUEST_ERROR, "%s: Interrupt status must be "
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                          "cleared before firing another command: 0x%08x\n",
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                          __func__, s->regs[R_PECI_INT_STS]);
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            break;
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        }
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        s->regs[R_PECI_RD_DATA0] = ASPEED_PECI_CC_RSP_SUCCESS;
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        s->regs[R_PECI_WR_DATA0] = ASPEED_PECI_CC_RSP_SUCCESS;
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        aspeed_peci_raise_interrupt(s,
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                                    FIELD_DP32(0, PECI_INT_STS, CMD_DONE, 1));
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        break;
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    default:
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        s->regs[offset / sizeof(s->regs[0])] = data;
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        break;
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    }
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}
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static const MemoryRegionOps aspeed_peci_ops = {
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    .read = aspeed_peci_read,
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    .write = aspeed_peci_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void aspeed_peci_realize(DeviceState *dev, Error **errp)
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{
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    AspeedPECIState *s = ASPEED_PECI(dev);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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    memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_peci_ops, s,
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                          TYPE_ASPEED_PECI, 0x1000);
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    sysbus_init_mmio(sbd, &s->mmio);
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    sysbus_init_irq(sbd, &s->irq);
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}
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static void aspeed_peci_reset(DeviceState *dev)
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{
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    AspeedPECIState *s = ASPEED_PECI(dev);
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    memset(s->regs, 0, sizeof(s->regs));
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}
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static void aspeed_peci_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->realize = aspeed_peci_realize;
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    dc->reset = aspeed_peci_reset;
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    dc->desc = "Aspeed PECI Controller";
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}
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static const TypeInfo aspeed_peci_types[] = {
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    {
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        .name = TYPE_ASPEED_PECI,
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        .parent = TYPE_SYS_BUS_DEVICE,
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        .instance_size = sizeof(AspeedPECIState),
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        .class_init = aspeed_peci_class_init,
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        .abstract = false,
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    },
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};
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DEFINE_TYPES(aspeed_peci_types);
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