qemu

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/*
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 * ASPEED I3C Controller
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 *
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 * Copyright (C) 2021 ASPEED Technology Inc.
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 *
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 * This code is licensed under the GPL version 2 or later.  See
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 * the COPYING file in the top-level directory.
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/misc/aspeed_i3c.h"
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#include "hw/registerfields.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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/* I3C Controller Registers */
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REG32(I3C1_REG0, 0x10)
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REG32(I3C1_REG1, 0x14)
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    FIELD(I3C1_REG1, I2C_MODE,  0,  1)
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    FIELD(I3C1_REG1, SA_EN,     15, 1)
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REG32(I3C2_REG0, 0x20)
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REG32(I3C2_REG1, 0x24)
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    FIELD(I3C2_REG1, I2C_MODE,  0,  1)
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    FIELD(I3C2_REG1, SA_EN,     15, 1)
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REG32(I3C3_REG0, 0x30)
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REG32(I3C3_REG1, 0x34)
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    FIELD(I3C3_REG1, I2C_MODE,  0,  1)
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    FIELD(I3C3_REG1, SA_EN,     15, 1)
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REG32(I3C4_REG0, 0x40)
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REG32(I3C4_REG1, 0x44)
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    FIELD(I3C4_REG1, I2C_MODE,  0,  1)
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    FIELD(I3C4_REG1, SA_EN,     15, 1)
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REG32(I3C5_REG0, 0x50)
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REG32(I3C5_REG1, 0x54)
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    FIELD(I3C5_REG1, I2C_MODE,  0,  1)
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    FIELD(I3C5_REG1, SA_EN,     15, 1)
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REG32(I3C6_REG0, 0x60)
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REG32(I3C6_REG1, 0x64)
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    FIELD(I3C6_REG1, I2C_MODE,  0,  1)
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    FIELD(I3C6_REG1, SA_EN,     15, 1)
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/* I3C Device Registers */
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REG32(DEVICE_CTRL,                  0x00)
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REG32(DEVICE_ADDR,                  0x04)
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REG32(HW_CAPABILITY,                0x08)
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REG32(COMMAND_QUEUE_PORT,           0x0c)
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REG32(RESPONSE_QUEUE_PORT,          0x10)
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REG32(RX_TX_DATA_PORT,              0x14)
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REG32(IBI_QUEUE_STATUS,             0x18)
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REG32(IBI_QUEUE_DATA,               0x18)
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REG32(QUEUE_THLD_CTRL,              0x1c)
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REG32(DATA_BUFFER_THLD_CTRL,        0x20)
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REG32(IBI_QUEUE_CTRL,               0x24)
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REG32(IBI_MR_REQ_REJECT,            0x2c)
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REG32(IBI_SIR_REQ_REJECT,           0x30)
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REG32(RESET_CTRL,                   0x34)
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REG32(SLV_EVENT_CTRL,               0x38)
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REG32(INTR_STATUS,                  0x3c)
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REG32(INTR_STATUS_EN,               0x40)
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REG32(INTR_SIGNAL_EN,               0x44)
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REG32(INTR_FORCE,                   0x48)
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REG32(QUEUE_STATUS_LEVEL,           0x4c)
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REG32(DATA_BUFFER_STATUS_LEVEL,     0x50)
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REG32(PRESENT_STATE,                0x54)
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REG32(CCC_DEVICE_STATUS,            0x58)
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REG32(DEVICE_ADDR_TABLE_POINTER,    0x5c)
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    FIELD(DEVICE_ADDR_TABLE_POINTER, DEPTH, 16, 16)
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    FIELD(DEVICE_ADDR_TABLE_POINTER, ADDR,  0,  16)
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REG32(DEV_CHAR_TABLE_POINTER,       0x60)
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REG32(VENDOR_SPECIFIC_REG_POINTER,  0x6c)
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REG32(SLV_MIPI_PID_VALUE,           0x70)
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REG32(SLV_PID_VALUE,                0x74)
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REG32(SLV_CHAR_CTRL,                0x78)
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REG32(SLV_MAX_LEN,                  0x7c)
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REG32(MAX_READ_TURNAROUND,          0x80)
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REG32(MAX_DATA_SPEED,               0x84)
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REG32(SLV_DEBUG_STATUS,             0x88)
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REG32(SLV_INTR_REQ,                 0x8c)
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REG32(DEVICE_CTRL_EXTENDED,         0xb0)
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REG32(SCL_I3C_OD_TIMING,            0xb4)
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REG32(SCL_I3C_PP_TIMING,            0xb8)
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REG32(SCL_I2C_FM_TIMING,            0xbc)
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REG32(SCL_I2C_FMP_TIMING,           0xc0)
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REG32(SCL_EXT_LCNT_TIMING,          0xc8)
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REG32(SCL_EXT_TERMN_LCNT_TIMING,    0xcc)
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REG32(BUS_FREE_TIMING,              0xd4)
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REG32(BUS_IDLE_TIMING,              0xd8)
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REG32(I3C_VER_ID,                   0xe0)
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REG32(I3C_VER_TYPE,                 0xe4)
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REG32(EXTENDED_CAPABILITY,          0xe8)
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REG32(SLAVE_CONFIG,                 0xec)
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static const uint32_t ast2600_i3c_device_resets[ASPEED_I3C_DEVICE_NR_REGS] = {
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    [R_HW_CAPABILITY]               = 0x000e00bf,
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    [R_QUEUE_THLD_CTRL]             = 0x01000101,
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    [R_I3C_VER_ID]                  = 0x3130302a,
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    [R_I3C_VER_TYPE]                = 0x6c633033,
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    [R_DEVICE_ADDR_TABLE_POINTER]   = 0x00080280,
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    [R_DEV_CHAR_TABLE_POINTER]      = 0x00020200,
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    [A_VENDOR_SPECIFIC_REG_POINTER] = 0x000000b0,
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    [R_SLV_MAX_LEN]                 = 0x00ff00ff,
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};
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static uint64_t aspeed_i3c_device_read(void *opaque, hwaddr offset,
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                                       unsigned size)
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{
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    AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque);
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    uint32_t addr = offset >> 2;
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    uint64_t value;
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    switch (addr) {
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    case R_COMMAND_QUEUE_PORT:
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        value = 0;
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        break;
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    default:
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        value = s->regs[addr];
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        break;
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    }
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    trace_aspeed_i3c_device_read(s->id, offset, value);
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    return value;
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}
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static void aspeed_i3c_device_write(void *opaque, hwaddr offset,
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                                    uint64_t value, unsigned size)
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{
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    AspeedI3CDevice *s = ASPEED_I3C_DEVICE(opaque);
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    uint32_t addr = offset >> 2;
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    trace_aspeed_i3c_device_write(s->id, offset, value);
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    switch (addr) {
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    case R_HW_CAPABILITY:
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    case R_RESPONSE_QUEUE_PORT:
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    case R_IBI_QUEUE_DATA:
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    case R_QUEUE_STATUS_LEVEL:
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    case R_PRESENT_STATE:
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    case R_CCC_DEVICE_STATUS:
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    case R_DEVICE_ADDR_TABLE_POINTER:
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    case R_VENDOR_SPECIFIC_REG_POINTER:
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    case R_SLV_CHAR_CTRL:
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    case R_SLV_MAX_LEN:
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    case R_MAX_READ_TURNAROUND:
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    case R_I3C_VER_ID:
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    case R_I3C_VER_TYPE:
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    case R_EXTENDED_CAPABILITY:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: write to readonly register[0x%02" HWADDR_PRIx
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                      "] = 0x%08" PRIx64 "\n",
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                      __func__, offset, value);
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        break;
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    case R_RX_TX_DATA_PORT:
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        break;
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    case R_RESET_CTRL:
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        break;
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    default:
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        s->regs[addr] = value;
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        break;
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    }
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}
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static const VMStateDescription aspeed_i3c_device_vmstate = {
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    .name = TYPE_ASPEED_I3C,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]){
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        VMSTATE_UINT32_ARRAY(regs, AspeedI3CDevice, ASPEED_I3C_DEVICE_NR_REGS),
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        VMSTATE_END_OF_LIST(),
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    }
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};
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static const MemoryRegionOps aspeed_i3c_device_ops = {
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    .read = aspeed_i3c_device_read,
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    .write = aspeed_i3c_device_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void aspeed_i3c_device_reset(DeviceState *dev)
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{
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    AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev);
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    memcpy(s->regs, ast2600_i3c_device_resets, sizeof(s->regs));
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}
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static void aspeed_i3c_device_realize(DeviceState *dev, Error **errp)
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{
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    AspeedI3CDevice *s = ASPEED_I3C_DEVICE(dev);
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    g_autofree char *name = g_strdup_printf(TYPE_ASPEED_I3C_DEVICE ".%d",
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                                            s->id);
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    sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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    memory_region_init_io(&s->mr, OBJECT(s), &aspeed_i3c_device_ops,
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                          s, name, ASPEED_I3C_DEVICE_NR_REGS << 2);
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}
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static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int size)
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{
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    AspeedI3CState *s = ASPEED_I3C(opaque);
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    uint64_t val = 0;
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    val = s->regs[addr >> 2];
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    trace_aspeed_i3c_read(addr, val);
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    return val;
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}
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static void aspeed_i3c_write(void *opaque,
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                             hwaddr addr,
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                             uint64_t data,
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                             unsigned int size)
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{
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    AspeedI3CState *s = ASPEED_I3C(opaque);
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    trace_aspeed_i3c_write(addr, data);
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    addr >>= 2;
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    /* I3C controller register */
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    switch (addr) {
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    case R_I3C1_REG1:
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    case R_I3C2_REG1:
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    case R_I3C3_REG1:
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    case R_I3C4_REG1:
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    case R_I3C5_REG1:
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    case R_I3C6_REG1:
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        if (data & R_I3C1_REG1_I2C_MODE_MASK) {
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            qemu_log_mask(LOG_UNIMP,
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                          "%s: Unsupported I2C mode [0x%08" HWADDR_PRIx
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                          "]=%08" PRIx64 "\n",
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                          __func__, addr << 2, data);
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            break;
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        }
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        if (data & R_I3C1_REG1_SA_EN_MASK) {
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            qemu_log_mask(LOG_UNIMP,
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                          "%s: Unsupported slave mode [%08" HWADDR_PRIx
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                          "]=0x%08" PRIx64 "\n",
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                          __func__, addr << 2, data);
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            break;
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        }
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        s->regs[addr] = data;
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        break;
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    default:
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        s->regs[addr] = data;
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        break;
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    }
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}
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static const MemoryRegionOps aspeed_i3c_ops = {
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    .read = aspeed_i3c_read,
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    .write = aspeed_i3c_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 4,
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    }
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};
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static void aspeed_i3c_reset(DeviceState *dev)
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{
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    AspeedI3CState *s = ASPEED_I3C(dev);
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    memset(s->regs, 0, sizeof(s->regs));
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}
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static void aspeed_i3c_instance_init(Object *obj)
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{
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    AspeedI3CState *s = ASPEED_I3C(obj);
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    int i;
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    for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) {
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        object_initialize_child(obj, "device[*]", &s->devices[i],
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                TYPE_ASPEED_I3C_DEVICE);
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    }
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}
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static void aspeed_i3c_realize(DeviceState *dev, Error **errp)
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{
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    int i;
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    AspeedI3CState *s = ASPEED_I3C(dev);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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    memory_region_init(&s->iomem_container, OBJECT(s),
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            TYPE_ASPEED_I3C ".container", 0x8000);
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    sysbus_init_mmio(sbd, &s->iomem_container);
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    memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_i3c_ops, s,
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            TYPE_ASPEED_I3C ".regs", ASPEED_I3C_NR_REGS << 2);
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    memory_region_add_subregion(&s->iomem_container, 0x0, &s->iomem);
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    for (i = 0; i < ASPEED_I3C_NR_DEVICES; ++i) {
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        Object *i3c_dev = OBJECT(&s->devices[i]);
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        if (!object_property_set_uint(i3c_dev, "device-id", i, errp)) {
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            return;
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        }
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        if (!sysbus_realize(SYS_BUS_DEVICE(i3c_dev), errp)) {
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            return;
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        }
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        /*
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         * Register Address of I3CX Device =
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         *     (Base Address of Global Register) + (Offset of I3CX) + Offset
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         * X = 0, 1, 2, 3, 4, 5
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         * Offset of I3C0 = 0x2000
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         * Offset of I3C1 = 0x3000
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         * Offset of I3C2 = 0x4000
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         * Offset of I3C3 = 0x5000
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         * Offset of I3C4 = 0x6000
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         * Offset of I3C5 = 0x7000
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         */
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        memory_region_add_subregion(&s->iomem_container,
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                0x2000 + i * 0x1000, &s->devices[i].mr);
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    }
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}
325

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static Property aspeed_i3c_device_properties[] = {
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    DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_i3c_device_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->desc = "Aspeed I3C Device";
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    dc->realize = aspeed_i3c_device_realize;
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    dc->reset = aspeed_i3c_device_reset;
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    device_class_set_props(dc, aspeed_i3c_device_properties);
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}
340

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static const TypeInfo aspeed_i3c_device_info = {
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    .name = TYPE_ASPEED_I3C_DEVICE,
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    .parent = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(AspeedI3CDevice),
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    .class_init = aspeed_i3c_device_class_init,
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};
347

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static const VMStateDescription vmstate_aspeed_i3c = {
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    .name = TYPE_ASPEED_I3C,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32_ARRAY(regs, AspeedI3CState, ASPEED_I3C_NR_REGS),
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        VMSTATE_STRUCT_ARRAY(devices, AspeedI3CState, ASPEED_I3C_NR_DEVICES, 1,
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                             aspeed_i3c_device_vmstate, AspeedI3CDevice),
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        VMSTATE_END_OF_LIST(),
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    }
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};
359

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static void aspeed_i3c_class_init(ObjectClass *klass, void *data)
361
{
362
    DeviceClass *dc = DEVICE_CLASS(klass);
363

364
    dc->realize = aspeed_i3c_realize;
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    dc->reset = aspeed_i3c_reset;
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    dc->desc = "Aspeed I3C Controller";
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    dc->vmsd = &vmstate_aspeed_i3c;
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}
369

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static const TypeInfo aspeed_i3c_info = {
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    .name = TYPE_ASPEED_I3C,
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    .parent = TYPE_SYS_BUS_DEVICE,
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    .instance_init = aspeed_i3c_instance_init,
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    .instance_size = sizeof(AspeedI3CState),
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    .class_init = aspeed_i3c_class_init,
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};
377

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static void aspeed_i3c_register_types(void)
379
{
380
    type_register_static(&aspeed_i3c_device_info);
381
    type_register_static(&aspeed_i3c_info);
382
}
383

384
type_init(aspeed_i3c_register_types);
385