qemu

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/*
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 * ARM11MPCore Snoop Control Unit (SCU) emulation
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 *
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 * Copyright (c) 2006-2007 CodeSourcery.
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 * Copyright (c) 2013 SUSE LINUX Products GmbH
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 * Written by Paul Brook and Andreas Färber
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 *
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 * This code is licensed under the GPL.
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 */
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#include "qemu/osdep.h"
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#include "hw/misc/arm11scu.h"
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#include "hw/qdev-properties.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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static uint64_t mpcore_scu_read(void *opaque, hwaddr offset,
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                                unsigned size)
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{
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    ARM11SCUState *s = (ARM11SCUState *)opaque;
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    int id;
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    /* SCU */
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    switch (offset) {
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    case 0x00: /* Control.  */
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        return s->control;
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    case 0x04: /* Configuration.  */
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        id = ((1 << s->num_cpu) - 1) << 4;
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        return id | (s->num_cpu - 1);
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    case 0x08: /* CPU status.  */
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        return 0;
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    case 0x0c: /* Invalidate all.  */
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        return 0;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "mpcore_priv_read: Bad offset %x\n", (int)offset);
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        return 0;
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    }
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}
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static void mpcore_scu_write(void *opaque, hwaddr offset,
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                             uint64_t value, unsigned size)
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{
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    ARM11SCUState *s = (ARM11SCUState *)opaque;
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    /* SCU */
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    switch (offset) {
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    case 0: /* Control register.  */
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        s->control = value & 1;
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        break;
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    case 0x0c: /* Invalidate all.  */
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        /* This is a no-op as cache is not emulated.  */
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "mpcore_priv_read: Bad offset %x\n", (int)offset);
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    }
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}
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static const MemoryRegionOps mpcore_scu_ops = {
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    .read = mpcore_scu_read,
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    .write = mpcore_scu_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void arm11_scu_realize(DeviceState *dev, Error **errp)
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{
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}
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static void arm11_scu_init(Object *obj)
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{
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    ARM11SCUState *s = ARM11_SCU(obj);
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    memory_region_init_io(&s->iomem, OBJECT(s),
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                          &mpcore_scu_ops, s, "mpcore-scu", 0x100);
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    sysbus_init_mmio(sbd, &s->iomem);
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}
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static Property arm11_scu_properties[] = {
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    DEFINE_PROP_UINT32("num-cpu", ARM11SCUState, num_cpu, 1),
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    DEFINE_PROP_END_OF_LIST()
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};
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static void arm11_scu_class_init(ObjectClass *oc, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(oc);
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    dc->realize = arm11_scu_realize;
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    device_class_set_props(dc, arm11_scu_properties);
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}
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static const TypeInfo arm11_scu_type_info = {
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    .name          = TYPE_ARM11_SCU,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(ARM11SCUState),
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    .instance_init = arm11_scu_init,
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    .class_init    = arm11_scu_class_init,
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};
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static void arm11_scu_register_types(void)
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{
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    type_register_static(&arm11_scu_type_info);
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}
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type_init(arm11_scu_register_types)
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