qemu

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/*
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 * Cortex-A9MPCore Snoop Control Unit (SCU) emulation.
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 *
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 * Copyright (c) 2009 CodeSourcery.
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 * Copyright (c) 2011 Linaro Limited.
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 * Written by Paul Brook, Peter Maydell.
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 *
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 * This code is licensed under the GPL.
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 */
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#include "qemu/osdep.h"
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#include "hw/misc/a9scu.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#define A9_SCU_CPU_MAX  4
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static uint64_t a9_scu_read(void *opaque, hwaddr offset,
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                            unsigned size)
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{
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    A9SCUState *s = (A9SCUState *)opaque;
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    switch (offset) {
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    case 0x00: /* Control */
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        return s->control;
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    case 0x04: /* Configuration */
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        return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1);
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    case 0x08: /* CPU Power Status */
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        return s->status;
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    case 0x0c: /* Invalidate All Registers In Secure State */
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        return 0;
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    case 0x40: /* Filtering Start Address Register */
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    case 0x44: /* Filtering End Address Register */
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        /* RAZ/WI, like an implementation with only one AXI master */
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        return 0;
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    case 0x50: /* SCU Access Control Register */
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    case 0x54: /* SCU Non-secure Access Control Register */
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        /* unimplemented, fall through */
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    default:
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        qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx"\n",
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                      __func__, offset);
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        return 0;
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    }
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}
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static void a9_scu_write(void *opaque, hwaddr offset,
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                         uint64_t value, unsigned size)
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{
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    A9SCUState *s = (A9SCUState *)opaque;
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    switch (offset) {
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    case 0x00: /* Control */
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        s->control = value & 1;
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        break;
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    case 0x4: /* Configuration: RO */
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        break;
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    case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */
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        s->status = value;
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        break;
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    case 0x0c: /* Invalidate All Registers In Secure State */
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        /* no-op as we do not implement caches */
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        break;
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    case 0x40: /* Filtering Start Address Register */
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    case 0x44: /* Filtering End Address Register */
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        /* RAZ/WI, like an implementation with only one AXI master */
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        break;
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    case 0x50: /* SCU Access Control Register */
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    case 0x54: /* SCU Non-secure Access Control Register */
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        /* unimplemented, fall through */
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    default:
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        qemu_log_mask(LOG_UNIMP, "%s: Unsupported offset 0x%"HWADDR_PRIx
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                                 " value 0x%"PRIx64"\n",
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                      __func__, offset, value);
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        break;
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    }
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}
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static const MemoryRegionOps a9_scu_ops = {
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    .read = a9_scu_read,
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    .write = a9_scu_write,
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    .impl = {
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        .min_access_size = 4,
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        .max_access_size = 4,
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    },
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 4,
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    },
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    .endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void a9_scu_reset(DeviceState *dev)
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{
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    A9SCUState *s = A9_SCU(dev);
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    s->control = 0;
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}
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static void a9_scu_realize(DeviceState *dev, Error **errp)
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{
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    A9SCUState *s = A9_SCU(dev);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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    if (!s->num_cpu || s->num_cpu > A9_SCU_CPU_MAX) {
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        error_setg(errp, "Illegal CPU count: %u", s->num_cpu);
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        return;
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    }
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    memory_region_init_io(&s->iomem, OBJECT(s), &a9_scu_ops, s,
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                          "a9-scu", 0x100);
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    sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription vmstate_a9_scu = {
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    .name = "a9-scu",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(control, A9SCUState),
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        VMSTATE_UINT32(status, A9SCUState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static Property a9_scu_properties[] = {
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    DEFINE_PROP_UINT32("num-cpu", A9SCUState, num_cpu, 1),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void a9_scu_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    device_class_set_props(dc, a9_scu_properties);
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    dc->vmsd = &vmstate_a9_scu;
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    dc->reset = a9_scu_reset;
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    dc->realize = a9_scu_realize;
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}
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static const TypeInfo a9_scu_info = {
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    .name          = TYPE_A9_SCU,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(A9SCUState),
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    .class_init    = a9_scu_class_init,
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};
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static void a9mp_register_types(void)
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{
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    type_register_static(&a9_scu_info);
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}
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type_init(a9mp_register_types)
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