qemu

1
/*
2
 * QEMU Malta board support
3
 *
4
 * Copyright (c) 2006 Aurelien Jarno
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22
 * THE SOFTWARE.
23
 */
24

25
#include "qemu/osdep.h"
26
#include "qemu/units.h"
27
#include "qemu/bitops.h"
28
#include "qemu/datadir.h"
29
#include "qemu/cutils.h"
30
#include "qemu/guest-random.h"
31
#include "hw/clock.h"
32
#include "hw/southbridge/piix.h"
33
#include "hw/isa/superio.h"
34
#include "hw/char/serial.h"
35
#include "net/net.h"
36
#include "hw/boards.h"
37
#include "hw/i2c/smbus_eeprom.h"
38
#include "hw/block/flash.h"
39
#include "hw/mips/mips.h"
40
#include "hw/mips/bootloader.h"
41
#include "hw/pci/pci.h"
42
#include "hw/pci/pci_bus.h"
43
#include "qemu/log.h"
44
#include "hw/ide/pci.h"
45
#include "hw/irq.h"
46
#include "hw/loader.h"
47
#include "elf.h"
48
#include "qom/object.h"
49
#include "hw/sysbus.h"             /* SysBusDevice */
50
#include "qemu/host-utils.h"
51
#include "sysemu/qtest.h"
52
#include "sysemu/reset.h"
53
#include "sysemu/runstate.h"
54
#include "qapi/error.h"
55
#include "qemu/error-report.h"
56
#include "sysemu/kvm.h"
57
#include "semihosting/semihost.h"
58
#include "hw/mips/cps.h"
59
#include "hw/qdev-clock.h"
60
#include "target/mips/internal.h"
61
#include "trace.h"
62
#include "cpu.h"
63

64
#define ENVP_PADDR          0x2000
65
#define ENVP_VADDR          cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
66
#define ENVP_NB_ENTRIES     16
67
#define ENVP_ENTRY_SIZE     256
68

69
/* Hardware addresses */
70
#define FLASH_ADDRESS       0x1e000000ULL
71
#define FPGA_ADDRESS        0x1f000000ULL
72
#define RESET_ADDRESS       0x1fc00000ULL
73

74
#define FLASH_SIZE          0x400000
75
#define BIOS_SIZE           (4 * MiB)
76

77
#define PIIX4_PCI_DEVFN     PCI_DEVFN(10, 0)
78

79
typedef struct {
80
    MemoryRegion iomem;
81
    MemoryRegion iomem_lo; /* 0 - 0x900 */
82
    MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
83
    uint32_t leds;
84
    uint32_t brk;
85
    uint32_t gpout;
86
    uint32_t i2cin;
87
    uint32_t i2coe;
88
    uint32_t i2cout;
89
    uint32_t i2csel;
90
    CharBackend display;
91
    char display_text[9];
92
    SerialMM *uart;
93
    bool display_inited;
94
} MaltaFPGAState;
95

96
#if TARGET_BIG_ENDIAN
97
#define BIOS_FILENAME "mips_bios.bin"
98
#else
99
#define BIOS_FILENAME "mipsel_bios.bin"
100
#endif
101

102
#define TYPE_MIPS_MALTA "mips-malta"
103
OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)
104

105
struct MaltaState {
106
    SysBusDevice parent_obj;
107

108
    Clock *cpuclk;
109
    MIPSCPSState cps;
110
};
111

112
static struct _loaderparams {
113
    int ram_size, ram_low_size;
114
    const char *kernel_filename;
115
    const char *kernel_cmdline;
116
    const char *initrd_filename;
117
} loaderparams;
118

119
/* Malta FPGA */
120
static void malta_fpga_update_display_leds(MaltaFPGAState *s)
121
{
122
    char leds_text[9];
123
    int i;
124

125
    for (i = 7 ; i >= 0 ; i--) {
126
        if (s->leds & (1 << i)) {
127
            leds_text[i] = '#';
128
        } else {
129
            leds_text[i] = ' ';
130
        }
131
    }
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    leds_text[8] = '\0';
133

134
    trace_malta_fpga_leds(leds_text);
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    qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
136
                       leds_text);
137
}
138

139
static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
140
{
141
    trace_malta_fpga_display(s->display_text);
142
    qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
143
                       s->display_text);
144
}
145

146
/*
147
 * EEPROM 24C01 / 24C02 emulation.
148
 *
149
 * Emulation for serial EEPROMs:
150
 * 24C01 - 1024 bit (128 x 8)
151
 * 24C02 - 2048 bit (256 x 8)
152
 *
153
 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
154
 */
155

156
#if defined(DEBUG)
157
#  define logout(fmt, ...) \
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          fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
159
#else
160
#  define logout(fmt, ...) ((void)0)
161
#endif
162

163
struct _eeprom24c0x_t {
164
  uint8_t tick;
165
  uint8_t address;
166
  uint8_t command;
167
  uint8_t ack;
168
  uint8_t scl;
169
  uint8_t sda;
170
  uint8_t data;
171
  /* uint16_t size; */
172
  uint8_t contents[256];
173
};
174

175
typedef struct _eeprom24c0x_t eeprom24c0x_t;
176

177
static eeprom24c0x_t spd_eeprom = {
178
    .contents = {
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        /* 00000000: */
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        0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
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        /* 00000008: */
182
        0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
183
        /* 00000010: */
184
        0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
185
        /* 00000018: */
186
        0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
187
        /* 00000020: */
188
        0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
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        /* 00000028: */
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        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
191
        /* 00000030: */
192
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
193
        /* 00000038: */
194
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
195
        /* 00000040: */
196
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
197
        /* 00000048: */
198
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
199
        /* 00000050: */
200
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
201
        /* 00000058: */
202
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
203
        /* 00000060: */
204
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
205
        /* 00000068: */
206
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
207
        /* 00000070: */
208
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
209
        /* 00000078: */
210
        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
211
    },
212
};
213

214
static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
215
{
216
    enum sdram_type type;
217
    uint8_t *spd = spd_eeprom.contents;
218
    uint8_t nbanks = 0;
219
    uint16_t density = 0;
220
    int i;
221

222
    /* work in terms of MB */
223
    ram_size /= MiB;
224

225
    while ((ram_size >= 4) && (nbanks <= 2)) {
226
        int sz_log2 = MIN(31 - clz32(ram_size), 14);
227
        nbanks++;
228
        density |= 1 << (sz_log2 - 2);
229
        ram_size -= 1 << sz_log2;
230
    }
231

232
    /* split to 2 banks if possible */
233
    if ((nbanks == 1) && (density > 1)) {
234
        nbanks++;
235
        density >>= 1;
236
    }
237

238
    if (density & 0xff00) {
239
        density = (density & 0xe0) | ((density >> 8) & 0x1f);
240
        type = DDR2;
241
    } else if (!(density & 0x1f)) {
242
        type = DDR2;
243
    } else {
244
        type = SDR;
245
    }
246

247
    if (ram_size) {
248
        warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
249
                    " of SDRAM", ram_size);
250
    }
251

252
    /* fill in SPD memory information */
253
    spd[2] = type;
254
    spd[5] = nbanks;
255
    spd[31] = density;
256

257
    /* checksum */
258
    spd[63] = 0;
259
    for (i = 0; i < 63; i++) {
260
        spd[63] += spd[i];
261
    }
262

263
    /* copy for SMBUS */
264
    memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
265
}
266

267
static void generate_eeprom_serial(uint8_t *eeprom)
268
{
269
    int i, pos = 0;
270
    uint8_t mac[6] = { 0x00 };
271
    uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
272

273
    /* version */
274
    eeprom[pos++] = 0x01;
275

276
    /* count */
277
    eeprom[pos++] = 0x02;
278

279
    /* MAC address */
280
    eeprom[pos++] = 0x01; /* MAC */
281
    eeprom[pos++] = 0x06; /* length */
282
    memcpy(&eeprom[pos], mac, sizeof(mac));
283
    pos += sizeof(mac);
284

285
    /* serial number */
286
    eeprom[pos++] = 0x02; /* serial */
287
    eeprom[pos++] = 0x05; /* length */
288
    memcpy(&eeprom[pos], sn, sizeof(sn));
289
    pos += sizeof(sn);
290

291
    /* checksum */
292
    eeprom[pos] = 0;
293
    for (i = 0; i < pos; i++) {
294
        eeprom[pos] += eeprom[i];
295
    }
296
}
297

298
static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
299
{
300
    logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
301
        eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
302
    return eeprom->sda;
303
}
304

305
static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
306
{
307
    if (eeprom->scl && scl && (eeprom->sda != sda)) {
308
        logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
309
                eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
310
                sda ? "stop" : "start");
311
        if (!sda) {
312
            eeprom->tick = 1;
313
            eeprom->command = 0;
314
        }
315
    } else if (eeprom->tick == 0 && !eeprom->ack) {
316
        /* Waiting for start. */
317
        logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
318
                eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
319
    } else if (!eeprom->scl && scl) {
320
        logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
321
                eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
322
        if (eeprom->ack) {
323
            logout("\ti2c ack bit = 0\n");
324
            sda = 0;
325
            eeprom->ack = 0;
326
        } else if (eeprom->sda == sda) {
327
            uint8_t bit = (sda != 0);
328
            logout("\ti2c bit = %d\n", bit);
329
            if (eeprom->tick < 9) {
330
                eeprom->command <<= 1;
331
                eeprom->command += bit;
332
                eeprom->tick++;
333
                if (eeprom->tick == 9) {
334
                    logout("\tcommand 0x%04x, %s\n", eeprom->command,
335
                           bit ? "read" : "write");
336
                    eeprom->ack = 1;
337
                }
338
            } else if (eeprom->tick < 17) {
339
                if (eeprom->command & 1) {
340
                    sda = ((eeprom->data & 0x80) != 0);
341
                }
342
                eeprom->address <<= 1;
343
                eeprom->address += bit;
344
                eeprom->tick++;
345
                eeprom->data <<= 1;
346
                if (eeprom->tick == 17) {
347
                    eeprom->data = eeprom->contents[eeprom->address];
348
                    logout("\taddress 0x%04x, data 0x%02x\n",
349
                           eeprom->address, eeprom->data);
350
                    eeprom->ack = 1;
351
                    eeprom->tick = 0;
352
                }
353
            } else if (eeprom->tick >= 17) {
354
                sda = 0;
355
            }
356
        } else {
357
            logout("\tsda changed with raising scl\n");
358
        }
359
    } else {
360
        logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
361
               scl, eeprom->sda, sda);
362
    }
363
    eeprom->scl = scl;
364
    eeprom->sda = sda;
365
}
366

367
static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
368
                                unsigned size)
369
{
370
    MaltaFPGAState *s = opaque;
371
    uint32_t val = 0;
372
    uint32_t saddr;
373

374
    saddr = (addr & 0xfffff);
375

376
    switch (saddr) {
377

378
    /* SWITCH Register */
379
    case 0x00200:
380
        val = 0x00000000;
381
        break;
382

383
    /* STATUS Register */
384
    case 0x00208:
385
#if TARGET_BIG_ENDIAN
386
        val = 0x00000012;
387
#else
388
        val = 0x00000010;
389
#endif
390
        break;
391

392
    /* JMPRS Register */
393
    case 0x00210:
394
        val = 0x00;
395
        break;
396

397
    /* LEDBAR Register */
398
    case 0x00408:
399
        val = s->leds;
400
        break;
401

402
    /* BRKRES Register */
403
    case 0x00508:
404
        val = s->brk;
405
        break;
406

407
    /* UART Registers are handled directly by the serial device */
408

409
    /* GPOUT Register */
410
    case 0x00a00:
411
        val = s->gpout;
412
        break;
413

414
    /* XXX: implement a real I2C controller */
415

416
    /* GPINP Register */
417
    case 0x00a08:
418
        /* IN = OUT until a real I2C control is implemented */
419
        if (s->i2csel) {
420
            val = s->i2cout;
421
        } else {
422
            val = 0x00;
423
        }
424
        break;
425

426
    /* I2CINP Register */
427
    case 0x00b00:
428
        val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
429
        break;
430

431
    /* I2COE Register */
432
    case 0x00b08:
433
        val = s->i2coe;
434
        break;
435

436
    /* I2COUT Register */
437
    case 0x00b10:
438
        val = s->i2cout;
439
        break;
440

441
    /* I2CSEL Register */
442
    case 0x00b18:
443
        val = s->i2csel;
444
        break;
445

446
    default:
447
        qemu_log_mask(LOG_GUEST_ERROR,
448
                      "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n",
449
                      addr);
450
        break;
451
    }
452
    return val;
453
}
454

455
static void malta_fpga_write(void *opaque, hwaddr addr,
456
                             uint64_t val, unsigned size)
457
{
458
    MaltaFPGAState *s = opaque;
459
    uint32_t saddr;
460

461
    saddr = (addr & 0xfffff);
462

463
    switch (saddr) {
464

465
    /* SWITCH Register */
466
    case 0x00200:
467
        break;
468

469
    /* JMPRS Register */
470
    case 0x00210:
471
        break;
472

473
    /* LEDBAR Register */
474
    case 0x00408:
475
        s->leds = val & 0xff;
476
        malta_fpga_update_display_leds(s);
477
        break;
478

479
    /* ASCIIWORD Register */
480
    case 0x00410:
481
        snprintf(s->display_text, 9, "%08X", (uint32_t)val);
482
        malta_fpga_update_display_ascii(s);
483
        break;
484

485
    /* ASCIIPOS0 to ASCIIPOS7 Registers */
486
    case 0x00418:
487
    case 0x00420:
488
    case 0x00428:
489
    case 0x00430:
490
    case 0x00438:
491
    case 0x00440:
492
    case 0x00448:
493
    case 0x00450:
494
        s->display_text[(saddr - 0x00418) >> 3] = (char) val;
495
        malta_fpga_update_display_ascii(s);
496
        break;
497

498
    /* SOFTRES Register */
499
    case 0x00500:
500
        if (val == 0x42) {
501
            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
502
        }
503
        break;
504

505
    /* BRKRES Register */
506
    case 0x00508:
507
        s->brk = val & 0xff;
508
        break;
509

510
    /* UART Registers are handled directly by the serial device */
511

512
    /* GPOUT Register */
513
    case 0x00a00:
514
        s->gpout = val & 0xff;
515
        break;
516

517
    /* I2COE Register */
518
    case 0x00b08:
519
        s->i2coe = val & 0x03;
520
        break;
521

522
    /* I2COUT Register */
523
    case 0x00b10:
524
        eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
525
        s->i2cout = val;
526
        break;
527

528
    /* I2CSEL Register */
529
    case 0x00b18:
530
        s->i2csel = val & 0x01;
531
        break;
532

533
    default:
534
        qemu_log_mask(LOG_GUEST_ERROR,
535
                      "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n",
536
                      addr);
537
        break;
538
    }
539
}
540

541
static const MemoryRegionOps malta_fpga_ops = {
542
    .read = malta_fpga_read,
543
    .write = malta_fpga_write,
544
    .endianness = DEVICE_NATIVE_ENDIAN,
545
};
546

547
static void malta_fpga_reset(void *opaque)
548
{
549
    MaltaFPGAState *s = opaque;
550

551
    s->leds   = 0x00;
552
    s->brk    = 0x0a;
553
    s->gpout  = 0x00;
554
    s->i2cin  = 0x3;
555
    s->i2coe  = 0x0;
556
    s->i2cout = 0x3;
557
    s->i2csel = 0x1;
558

559
    s->display_text[8] = '\0';
560
    snprintf(s->display_text, 9, "        ");
561
}
562

563
static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event)
564
{
565
    MaltaFPGAState *s = opaque;
566

567
    if (event == CHR_EVENT_OPENED && !s->display_inited) {
568
        qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
569
        qemu_chr_fe_printf(&s->display, "+--------+\r\n");
570
        qemu_chr_fe_printf(&s->display, "+        +\r\n");
571
        qemu_chr_fe_printf(&s->display, "+--------+\r\n");
572
        qemu_chr_fe_printf(&s->display, "\n");
573
        qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
574
        qemu_chr_fe_printf(&s->display, "+--------+\r\n");
575
        qemu_chr_fe_printf(&s->display, "+        +\r\n");
576
        qemu_chr_fe_printf(&s->display, "+--------+\r\n");
577
        s->display_inited = true;
578
    }
579
}
580

581
static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
582
         hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
583
{
584
    MaltaFPGAState *s;
585
    Chardev *chr;
586

587
    s = g_new0(MaltaFPGAState, 1);
588

589
    memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
590
                          "malta-fpga", 0x100000);
591
    memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
592
                             &s->iomem, 0, 0x900);
593
    memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
594
                             &s->iomem, 0xa00, 0x100000 - 0xa00);
595

596
    memory_region_add_subregion(address_space, base, &s->iomem_lo);
597
    memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
598

599
    chr = qemu_chr_new("fpga", "vc:320x200", NULL);
600
    qemu_chr_fe_init(&s->display, chr, NULL);
601
    qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
602
                             malta_fgpa_display_event, NULL, s, NULL, true);
603

604
    s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
605
                             230400, uart_chr, DEVICE_NATIVE_ENDIAN);
606

607
    malta_fpga_reset(s);
608
    qemu_register_reset(malta_fpga_reset, s);
609

610
    return s;
611
}
612

613
/* Network support */
614
static void network_init(PCIBus *pci_bus)
615
{
616
    /* The malta board has a PCNet card using PCI SLOT 11 */
617
    pci_init_nic_in_slot(pci_bus, "pcnet", NULL, "0b");
618
    pci_init_nic_devices(pci_bus, "pcnet");
619
}
620

621
static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
622
                                         uint64_t kernel_entry)
623
{
624
    static const char pci_pins_cfg[PCI_NUM_PINS] = {
625
        10, 10, 11, 11 /* PIIX IRQRC[A:D] */
626
    };
627

628
    /* Bus endianness is always reversed */
629
#if TARGET_BIG_ENDIAN
630
#define cpu_to_gt32(x) (x)
631
#else
632
#define cpu_to_gt32(x) bswap32(x)
633
#endif
634

635
    /* setup MEM-to-PCI0 mapping as done by YAMON */
636

637
    /* move GT64120 registers from 0x14000000 to 0x1be00000 */
638
    bl_gen_write_u32(p, /* GT_ISD */
639
                     cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
640
                     cpu_to_gt32(0x1be00000 << 3));
641

642
    /* setup PCI0 io window to 0x18000000-0x181fffff */
643
    bl_gen_write_u32(p, /* GT_PCI0IOLD */
644
                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
645
                     cpu_to_gt32(0x18000000 << 3));
646
    bl_gen_write_u32(p, /* GT_PCI0IOHD */
647
                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
648
                     cpu_to_gt32(0x08000000 << 3));
649

650
    /* setup PCI0 mem windows */
651
    bl_gen_write_u32(p, /* GT_PCI0M0LD */
652
                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
653
                     cpu_to_gt32(0x10000000 << 3));
654
    bl_gen_write_u32(p, /* GT_PCI0M0HD */
655
                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
656
                     cpu_to_gt32(0x07e00000 << 3));
657
    bl_gen_write_u32(p, /* GT_PCI0M1LD */
658
                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
659
                     cpu_to_gt32(0x18200000 << 3));
660
    bl_gen_write_u32(p, /* GT_PCI0M1HD */
661
                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
662
                     cpu_to_gt32(0x0bc00000 << 3));
663

664
#undef cpu_to_gt32
665

666
    /*
667
     * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0.
668
     * Load the PIIX IRQC[A:D] routing config address, then
669
     * write routing configuration to the config data register.
670
     */
671
    bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */
672
                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8),
673
                     tswap32((1 << 31) /* ConfigEn */
674
                             | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8
675
                             | PIIX_PIRQCA));
676
    bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */
677
                     cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc),
678
                     tswap32(ldl_be_p(pci_pins_cfg)));
679

680
    bl_gen_jump_kernel(p,
681
                       true, ENVP_VADDR - 64,
682
                       /*
683
                        * If semihosting is used, arguments have already
684
                        * been passed, so we preserve $a0.
685
                        */
686
                       !semihosting_get_argc(), 2,
687
                       true, ENVP_VADDR,
688
                       true, ENVP_VADDR + 8,
689
                       true, loaderparams.ram_low_size,
690
                       kernel_entry);
691
}
692

693
static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
694
                                      uint64_t kernel_entry)
695
{
696
    uint16_t *p;
697

698
    /* Small bootloader */
699
    p = (uint16_t *)base;
700

701
    stw_p(p++, 0x2800); stw_p(p++, 0x001c);
702
                                /* bc to_here */
703
    stw_p(p++, 0x8000); stw_p(p++, 0xc000);
704
                                /* nop */
705
    stw_p(p++, 0x8000); stw_p(p++, 0xc000);
706
                                /* nop */
707
    stw_p(p++, 0x8000); stw_p(p++, 0xc000);
708
                                /* nop */
709
    stw_p(p++, 0x8000); stw_p(p++, 0xc000);
710
                                /* nop */
711
    stw_p(p++, 0x8000); stw_p(p++, 0xc000);
712
                                /* nop */
713
    stw_p(p++, 0x8000); stw_p(p++, 0xc000);
714
                                /* nop */
715
    stw_p(p++, 0x8000); stw_p(p++, 0xc000);
716
                                /* nop */
717

718
    /* to_here: */
719

720
    bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
721
}
722

723
/*
724
 * ROM and pseudo bootloader
725
 *
726
 * The following code implements a very very simple bootloader. It first
727
 * loads the registers a0 to a3 to the values expected by the OS, and
728
 * then jump at the kernel address.
729
 *
730
 * The bootloader should pass the locations of the kernel arguments and
731
 * environment variables tables. Those tables contain the 32-bit address
732
 * of NULL terminated strings. The environment variables table should be
733
 * terminated by a NULL address.
734
 *
735
 * For a simpler implementation, the number of kernel arguments is fixed
736
 * to two (the name of the kernel and the command line), and the two
737
 * tables are actually the same one.
738
 *
739
 * The registers a0 to a3 should contain the following values:
740
 *   a0 - number of kernel arguments
741
 *   a1 - 32-bit address of the kernel arguments table
742
 *   a2 - 32-bit address of the environment variables table
743
 *   a3 - RAM size in bytes
744
 */
745
static void write_bootloader(uint8_t *base, uint64_t run_addr,
746
                             uint64_t kernel_entry)
747
{
748
    uint32_t *p;
749

750
    /* Small bootloader */
751
    p = (uint32_t *)base;
752

753
    stl_p(p++, 0x08000000 |                  /* j 0x1fc00580 */
754
                 ((run_addr + 0x580) & 0x0fffffff) >> 2);
755
    stl_p(p++, 0x00000000);                  /* nop */
756

757
    /* YAMON service vector */
758
    stl_p(base + 0x500, run_addr + 0x0580);  /* start: */
759
    stl_p(base + 0x504, run_addr + 0x083c);  /* print_count: */
760
    stl_p(base + 0x520, run_addr + 0x0580);  /* start: */
761
    stl_p(base + 0x52c, run_addr + 0x0800);  /* flush_cache: */
762
    stl_p(base + 0x534, run_addr + 0x0808);  /* print: */
763
    stl_p(base + 0x538, run_addr + 0x0800);  /* reg_cpu_isr: */
764
    stl_p(base + 0x53c, run_addr + 0x0800);  /* unred_cpu_isr: */
765
    stl_p(base + 0x540, run_addr + 0x0800);  /* reg_ic_isr: */
766
    stl_p(base + 0x544, run_addr + 0x0800);  /* unred_ic_isr: */
767
    stl_p(base + 0x548, run_addr + 0x0800);  /* reg_esr: */
768
    stl_p(base + 0x54c, run_addr + 0x0800);  /* unreg_esr: */
769
    stl_p(base + 0x550, run_addr + 0x0800);  /* getchar: */
770
    stl_p(base + 0x554, run_addr + 0x0800);  /* syscon_read: */
771

772

773
    /* Second part of the bootloader */
774
    p = (uint32_t *) (base + 0x580);
775

776
    /*
777
     * Load BAR registers as done by YAMON:
778
     *
779
     *  - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
780
     *  - set up PCI0 MEM0 at 0x10000000, size 0x7e00000
781
     *  - set up PCI0 MEM1 at 0x18200000, size 0xbc00000
782
     *
783
     */
784

785
    bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
786

787
    /* YAMON subroutines */
788
    p = (uint32_t *) (base + 0x800);
789
    stl_p(p++, 0x03e00009);                  /* jalr ra */
790
    stl_p(p++, 0x24020000);                  /* li v0,0 */
791
    /* 808 YAMON print */
792
    stl_p(p++, 0x03e06821);                  /* move t5,ra */
793
    stl_p(p++, 0x00805821);                  /* move t3,a0 */
794
    stl_p(p++, 0x00a05021);                  /* move t2,a1 */
795
    stl_p(p++, 0x91440000);                  /* lbu a0,0(t2) */
796
    stl_p(p++, 0x254a0001);                  /* addiu t2,t2,1 */
797
    stl_p(p++, 0x10800005);                  /* beqz a0,834 */
798
    stl_p(p++, 0x00000000);                  /* nop */
799
    stl_p(p++, 0x0ff0021c);                  /* jal 870 */
800
    stl_p(p++, 0x00000000);                  /* nop */
801
    stl_p(p++, 0x1000fff9);                  /* b 814 */
802
    stl_p(p++, 0x00000000);                  /* nop */
803
    stl_p(p++, 0x01a00009);                  /* jalr t5 */
804
    stl_p(p++, 0x01602021);                  /* move a0,t3 */
805
    /* 0x83c YAMON print_count */
806
    stl_p(p++, 0x03e06821);                  /* move t5,ra */
807
    stl_p(p++, 0x00805821);                  /* move t3,a0 */
808
    stl_p(p++, 0x00a05021);                  /* move t2,a1 */
809
    stl_p(p++, 0x00c06021);                  /* move t4,a2 */
810
    stl_p(p++, 0x91440000);                  /* lbu a0,0(t2) */
811
    stl_p(p++, 0x0ff0021c);                  /* jal 870 */
812
    stl_p(p++, 0x00000000);                  /* nop */
813
    stl_p(p++, 0x254a0001);                  /* addiu t2,t2,1 */
814
    stl_p(p++, 0x258cffff);                  /* addiu t4,t4,-1 */
815
    stl_p(p++, 0x1580fffa);                  /* bnez t4,84c */
816
    stl_p(p++, 0x00000000);                  /* nop */
817
    stl_p(p++, 0x01a00009);                  /* jalr t5 */
818
    stl_p(p++, 0x01602021);                  /* move a0,t3 */
819
    /* 0x870 */
820
    stl_p(p++, 0x3c08b800);                  /* lui t0,0xb400 */
821
    stl_p(p++, 0x350803f8);                  /* ori t0,t0,0x3f8 */
822
    stl_p(p++, 0x91090005);                  /* lbu t1,5(t0) */
823
    stl_p(p++, 0x00000000);                  /* nop */
824
    stl_p(p++, 0x31290040);                  /* andi t1,t1,0x40 */
825
    stl_p(p++, 0x1120fffc);                  /* beqz t1,878 <outch+0x8> */
826
    stl_p(p++, 0x00000000);                  /* nop */
827
    stl_p(p++, 0x03e00009);                  /* jalr ra */
828
    stl_p(p++, 0xa1040000);                  /* sb a0,0(t0) */
829
}
830

831
static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
832
                                        const char *string, ...)
833
{
834
    va_list ap;
835
    uint32_t table_addr;
836

837
    if (index >= ENVP_NB_ENTRIES) {
838
        return;
839
    }
840

841
    if (string == NULL) {
842
        prom_buf[index] = 0;
843
        return;
844
    }
845

846
    table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
847
    prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
848

849
    va_start(ap, string);
850
    vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
851
    va_end(ap);
852
}
853

854
static GString *rng_seed_hex_new(void)
855
{
856
    uint8_t rng_seed[32];
857

858
    qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
859
    return qemu_hexdump_line(NULL, rng_seed, sizeof(rng_seed), 0, 0);
860
}
861

862
static void reinitialize_rng_seed(void *opaque)
863
{
864
    g_autoptr(GString) hex = rng_seed_hex_new();
865
    memcpy(opaque, hex->str, hex->len);
866
}
867

868
/* Kernel */
869
static uint64_t load_kernel(void)
870
{
871
    uint64_t kernel_entry, kernel_high, initrd_size;
872
    long kernel_size;
873
    ram_addr_t initrd_offset;
874
    uint32_t *prom_buf;
875
    long prom_size;
876
    int prom_index = 0;
877
    size_t rng_seed_prom_offset;
878

879
    kernel_size = load_elf(loaderparams.kernel_filename, NULL,
880
                           cpu_mips_kseg0_to_phys, NULL,
881
                           &kernel_entry, NULL,
882
                           &kernel_high, NULL, TARGET_BIG_ENDIAN, EM_MIPS,
883
                           1, 0);
884
    if (kernel_size < 0) {
885
        error_report("could not load kernel '%s': %s",
886
                     loaderparams.kernel_filename,
887
                     load_elf_strerror(kernel_size));
888
        exit(1);
889
    }
890

891
    /* Check where the kernel has been linked */
892
    if (kernel_entry <= USEG_LIMIT) {
893
        error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)"
894
                     " are not supported");
895
        exit(1);
896
    }
897

898
    /* load initrd */
899
    initrd_size = 0;
900
    initrd_offset = 0;
901
    if (loaderparams.initrd_filename) {
902
        initrd_size = get_image_size(loaderparams.initrd_filename);
903
        if (initrd_size > 0) {
904
            /*
905
             * The kernel allocates the bootmap memory in the low memory after
906
             * the initrd.  It takes at most 128kiB for 2GB RAM and 4kiB
907
             * pages.
908
             */
909
            initrd_offset = ROUND_UP(loaderparams.ram_low_size
910
                                     - (initrd_size + 128 * KiB),
911
                                     INITRD_PAGE_SIZE);
912
            if (kernel_high >= initrd_offset) {
913
                error_report("memory too small for initial ram disk '%s'",
914
                             loaderparams.initrd_filename);
915
                exit(1);
916
            }
917
            initrd_size = load_image_targphys(loaderparams.initrd_filename,
918
                                              initrd_offset,
919
                                              loaderparams.ram_size - initrd_offset);
920
        }
921
        if (initrd_size == (target_ulong) -1) {
922
            error_report("could not load initial ram disk '%s'",
923
                         loaderparams.initrd_filename);
924
            exit(1);
925
        }
926
    }
927

928
    /* Setup prom parameters. */
929
    prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
930
    prom_buf = g_malloc(prom_size);
931

932
    prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
933
    if (initrd_size > 0) {
934
        prom_set(prom_buf, prom_index++,
935
                 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
936
                 cpu_mips_phys_to_kseg0(NULL, initrd_offset),
937
                 initrd_size, loaderparams.kernel_cmdline);
938
    } else {
939
        prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
940
    }
941

942
    prom_set(prom_buf, prom_index++, "memsize");
943
    prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
944

945
    prom_set(prom_buf, prom_index++, "ememsize");
946
    prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
947

948
    prom_set(prom_buf, prom_index++, "modetty0");
949
    prom_set(prom_buf, prom_index++, "38400n8r");
950

951
    prom_set(prom_buf, prom_index++, "rngseed");
952
    rng_seed_prom_offset = prom_index * ENVP_ENTRY_SIZE +
953
                           sizeof(uint32_t) * ENVP_NB_ENTRIES;
954
    {
955
        g_autoptr(GString) hex = rng_seed_hex_new();
956
        prom_set(prom_buf, prom_index++, "%s", hex->str);
957
    }
958

959
    prom_set(prom_buf, prom_index++, NULL);
960

961
    rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
962
    qemu_register_reset_nosnapshotload(reinitialize_rng_seed,
963
            rom_ptr(ENVP_PADDR, prom_size) + rng_seed_prom_offset);
964

965
    g_free(prom_buf);
966
    return kernel_entry;
967
}
968

969
static void malta_mips_config(MIPSCPU *cpu)
970
{
971
    MachineState *ms = MACHINE(qdev_get_machine());
972
    unsigned int smp_cpus = ms->smp.cpus;
973
    CPUMIPSState *env = &cpu->env;
974
    CPUState *cs = CPU(cpu);
975

976
    if (ase_mt_available(env)) {
977
        env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
978
                                           CP0MVPC0_PTC, 8,
979
                                           smp_cpus * cs->nr_threads - 1);
980
        env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
981
                                           CP0MVPC0_PVPE, 4, smp_cpus - 1);
982
    }
983
}
984

985
static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
986
{
987
    int slot;
988

989
    slot = PCI_SLOT(pci_dev->devfn);
990

991
    switch (slot) {
992
    /* PIIX4 USB */
993
    case 10:
994
        return 3;
995
    /* AMD 79C973 Ethernet */
996
    case 11:
997
        return 1;
998
    /* Crystal 4281 Sound */
999
    case 12:
1000
        return 2;
1001
    /* PCI slot 1 to 4 */
1002
    case 18 ... 21:
1003
        return ((slot - 18) + irq_num) & 0x03;
1004
    /* Unknown device, don't do any translation */
1005
    default:
1006
        return irq_num;
1007
    }
1008
}
1009

1010
static void main_cpu_reset(void *opaque)
1011
{
1012
    MIPSCPU *cpu = opaque;
1013
    CPUMIPSState *env = &cpu->env;
1014

1015
    cpu_reset(CPU(cpu));
1016

1017
    /*
1018
     * The bootloader does not need to be rewritten as it is located in a
1019
     * read only location. The kernel location and the arguments table
1020
     * location does not change.
1021
     */
1022
    if (loaderparams.kernel_filename) {
1023
        env->CP0_Status &= ~(1 << CP0St_ERL);
1024
    }
1025

1026
    malta_mips_config(cpu);
1027
}
1028

1029
static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
1030
                                   qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1031
{
1032
    CPUMIPSState *env;
1033
    MIPSCPU *cpu;
1034
    int i;
1035

1036
    for (i = 0; i < ms->smp.cpus; i++) {
1037
        cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
1038

1039
        /* Init internal devices */
1040
        cpu_mips_irq_init_cpu(cpu);
1041
        cpu_mips_clock_init(cpu);
1042
        qemu_register_reset(main_cpu_reset, cpu);
1043
    }
1044

1045
    cpu = MIPS_CPU(first_cpu);
1046
    env = &cpu->env;
1047
    *i8259_irq = env->irq[2];
1048
    *cbus_irq = env->irq[4];
1049
}
1050

1051
static void create_cps(MachineState *ms, MaltaState *s,
1052
                       qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1053
{
1054
    object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
1055
    object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
1056
                            &error_fatal);
1057
    object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
1058
                            &error_fatal);
1059
    qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
1060
    sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
1061

1062
    sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
1063

1064
    *i8259_irq = get_cps_irq(&s->cps, 3);
1065
    *cbus_irq = NULL;
1066
}
1067

1068
static void mips_create_cpu(MachineState *ms, MaltaState *s,
1069
                            qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1070
{
1071
    if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
1072
        create_cps(ms, s, cbus_irq, i8259_irq);
1073
    } else {
1074
        create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
1075
    }
1076
}
1077

1078
static
1079
void mips_malta_init(MachineState *machine)
1080
{
1081
    ram_addr_t ram_size = machine->ram_size;
1082
    ram_addr_t ram_low_size;
1083
    const char *kernel_filename = machine->kernel_filename;
1084
    const char *kernel_cmdline = machine->kernel_cmdline;
1085
    const char *initrd_filename = machine->initrd_filename;
1086
    char *filename;
1087
    PFlashCFI01 *fl;
1088
    MemoryRegion *system_memory = get_system_memory();
1089
    MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
1090
    MemoryRegion *ram_low_postio;
1091
    MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
1092
    const size_t smbus_eeprom_size = 8 * 256;
1093
    uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
1094
    uint64_t kernel_entry, bootloader_run_addr;
1095
    PCIBus *pci_bus;
1096
    ISABus *isa_bus;
1097
    qemu_irq cbus_irq, i8259_irq;
1098
    I2CBus *smbus;
1099
    DriveInfo *dinfo;
1100
    int fl_idx = 0;
1101
    MaltaState *s;
1102
    PCIDevice *piix4;
1103
    DeviceState *dev;
1104

1105
    s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
1106
    sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
1107

1108
    /* create CPU */
1109
    mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
1110

1111
    /* allocate RAM */
1112
    if (ram_size > 2 * GiB) {
1113
        error_report("Too much memory for this machine: %" PRId64 "MB,"
1114
                     " maximum 2048MB", ram_size / MiB);
1115
        exit(1);
1116
    }
1117

1118
    /* register RAM at high address where it is undisturbed by IO */
1119
    memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
1120

1121
    /* alias for pre IO hole access */
1122
    memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
1123
                             machine->ram, 0, MIN(ram_size, 256 * MiB));
1124
    memory_region_add_subregion(system_memory, 0, ram_low_preio);
1125

1126
    /* alias for post IO hole access, if there is enough RAM */
1127
    if (ram_size > 512 * MiB) {
1128
        ram_low_postio = g_new(MemoryRegion, 1);
1129
        memory_region_init_alias(ram_low_postio, NULL,
1130
                                 "mips_malta_low_postio.ram",
1131
                                 machine->ram, 512 * MiB,
1132
                                 ram_size - 512 * MiB);
1133
        memory_region_add_subregion(system_memory, 512 * MiB,
1134
                                    ram_low_postio);
1135
    }
1136

1137
    /* FPGA */
1138

1139
    /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
1140
    malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2));
1141

1142
    /* Load firmware in flash / BIOS. */
1143
    dinfo = drive_get(IF_PFLASH, 0, fl_idx);
1144
    fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios",
1145
                               FLASH_SIZE,
1146
                               dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
1147
                               65536,
1148
                               4, 0x0000, 0x0000, 0x0000, 0x0000,
1149
                               TARGET_BIG_ENDIAN);
1150
    bios = pflash_cfi01_get_memory(fl);
1151
    fl_idx++;
1152
    if (kernel_filename) {
1153
        ram_low_size = MIN(ram_size, 256 * MiB);
1154
        bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
1155

1156
        /* Write a small bootloader to the flash location. */
1157
        loaderparams.ram_size = ram_size;
1158
        loaderparams.ram_low_size = ram_low_size;
1159
        loaderparams.kernel_filename = kernel_filename;
1160
        loaderparams.kernel_cmdline = kernel_cmdline;
1161
        loaderparams.initrd_filename = initrd_filename;
1162
        kernel_entry = load_kernel();
1163

1164
        if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
1165
            write_bootloader(memory_region_get_ram_ptr(bios),
1166
                             bootloader_run_addr, kernel_entry);
1167
        } else {
1168
            write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
1169
                                      bootloader_run_addr, kernel_entry);
1170
        }
1171
    } else {
1172
        target_long bios_size = FLASH_SIZE;
1173
        /* Load firmware from flash. */
1174
        if (!dinfo) {
1175
            /* Load a BIOS image. */
1176
            filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
1177
                                      machine->firmware ?: BIOS_FILENAME);
1178
            if (filename) {
1179
                bios_size = load_image_targphys(filename, FLASH_ADDRESS,
1180
                                                BIOS_SIZE);
1181
                g_free(filename);
1182
            } else {
1183
                bios_size = -1;
1184
            }
1185
            if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
1186
                machine->firmware && !qtest_enabled()) {
1187
                error_report("Could not load MIPS bios '%s'", machine->firmware);
1188
                exit(1);
1189
            }
1190
        }
1191
        /*
1192
         * In little endian mode the 32bit words in the bios are swapped,
1193
         * a neat trick which allows bi-endian firmware.
1194
         */
1195
#if !TARGET_BIG_ENDIAN
1196
        {
1197
            uint32_t *end, *addr;
1198
            const size_t swapsize = MIN(bios_size, 0x3e0000);
1199
            addr = rom_ptr(FLASH_ADDRESS, swapsize);
1200
            if (!addr) {
1201
                addr = memory_region_get_ram_ptr(bios);
1202
            }
1203
            end = (void *)addr + swapsize;
1204
            while (addr < end) {
1205
                bswap32s(addr);
1206
                addr++;
1207
            }
1208
        }
1209
#endif
1210
    }
1211

1212
    /*
1213
     * Map the BIOS at a 2nd physical location, as on the real board.
1214
     * Copy it so that we can patch in the MIPS revision, which cannot be
1215
     * handled by an overlapping region as the resulting ROM code subpage
1216
     * regions are not executable.
1217
     */
1218
    memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
1219
                           &error_fatal);
1220
    if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
1221
                  FLASH_ADDRESS, BIOS_SIZE)) {
1222
        memcpy(memory_region_get_ram_ptr(bios_copy),
1223
               memory_region_get_ram_ptr(bios), BIOS_SIZE);
1224
    }
1225
    memory_region_set_readonly(bios_copy, true);
1226
    memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
1227

1228
    /* Board ID = 0x420 (Malta Board with CoreLV) */
1229
    stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
1230

1231
    /* Northbridge */
1232
    dev = qdev_new("gt64120");
1233
    qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN);
1234
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1235
    pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
1236
    pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq);
1237

1238
    /* Southbridge */
1239
    piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE);
1240
    qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100);
1241
    pci_realize_and_unref(piix4, pci_bus, &error_fatal);
1242
    isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
1243

1244
    dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide"));
1245
    pci_ide_create_devs(PCI_DEVICE(dev));
1246

1247
    /* Interrupt controller */
1248
    qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq);
1249

1250
    /* generate SPD EEPROM data */
1251
    dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm"));
1252
    smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
1253
    generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
1254
    generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
1255
    smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
1256
    g_free(smbus_eeprom_buf);
1257

1258
    /* Super I/O: SMS FDC37M817 */
1259
    isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
1260

1261
    /* Network card */
1262
    network_init(pci_bus);
1263

1264
    /* Optional PCI video card */
1265
    pci_vga_init(pci_bus);
1266
}
1267

1268
static void mips_malta_instance_init(Object *obj)
1269
{
1270
    MaltaState *s = MIPS_MALTA(obj);
1271

1272
    s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
1273
    clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */
1274
}
1275

1276
static const TypeInfo mips_malta_device = {
1277
    .name          = TYPE_MIPS_MALTA,
1278
    .parent        = TYPE_SYS_BUS_DEVICE,
1279
    .instance_size = sizeof(MaltaState),
1280
    .instance_init = mips_malta_instance_init,
1281
};
1282

1283
GlobalProperty malta_compat[] = {
1284
    { "PIIX4_PM", "memory-hotplug-support", "off" },
1285
    { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
1286
    { "PIIX4_PM", "acpi-root-pci-hotplug", "off" },
1287
    { "PIIX4_PM", "x-not-migrate-acpi-index", "true" },
1288
};
1289
const size_t malta_compat_len = G_N_ELEMENTS(malta_compat);
1290

1291
static void mips_malta_machine_init(MachineClass *mc)
1292
{
1293
    mc->desc = "MIPS Malta Core LV";
1294
    mc->init = mips_malta_init;
1295
    mc->block_default_type = IF_IDE;
1296
    mc->max_cpus = 16;
1297
    mc->is_default = true;
1298
#ifdef TARGET_MIPS64
1299
    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
1300
#else
1301
    mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
1302
#endif
1303
    mc->default_ram_id = "mips_malta.ram";
1304
    compat_props_add(mc->compat_props, malta_compat, malta_compat_len);
1305
}
1306

1307
DEFINE_MACHINE("malta", mips_malta_machine_init)
1308

1309
static void mips_malta_register_types(void)
1310
{
1311
    type_register_static(&mips_malta_device);
1312
}
1313

1314
type_init(mips_malta_register_types)
1315