qemu

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/*
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 * Generic Loongson-3 Platform support
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 *
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 * Copyright (c) 2018-2020 Huacai Chen (chenhc@lemote.com)
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 * Copyright (c) 2018-2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
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 *
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 * This program is free software: you can redistribute it and/or modify
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 * it under the terms of the GNU General Public License as published by
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 * the Free Software Foundation, either version 2 of the License, or
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 * (at your option) any later version.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License
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 * along with this program. If not, see <https://www.gnu.org/licenses/>.
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 */
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/*
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 * Generic virtualized PC Platform based on Loongson-3 CPU (MIPS64R2 with
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 * extensions, 800~2000MHz)
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 */
25

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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/cutils.h"
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#include "qemu/datadir.h"
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#include "qapi/error.h"
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#include "elf.h"
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#include "hw/char/serial.h"
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#include "hw/intc/loongson_liointc.h"
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#include "hw/mips/mips.h"
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#include "hw/mips/fw_cfg.h"
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#include "hw/mips/loongson3_bootp.h"
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#include "hw/misc/unimp.h"
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#include "hw/intc/i8259.h"
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#include "hw/intc/loongson_ipi.h"
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#include "hw/loader.h"
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#include "hw/isa/superio.h"
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#include "hw/pci/msi.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/usb.h"
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#include "net/net.h"
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#include "sysemu/kvm.h"
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#include "sysemu/qtest.h"
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#include "sysemu/reset.h"
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#include "sysemu/runstate.h"
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#include "qemu/error-report.h"
53

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#define PM_CNTL_MODE          0x10
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#define LOONGSON_MAX_VCPUS      16
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/*
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 * Loongson-3's virtual machine BIOS can be obtained here:
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 * 1, https://github.com/loongson-community/firmware-nonfree
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 * 2, http://dev.lemote.com:8000/files/firmware/UEFI/KVM/bios_loongson3.bin
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 */
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#define LOONGSON3_BIOSNAME "bios_loongson3.bin"
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#define UART_IRQ            0
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#define RTC_IRQ             1
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#define PCIE_IRQ_BASE       2
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const MemMapEntry virt_memmap[] = {
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    [VIRT_LOWMEM] =      { 0x00000000,    0x10000000 },
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    [VIRT_PM] =          { 0x10080000,         0x100 },
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    [VIRT_FW_CFG] =      { 0x10080100,         0x100 },
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    [VIRT_RTC] =         { 0x10081000,        0x1000 },
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    [VIRT_PCIE_PIO] =    { 0x18000000,       0x80000 },
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    [VIRT_PCIE_ECAM] =   { 0x1a000000,     0x2000000 },
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    [VIRT_BIOS_ROM] =    { 0x1fc00000,      0x200000 },
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    [VIRT_UART] =        { 0x1fe001e0,           0x8 },
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    [VIRT_IPI] =         { 0x3ff01000,         0x400 },
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    [VIRT_LIOINTC] =     { 0x3ff01400,          0x64 },
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    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
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    [VIRT_HIGHMEM] =     { 0x80000000,           0x0 }, /* Variable */
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};
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static const MemMapEntry loader_memmap[] = {
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    [LOADER_KERNEL] =    { 0x00000000,     0x4000000 },
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    [LOADER_INITRD] =    { 0x04000000,           0x0 }, /* Variable */
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    [LOADER_CMDLINE] =   { 0x0ff00000,      0x100000 },
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};
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static const MemMapEntry loader_rommap[] = {
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    [LOADER_BOOTROM] =   { 0x1fc00000,        0x1000 },
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    [LOADER_PARAM] =     { 0x1fc01000,       0x10000 },
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};
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struct LoongsonMachineState {
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    MachineState parent_obj;
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    MemoryRegion *pio_alias;
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    MemoryRegion *mmio_alias;
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    MemoryRegion *ecam_alias;
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    MemoryRegion *core_iocsr[LOONGSON_MAX_VCPUS];
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};
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typedef struct LoongsonMachineState LoongsonMachineState;
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#define TYPE_LOONGSON_MACHINE  MACHINE_TYPE_NAME("loongson3-virt")
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DECLARE_INSTANCE_CHECKER(LoongsonMachineState, LOONGSON_MACHINE, TYPE_LOONGSON_MACHINE)
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static struct _loaderparams {
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    uint64_t cpu_freq;
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    uint64_t ram_size;
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    const char *kernel_cmdline;
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    const char *kernel_filename;
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    const char *initrd_filename;
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    uint64_t kernel_entry;
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    uint64_t a0, a1, a2;
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} loaderparams;
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static uint64_t loongson3_pm_read(void *opaque, hwaddr addr, unsigned size)
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{
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    return 0;
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}
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static void loongson3_pm_write(void *opaque, hwaddr addr,
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                               uint64_t val, unsigned size)
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{
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    if (addr != PM_CNTL_MODE) {
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        return;
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    }
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    switch (val) {
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    case 0x00:
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        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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        return;
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    case 0x01:
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        qemu_system_suspend_request();
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        return;
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    case 0xff:
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        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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        return;
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    default:
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        return;
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    }
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}
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static const MemoryRegionOps loongson3_pm_ops = {
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    .read  = loongson3_pm_read,
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    .write = loongson3_pm_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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    .valid = {
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        .min_access_size = 1,
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        .max_access_size = 1
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    }
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};
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#define DEF_LOONGSON3_FREQ (800 * 1000 * 1000)
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static uint64_t get_cpu_freq_hz(void)
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{
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#ifdef CONFIG_KVM
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    int ret;
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    uint64_t freq;
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    struct kvm_one_reg freq_reg = {
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        .id = KVM_REG_MIPS_COUNT_HZ,
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        .addr = (uintptr_t)(&freq)
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    };
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    if (kvm_enabled()) {
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        ret = kvm_vcpu_ioctl(first_cpu, KVM_GET_ONE_REG, &freq_reg);
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        if (ret >= 0) {
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            return freq * 2;
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        }
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    }
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#endif
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    return DEF_LOONGSON3_FREQ;
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}
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static void init_boot_param(void)
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{
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    static void *p;
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    struct boot_params *bp;
180

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    p = g_malloc0(loader_rommap[LOADER_PARAM].size);
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    bp = p;
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    bp->efi.smbios.vers = cpu_to_le16(1);
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    init_reset_system(&(bp->reset_system));
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    p += ROUND_UP(sizeof(struct boot_params), 64);
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    init_loongson_params(&(bp->efi.smbios.lp), p,
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                         loaderparams.cpu_freq, loaderparams.ram_size);
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    rom_add_blob_fixed("params_rom", bp,
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                       loader_rommap[LOADER_PARAM].size,
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                       loader_rommap[LOADER_PARAM].base);
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    g_free(bp);
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    loaderparams.a2 = cpu_mips_phys_to_kseg0(NULL,
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                                             loader_rommap[LOADER_PARAM].base);
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}
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static void init_boot_rom(void)
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{
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    const unsigned int boot_code[] = {
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        0x40086000,   /* mfc0    t0, CP0_STATUS                               */
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        0x240900E4,   /* li      t1, 0xe4         #set kx, sx, ux, erl        */
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        0x01094025,   /* or      t0, t0, t1                                   */
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        0x3C090040,   /* lui     t1, 0x40         #set bev                    */
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        0x01094025,   /* or      t0, t0, t1                                   */
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        0x40886000,   /* mtc0    t0, CP0_STATUS                               */
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        0x00000000,
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        0x40806800,   /* mtc0    zero, CP0_CAUSE                              */
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        0x00000000,
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        0x400A7801,   /* mfc0    t2, $15, 1                                   */
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        0x314A00FF,   /* andi    t2, 0x0ff                                    */
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        0x3C089000,   /* dli     t0, 0x900000003ff01000                       */
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        0x00084438,
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        0x35083FF0,
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        0x00084438,
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        0x35081000,
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        0x314B0003,   /* andi    t3, t2, 0x3      #local cpuid                */
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        0x000B5A00,   /* sll     t3, 8                                        */
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        0x010B4025,   /* or      t0, t0, t3                                   */
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        0x314C000C,   /* andi    t4, t2, 0xc      #node id                    */
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        0x000C62BC,   /* dsll    t4, 42                                       */
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        0x010C4025,   /* or      t0, t0, t4                                   */
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                      /* WaitForInit:                                         */
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        0xDD020020,   /* ld      v0, FN_OFF(t0)   #FN_OFF 0x020               */
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        0x1040FFFE,   /* beqz    v0, WaitForInit                              */
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        0x00000000,   /* nop                                                  */
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        0xDD1D0028,   /* ld      sp, SP_OFF(t0)   #FN_OFF 0x028               */
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        0xDD1C0030,   /* ld      gp, GP_OFF(t0)   #FN_OFF 0x030               */
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        0xDD050038,   /* ld      a1, A1_OFF(t0)   #FN_OFF 0x038               */
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        0x00400008,   /* jr      v0               #byebye                     */
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        0x00000000,   /* nop                                                  */
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        0x1000FFFF,   /* 1:  b   1b                                           */
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        0x00000000,   /* nop                                                  */
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                      /* Reset                                                */
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        0x3C0C9000,   /* dli     t0, 0x9000000010080010                       */
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        0x358C0000,
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        0x000C6438,
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        0x358C1008,
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        0x000C6438,
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        0x358C0010,
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        0x240D0000,   /* li      t1, 0x00                                     */
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        0xA18D0000,   /* sb      t1, (t0)                                     */
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        0x1000FFFF,   /* 1:  b   1b                                           */
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        0x00000000,   /* nop                                                  */
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                      /* Shutdown                                             */
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        0x3C0C9000,   /* dli     t0, 0x9000000010080010                       */
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        0x358C0000,
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        0x000C6438,
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        0x358C1008,
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        0x000C6438,
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        0x358C0010,
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        0x240D00FF,   /* li      t1, 0xff                                     */
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        0xA18D0000,   /* sb      t1, (t0)                                     */
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        0x1000FFFF,   /* 1:  b   1b                                           */
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        0x00000000,   /* nop                                                  */
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                      /* Suspend                                              */
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        0x3C0C9000,   /* dli     t0, 0x9000000010080010                       */
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        0x358C0000,
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        0x000C6438,
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        0x358C1008,
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        0x000C6438,
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        0x358C0010,
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        0x240D0001,   /* li      t1, 0x01                                     */
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        0xA18D0000,   /* sb      t1, (t0)                                     */
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        0x03e00008,   /* jr      ra                                           */
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        0x00000000    /* nop                                                  */
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    };
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    rom_add_blob_fixed("boot_rom", boot_code, sizeof(boot_code),
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                       loader_rommap[LOADER_BOOTROM].base);
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}
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static void fw_cfg_boot_set(void *opaque, const char *boot_device,
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                            Error **errp)
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{
280
    fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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}
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static void fw_conf_init(unsigned long ram_size)
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{
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    static const uint8_t suspend[6] = {128, 0, 0, 129, 128, 128};
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    FWCfgState *fw_cfg;
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    hwaddr cfg_addr = virt_memmap[VIRT_FW_CFG].base;
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    fw_cfg = fw_cfg_init_mem_wide(cfg_addr, cfg_addr + 8, 8, 0, NULL);
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    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)current_machine->smp.cpus);
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    fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)current_machine->smp.max_cpus);
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    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
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    fw_cfg_add_i32(fw_cfg, FW_CFG_MACHINE_VERSION, 1);
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    fw_cfg_add_i64(fw_cfg, FW_CFG_CPU_FREQ, get_cpu_freq_hz());
295

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    fw_cfg_add_file(fw_cfg, "etc/system-states",
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                    g_memdup2(suspend, sizeof(suspend)), sizeof(suspend));
298

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    qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
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}
301

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static int set_prom_cmdline(ram_addr_t initrd_offset, long initrd_size)
303
{
304
    int ret = 0;
305
    void *cmdline_buf;
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    hwaddr cmdline_vaddr;
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    unsigned int *parg_env;
308

309
    /* Allocate cmdline_buf for command line. */
310
    cmdline_buf = g_malloc0(loader_memmap[LOADER_CMDLINE].size);
311
    cmdline_vaddr = cpu_mips_phys_to_kseg0(NULL,
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                                           loader_memmap[LOADER_CMDLINE].base);
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    /*
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     * Layout of cmdline_buf looks like this:
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     * argv[0], argv[1], 0, env[0], env[1], ... env[i], 0,
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     * argv[0]'s data, argv[1]'s data, env[0]'data, ..., env[i]'s data, 0
318
     */
319
    parg_env = (void *)cmdline_buf;
320

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    ret = (3 + 1) * 4;
322
    *parg_env++ = cmdline_vaddr + ret;
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    ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "g"));
324

325
    /* argv1 */
326
    *parg_env++ = cmdline_vaddr + ret;
327
    if (initrd_size > 0)
328
        ret += (1 + snprintf(cmdline_buf + ret, 256 - ret,
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                "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s",
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                cpu_mips_phys_to_kseg0(NULL, initrd_offset),
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                initrd_size, loaderparams.kernel_cmdline));
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    else
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        ret += (1 + snprintf(cmdline_buf + ret, 256 - ret, "%s",
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                loaderparams.kernel_cmdline));
335

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    /* argv2 */
337
    *parg_env++ = cmdline_vaddr + 4 * ret;
338

339
    rom_add_blob_fixed("cmdline", cmdline_buf,
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                       loader_memmap[LOADER_CMDLINE].size,
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                       loader_memmap[LOADER_CMDLINE].base);
342

343
    g_free(cmdline_buf);
344

345
    loaderparams.a0 = 2;
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    loaderparams.a1 = cmdline_vaddr;
347

348
    return 0;
349
}
350

351
static uint64_t load_kernel(CPUMIPSState *env)
352
{
353
    long kernel_size;
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    ram_addr_t initrd_offset;
355
    uint64_t kernel_entry, kernel_low, kernel_high, initrd_size;
356

357
    kernel_size = load_elf(loaderparams.kernel_filename, NULL,
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                           cpu_mips_kseg0_to_phys, NULL,
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                           &kernel_entry,
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                           &kernel_low, &kernel_high,
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                           NULL, 0, EM_MIPS, 1, 0);
362
    if (kernel_size < 0) {
363
        error_report("could not load kernel '%s': %s",
364
                     loaderparams.kernel_filename,
365
                     load_elf_strerror(kernel_size));
366
        exit(1);
367
    }
368

369
    /* load initrd */
370
    initrd_size = 0;
371
    initrd_offset = 0;
372
    if (loaderparams.initrd_filename) {
373
        initrd_size = get_image_size(loaderparams.initrd_filename);
374
        if (initrd_size > 0) {
375
            initrd_offset = MAX(loader_memmap[LOADER_INITRD].base,
376
                                ROUND_UP(kernel_high, INITRD_PAGE_SIZE));
377

378
            if (initrd_offset + initrd_size > loaderparams.ram_size) {
379
                error_report("memory too small for initial ram disk '%s'",
380
                             loaderparams.initrd_filename);
381
                exit(1);
382
            }
383

384
            initrd_size = load_image_targphys(loaderparams.initrd_filename,
385
                                              initrd_offset,
386
                                              loaderparams.ram_size - initrd_offset);
387
        }
388

389
        if (initrd_size == (target_ulong) -1) {
390
            error_report("could not load initial ram disk '%s'",
391
                         loaderparams.initrd_filename);
392
            exit(1);
393
        }
394
    }
395

396
    /* Setup prom cmdline. */
397
    set_prom_cmdline(initrd_offset, initrd_size);
398

399
    return kernel_entry;
400
}
401

402
static void main_cpu_reset(void *opaque)
403
{
404
    MIPSCPU *cpu = opaque;
405
    CPUMIPSState *env = &cpu->env;
406

407
    cpu_reset(CPU(cpu));
408

409
    /* Loongson-3 reset stuff */
410
    if (loaderparams.kernel_filename) {
411
        if (cpu == MIPS_CPU(first_cpu)) {
412
            env->active_tc.gpr[4] = loaderparams.a0;
413
            env->active_tc.gpr[5] = loaderparams.a1;
414
            env->active_tc.gpr[6] = loaderparams.a2;
415
            env->active_tc.PC = loaderparams.kernel_entry;
416
        }
417
        env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
418
    }
419
}
420

421
static inline void loongson3_virt_devices_init(MachineState *machine,
422
                                               DeviceState *pic)
423
{
424
    int i;
425
    qemu_irq irq;
426
    PCIBus *pci_bus;
427
    DeviceState *dev;
428
    MemoryRegion *mmio_reg, *ecam_reg;
429
    MachineClass *mc = MACHINE_GET_CLASS(machine);
430
    LoongsonMachineState *s = LOONGSON_MACHINE(machine);
431

432
    dev = qdev_new(TYPE_GPEX_HOST);
433
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
434
    pci_bus = PCI_HOST_BRIDGE(dev)->bus;
435

436
    s->ecam_alias = g_new0(MemoryRegion, 1);
437
    ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
438
    memory_region_init_alias(s->ecam_alias, OBJECT(dev), "pcie-ecam",
439
                             ecam_reg, 0, virt_memmap[VIRT_PCIE_ECAM].size);
440
    memory_region_add_subregion(get_system_memory(),
441
                                virt_memmap[VIRT_PCIE_ECAM].base,
442
                                s->ecam_alias);
443

444
    s->mmio_alias = g_new0(MemoryRegion, 1);
445
    mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
446
    memory_region_init_alias(s->mmio_alias, OBJECT(dev), "pcie-mmio",
447
                             mmio_reg, virt_memmap[VIRT_PCIE_MMIO].base,
448
                             virt_memmap[VIRT_PCIE_MMIO].size);
449
    memory_region_add_subregion(get_system_memory(),
450
                                virt_memmap[VIRT_PCIE_MMIO].base,
451
                                s->mmio_alias);
452

453
    s->pio_alias = g_new0(MemoryRegion, 1);
454
    memory_region_init_alias(s->pio_alias, OBJECT(dev), "pcie-pio",
455
                             get_system_io(), 0,
456
                             virt_memmap[VIRT_PCIE_PIO].size);
457
    memory_region_add_subregion(get_system_memory(),
458
                                virt_memmap[VIRT_PCIE_PIO].base, s->pio_alias);
459
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, virt_memmap[VIRT_PCIE_PIO].base);
460

461
    for (i = 0; i < GPEX_NUM_IRQS; i++) {
462
        irq = qdev_get_gpio_in(pic, PCIE_IRQ_BASE + i);
463
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
464
        gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ_BASE + i);
465
    }
466
    msi_nonbroken = true;
467

468
    pci_vga_init(pci_bus);
469

470
    if (defaults_enabled() && object_class_by_name("pci-ohci")) {
471
        USBBus *usb_bus;
472

473
        pci_create_simple(pci_bus, -1, "pci-ohci");
474
        usb_bus = USB_BUS(object_resolve_type_unambiguous(TYPE_USB_BUS,
475
                                                          &error_abort));
476
        usb_create_simple(usb_bus, "usb-kbd");
477
        usb_create_simple(usb_bus, "usb-tablet");
478
    }
479

480
    pci_init_nic_devices(pci_bus, mc->default_nic);
481
}
482

483
static void mips_loongson3_virt_init(MachineState *machine)
484
{
485
    int i;
486
    long bios_size;
487
    MIPSCPU *cpu;
488
    Clock *cpuclk;
489
    CPUMIPSState *env;
490
    DeviceState *liointc;
491
    DeviceState *ipi = NULL;
492
    char *filename;
493
    const char *kernel_cmdline = machine->kernel_cmdline;
494
    const char *kernel_filename = machine->kernel_filename;
495
    const char *initrd_filename = machine->initrd_filename;
496
    ram_addr_t ram_size = machine->ram_size;
497
    LoongsonMachineState *s = LOONGSON_MACHINE(machine);
498
    MemoryRegion *address_space_mem = get_system_memory();
499
    MemoryRegion *ram = g_new(MemoryRegion, 1);
500
    MemoryRegion *bios = g_new(MemoryRegion, 1);
501
    MemoryRegion *iomem = g_new(MemoryRegion, 1);
502
    MemoryRegion *iocsr = g_new(MemoryRegion, 1);
503

504
    /* TODO: TCG will support all CPU types */
505
    if (!kvm_enabled()) {
506
        if (!machine->cpu_type) {
507
            machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A1000");
508
        }
509
        if (!cpu_type_supports_isa(machine->cpu_type, INSN_LOONGSON3A)) {
510
            error_report("Loongson-3/TCG needs a Loongson-3 series cpu");
511
            exit(1);
512
        }
513
    } else {
514
        if (!machine->cpu_type) {
515
            machine->cpu_type = MIPS_CPU_TYPE_NAME("Loongson-3A4000");
516
        }
517
        if (!strstr(machine->cpu_type, "Loongson-3A4000")) {
518
            error_report("Loongson-3/KVM needs cpu type Loongson-3A4000");
519
            exit(1);
520
        }
521
    }
522

523
    if (ram_size < 512 * MiB) {
524
        error_report("Loongson-3 machine needs at least 512MB memory");
525
        exit(1);
526
    }
527

528
    /*
529
     * The whole MMIO range among configure registers doesn't generate
530
     * exception when accessing invalid memory. Create some unimplememted
531
     * devices to emulate this feature.
532
     */
533
    create_unimplemented_device("mmio fallback 0", 0x10000000, 256 * MiB);
534
    create_unimplemented_device("mmio fallback 1", 0x30000000, 256 * MiB);
535

536
    memory_region_init(iocsr, OBJECT(machine), "loongson3.iocsr", UINT32_MAX);
537

538
    /* IPI controller is in kernel for KVM */
539
    if (!kvm_enabled()) {
540
        ipi = qdev_new(TYPE_LOONGSON_IPI);
541
        qdev_prop_set_uint32(ipi, "num-cpu", machine->smp.cpus);
542
        sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal);
543
        memory_region_add_subregion(iocsr, SMP_IPI_MAILBOX,
544
                                sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0));
545
        memory_region_add_subregion(iocsr, MAIL_SEND_ADDR,
546
                                sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1));
547
    }
548

549
    liointc = qdev_new("loongson.liointc");
550
    sysbus_realize_and_unref(SYS_BUS_DEVICE(liointc), &error_fatal);
551

552
    sysbus_mmio_map(SYS_BUS_DEVICE(liointc), 0, virt_memmap[VIRT_LIOINTC].base);
553

554
    serial_mm_init(address_space_mem, virt_memmap[VIRT_UART].base, 0,
555
                   qdev_get_gpio_in(liointc, UART_IRQ), 115200, serial_hd(0),
556
                   DEVICE_NATIVE_ENDIAN);
557

558
    sysbus_create_simple("goldfish_rtc", virt_memmap[VIRT_RTC].base,
559
                         qdev_get_gpio_in(liointc, RTC_IRQ));
560

561
    cpuclk = clock_new(OBJECT(machine), "cpu-refclk");
562
    clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ);
563

564
    for (i = 0; i < machine->smp.cpus; i++) {
565
        int node = i / LOONGSON3_CORE_PER_NODE;
566
        int core = i % LOONGSON3_CORE_PER_NODE;
567
        int ip;
568

569
        /* init CPUs */
570
        cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk);
571

572
        /* Init internal devices */
573
        cpu_mips_irq_init_cpu(cpu);
574
        cpu_mips_clock_init(cpu);
575
        qemu_register_reset(main_cpu_reset, cpu);
576

577
        if (!kvm_enabled()) {
578
            hwaddr base = ((hwaddr)node << 44) + virt_memmap[VIRT_IPI].base;
579
            base += core * 0x100;
580
            qdev_connect_gpio_out(ipi, i, cpu->env.irq[6]);
581
            sysbus_mmio_map(SYS_BUS_DEVICE(ipi), i + 2, base);
582
        }
583

584
        if (ase_lcsr_available(&MIPS_CPU(cpu)->env)) {
585
            MemoryRegion *core_iocsr = g_new(MemoryRegion, 1);
586
            g_autofree char *name = g_strdup_printf("core%d_iocsr", i);
587
            memory_region_init_alias(core_iocsr, OBJECT(cpu), name,
588
                                     iocsr, 0, UINT32_MAX);
589
            memory_region_add_subregion(&MIPS_CPU(cpu)->env.iocsr.mr,
590
                                        0, core_iocsr);
591
            s->core_iocsr[i] = core_iocsr;
592
        }
593

594
        if (node > 0) {
595
            continue; /* Only node-0 can be connected to LIOINTC */
596
        }
597

598
        for (ip = 0; ip < 4 ; ip++) {
599
            int pin = core * LOONGSON3_CORE_PER_NODE + ip;
600
            sysbus_connect_irq(SYS_BUS_DEVICE(liointc),
601
                               pin, cpu->env.irq[ip + 2]);
602
        }
603
    }
604
    env = &MIPS_CPU(first_cpu)->env;
605

606
    /* Allocate RAM/BIOS, 0x00000000~0x10000000 is alias of 0x80000000~0x90000000 */
607
    memory_region_init_rom(bios, NULL, "loongson3.bios",
608
                           virt_memmap[VIRT_BIOS_ROM].size, &error_fatal);
609
    memory_region_init_alias(ram, NULL, "loongson3.lowmem",
610
                           machine->ram, 0, virt_memmap[VIRT_LOWMEM].size);
611
    memory_region_init_io(iomem, NULL, &loongson3_pm_ops,
612
                           NULL, "loongson3_pm", virt_memmap[VIRT_PM].size);
613
    qemu_register_wakeup_support();
614

615
    memory_region_add_subregion(address_space_mem,
616
                      virt_memmap[VIRT_LOWMEM].base, ram);
617
    memory_region_add_subregion(address_space_mem,
618
                      virt_memmap[VIRT_BIOS_ROM].base, bios);
619
    memory_region_add_subregion(address_space_mem,
620
                      virt_memmap[VIRT_HIGHMEM].base, machine->ram);
621
    memory_region_add_subregion(address_space_mem,
622
                      virt_memmap[VIRT_PM].base, iomem);
623

624
    /*
625
     * We do not support flash operation, just loading bios.bin as raw BIOS.
626
     * Please use -L to set the BIOS path and -bios to set bios name.
627
     */
628

629
    if (kernel_filename) {
630
        loaderparams.cpu_freq = get_cpu_freq_hz();
631
        loaderparams.ram_size = ram_size;
632
        loaderparams.kernel_filename = kernel_filename;
633
        loaderparams.kernel_cmdline = kernel_cmdline;
634
        loaderparams.initrd_filename = initrd_filename;
635
        loaderparams.kernel_entry = load_kernel(env);
636

637
        init_boot_rom();
638
        init_boot_param();
639
    } else {
640
        filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
641
                                  machine->firmware ?: LOONGSON3_BIOSNAME);
642
        if (filename) {
643
            bios_size = load_image_targphys(filename,
644
                                            virt_memmap[VIRT_BIOS_ROM].base,
645
                                            virt_memmap[VIRT_BIOS_ROM].size);
646
            g_free(filename);
647
        } else {
648
            bios_size = -1;
649
        }
650

651
        if ((bios_size < 0 || bios_size > virt_memmap[VIRT_BIOS_ROM].size) &&
652
            !kernel_filename && !qtest_enabled()) {
653
            error_report("Could not load MIPS bios '%s'", machine->firmware);
654
            exit(1);
655
        }
656

657
        fw_conf_init(ram_size);
658
    }
659

660
    loongson3_virt_devices_init(machine, liointc);
661
}
662

663
static void loongson3v_machine_class_init(ObjectClass *oc, void *data)
664
{
665
    MachineClass *mc = MACHINE_CLASS(oc);
666

667
    mc->desc = "Loongson-3 Virtualization Platform";
668
    mc->init = mips_loongson3_virt_init;
669
    mc->block_default_type = IF_IDE;
670
    mc->max_cpus = LOONGSON_MAX_VCPUS;
671
    mc->default_ram_id = "loongson3.highram";
672
    mc->default_ram_size = 1600 * MiB;
673
    mc->minimum_page_bits = 14;
674
    mc->default_nic = "virtio-net-pci";
675
}
676

677
static const TypeInfo loongson3_machine_types[] = {
678
    {
679
        .name           = TYPE_LOONGSON_MACHINE,
680
        .parent         = TYPE_MACHINE,
681
        .instance_size  = sizeof(LoongsonMachineState),
682
        .class_init     = loongson3v_machine_class_init,
683
    }
684
};
685

686
DEFINE_TYPES(loongson3_machine_types)
687