qemu

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/*
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 * Utility for QEMU MIPS to generate it's simple bootloader
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 *
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 * Instructions used here are carefully selected to keep compatibility with
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 * MIPS Release 6.
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 *
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 * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
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 *
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 */
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "cpu.h"
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#include "hw/mips/bootloader.h"
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typedef enum bl_reg {
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    BL_REG_ZERO = 0,
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    BL_REG_AT = 1,
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    BL_REG_V0 = 2,
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    BL_REG_V1 = 3,
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    BL_REG_A0 = 4,
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    BL_REG_A1 = 5,
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    BL_REG_A2 = 6,
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    BL_REG_A3 = 7,
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    BL_REG_T0 = 8,
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    BL_REG_T1 = 9,
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    BL_REG_T2 = 10,
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    BL_REG_T3 = 11,
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    BL_REG_T4 = 12,
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    BL_REG_T5 = 13,
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    BL_REG_T6 = 14,
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    BL_REG_T7 = 15,
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    BL_REG_S0 = 16,
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    BL_REG_S1 = 17,
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    BL_REG_S2 = 18,
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    BL_REG_S3 = 19,
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    BL_REG_S4 = 20,
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    BL_REG_S5 = 21,
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    BL_REG_S6 = 22,
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    BL_REG_S7 = 23,
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    BL_REG_T8 = 24,
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    BL_REG_T9 = 25,
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    BL_REG_K0 = 26,
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    BL_REG_K1 = 27,
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    BL_REG_GP = 28,
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    BL_REG_SP = 29,
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    BL_REG_FP = 30,
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    BL_REG_RA = 31,
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} bl_reg;
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static bool bootcpu_supports_isa(uint64_t isa_mask)
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{
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    return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask);
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}
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static void st_nm32_p(void **ptr, uint32_t insn)
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{
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    uint16_t *p = *ptr;
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    stw_p(p, insn >> 16);
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    p++;
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    stw_p(p, insn >> 0);
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    p++;
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    *ptr = p;
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}
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/* Base types */
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static void bl_gen_nop(void **ptr)
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{
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    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
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        st_nm32_p(ptr, 0x8000c000);
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    } else {
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        uint32_t *p = *ptr;
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        stl_p(p, 0);
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        p++;
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        *ptr = p;
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    }
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}
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static void bl_gen_r_type(void **ptr, uint8_t opcode,
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                          bl_reg rs, bl_reg rt, bl_reg rd,
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                          uint8_t shift, uint8_t funct)
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{
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    uint32_t *p = *ptr;
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    uint32_t insn = 0;
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    insn = deposit32(insn, 26, 6, opcode);
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    insn = deposit32(insn, 21, 5, rs);
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    insn = deposit32(insn, 16, 5, rt);
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    insn = deposit32(insn, 11, 5, rd);
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    insn = deposit32(insn, 6, 5, shift);
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    insn = deposit32(insn, 0, 6, funct);
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    stl_p(p, insn);
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    p++;
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    *ptr = p;
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}
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static void bl_gen_i_type(void **ptr, uint8_t opcode,
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                          bl_reg rs, bl_reg rt, uint16_t imm)
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{
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    uint32_t *p = *ptr;
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    uint32_t insn = 0;
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    insn = deposit32(insn, 26, 6, opcode);
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    insn = deposit32(insn, 21, 5, rs);
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    insn = deposit32(insn, 16, 5, rt);
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    insn = deposit32(insn, 0, 16, imm);
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    stl_p(p, insn);
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    p++;
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    *ptr = p;
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}
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/* Single instructions */
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static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
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{
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    if (bootcpu_supports_isa(ISA_MIPS3)) {
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        bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
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    } else {
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        g_assert_not_reached(); /* unsupported */
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    }
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}
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static void bl_gen_jalr(void **p, bl_reg rs)
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{
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    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
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        uint32_t insn = 0;
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        insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */
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        insn = deposit32(insn, 21, 5, BL_REG_RA);
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        insn = deposit32(insn, 16, 5, rs);
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        st_nm32_p(p, insn);
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    } else {
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        bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
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    }
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}
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static void bl_gen_lui_nm(void **ptr, bl_reg rt, uint32_t imm20)
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{
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    uint32_t insn = 0;
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    assert(extract32(imm20, 0, 20) == imm20);
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    insn = deposit32(insn, 26, 6, 0b111000);
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    insn = deposit32(insn, 21, 5, rt);
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    insn = deposit32(insn, 12, 9, extract32(imm20, 0, 9));
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    insn = deposit32(insn, 2, 10, extract32(imm20, 9, 10));
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    insn = deposit32(insn, 0, 1, sextract32(imm20, 19, 1));
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    st_nm32_p(ptr, insn);
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}
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static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
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{
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    /* R6: It's a alias of AUI with RS = 0 */
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    bl_gen_i_type(p, 0x0f, 0, rt, imm);
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}
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static void bl_gen_ori_nm(void **ptr, bl_reg rt, bl_reg rs, uint16_t imm12)
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{
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    uint32_t insn = 0;
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    assert(extract32(imm12, 0, 12) == imm12);
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    insn = deposit32(insn, 26, 6, 0b100000);
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    insn = deposit32(insn, 21, 5, rt);
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    insn = deposit32(insn, 16, 5, rs);
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    insn = deposit32(insn, 0, 12, imm12);
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    st_nm32_p(ptr, insn);
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}
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static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
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{
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    bl_gen_i_type(p, 0x0d, rs, rt, imm);
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}
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static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12)
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{
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    uint32_t insn = 0;
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    assert(extract32(ofs12, 0, 12) == ofs12);
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    insn = deposit32(insn, 26, 6, 0b100001);
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    insn = deposit32(insn, 21, 5, rt);
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    insn = deposit32(insn, 16, 5, rs);
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    insn = deposit32(insn, 12, 4, 0b1001);
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    insn = deposit32(insn, 0, 12, ofs12);
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    st_nm32_p(ptr, insn);
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}
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static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
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{
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    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
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        bl_gen_sw_nm(p, rt, base, offset);
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    } else {
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        bl_gen_i_type(p, 0x2b, base, rt, offset);
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    }
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}
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static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
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{
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    if (bootcpu_supports_isa(ISA_MIPS3)) {
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        bl_gen_i_type(p, 0x3f, base, rt, offset);
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    } else {
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        g_assert_not_reached(); /* unsupported */
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    }
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}
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/* Pseudo instructions */
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static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
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{
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    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
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        bl_gen_lui_nm(p, rt, extract32(imm, 12, 20));
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        bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12));
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    } else {
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        bl_gen_lui(p, rt, extract32(imm, 16, 16));
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        bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
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    }
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}
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static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
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{
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    bl_gen_li(p, rt, extract64(imm, 32, 32));
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    bl_gen_dsll(p, rt, rt, 16);
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    bl_gen_ori(p, rt, rt, extract64(imm, 16, 16));
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    bl_gen_dsll(p, rt, rt, 16);
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    bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
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}
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static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm)
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{
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    if (bootcpu_supports_isa(ISA_MIPS3)) {
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        bl_gen_dli(p, rt, imm); /* 64bit */
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    } else {
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        bl_gen_li(p, rt, imm); /* 32bit */
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    }
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}
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/* Helpers */
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void bl_gen_jump_to(void **p, target_ulong jump_addr)
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{
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    bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
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    bl_gen_jalr(p, BL_REG_T9);
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    bl_gen_nop(p); /* delay slot */
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}
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void bl_gen_jump_kernel(void **p,
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                        bool set_sp, target_ulong sp,
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                        bool set_a0, target_ulong a0,
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                        bool set_a1, target_ulong a1,
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                        bool set_a2, target_ulong a2,
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                        bool set_a3, target_ulong a3,
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                        target_ulong kernel_addr)
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{
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    if (set_sp) {
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        bl_gen_load_ulong(p, BL_REG_SP, sp);
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    }
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    if (set_a0) {
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        bl_gen_load_ulong(p, BL_REG_A0, a0);
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    }
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    if (set_a1) {
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        bl_gen_load_ulong(p, BL_REG_A1, a1);
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    }
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    if (set_a2) {
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        bl_gen_load_ulong(p, BL_REG_A2, a2);
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    }
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    if (set_a3) {
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        bl_gen_load_ulong(p, BL_REG_A3, a3);
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    }
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    bl_gen_jump_to(p, kernel_addr);
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}
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void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val)
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{
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    bl_gen_load_ulong(p, BL_REG_K0, val);
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    bl_gen_load_ulong(p, BL_REG_K1, addr);
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    if (bootcpu_supports_isa(ISA_MIPS3)) {
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        bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
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    } else {
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        bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
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    }
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}
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void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val)
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{
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    bl_gen_li(p, BL_REG_K0, val);
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    bl_gen_load_ulong(p, BL_REG_K1, addr);
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    bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
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}
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void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val)
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{
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    bl_gen_dli(p, BL_REG_K0, val);
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    bl_gen_load_ulong(p, BL_REG_K1, addr);
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    bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
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}
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