qemu

1
/*
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 * QEMU PIIX PCI ISA Bridge Emulation
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 *
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 * Copyright (c) 2006 Fabrice Bellard
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 * Copyright (c) 2018 Hervé Poussineau
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "qemu/range.h"
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#include "qapi/error.h"
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#include "hw/dma/i8257.h"
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#include "hw/southbridge/piix.h"
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#include "hw/timer/i8254.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/ide/piix.h"
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#include "hw/intc/i8259.h"
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#include "hw/isa/isa.h"
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#include "sysemu/runstate.h"
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#include "migration/vmstate.h"
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#include "hw/acpi/acpi_aml_interface.h"
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static void piix_set_irq_pic(PIIXState *s, int pic_irq)
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{
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    qemu_set_irq(s->isa_irqs_in[pic_irq],
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                 !!(s->pic_levels &
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                    (((1ULL << PIIX_NUM_PIRQS) - 1) <<
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                     (pic_irq * PIIX_NUM_PIRQS))));
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}
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static void piix_set_pci_irq_level_internal(PIIXState *s, int pirq, int level)
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{
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    int pic_irq;
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    uint64_t mask;
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    pic_irq = s->dev.config[PIIX_PIRQCA + pirq];
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    if (pic_irq >= ISA_NUM_IRQS) {
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        return;
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    }
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    mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
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    s->pic_levels &= ~mask;
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    s->pic_levels |= mask * !!level;
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}
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static void piix_set_pci_irq_level(PIIXState *s, int pirq, int level)
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{
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    int pic_irq;
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    pic_irq = s->dev.config[PIIX_PIRQCA + pirq];
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    if (pic_irq >= ISA_NUM_IRQS) {
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        return;
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    }
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    piix_set_pci_irq_level_internal(s, pirq, level);
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    piix_set_irq_pic(s, pic_irq);
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}
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static void piix_set_pci_irq(void *opaque, int pirq, int level)
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{
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    PIIXState *s = opaque;
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    piix_set_pci_irq_level(s, pirq, level);
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}
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static void piix_request_i8259_irq(void *opaque, int irq, int level)
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{
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    PIIXState *s = opaque;
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    qemu_set_irq(s->cpu_intr, level);
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}
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static PCIINTxRoute piix_route_intx_pin_to_irq(void *opaque, int pin)
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{
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    PCIDevice *pci_dev = opaque;
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    int irq = pci_dev->config[PIIX_PIRQCA + pin];
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    PCIINTxRoute route;
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    if (irq < ISA_NUM_IRQS) {
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        route.mode = PCI_INTX_ENABLED;
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        route.irq = irq;
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    } else {
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        route.mode = PCI_INTX_DISABLED;
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        route.irq = -1;
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    }
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    return route;
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}
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/* irq routing is changed. so rebuild bitmap */
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static void piix_update_pci_irq_levels(PIIXState *s)
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{
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    PCIBus *bus = pci_get_bus(&s->dev);
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    int pirq;
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    s->pic_levels = 0;
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    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
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        piix_set_pci_irq_level(s, pirq, pci_bus_get_irq_level(bus, pirq));
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    }
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}
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static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t val,
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                              int len)
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{
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    pci_default_write_config(dev, address, val, len);
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    if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
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        PIIXState *s = PIIX_PCI_DEVICE(dev);
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        int pic_irq;
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        pci_bus_fire_intx_routing_notifier(pci_get_bus(&s->dev));
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        piix_update_pci_irq_levels(s);
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        for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
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            piix_set_irq_pic(s, pic_irq);
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        }
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    }
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}
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static void piix_reset(DeviceState *dev)
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{
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    PIIXState *d = PIIX_PCI_DEVICE(dev);
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    uint8_t *pci_conf = d->dev.config;
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    pci_conf[0x04] = 0x07; /* master, memory and I/O */
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    pci_conf[0x05] = 0x00;
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    pci_conf[0x06] = 0x00;
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    pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
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    pci_conf[0x4c] = 0x4d;
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    pci_conf[0x4e] = 0x03;
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    pci_conf[0x4f] = 0x00;
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    pci_conf[0x60] = 0x80;
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    pci_conf[0x61] = 0x80;
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    pci_conf[0x62] = 0x80;
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    pci_conf[0x63] = 0x80;
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    pci_conf[0x69] = 0x02;
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    pci_conf[0x70] = 0x80;
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    pci_conf[0x76] = 0x0c;
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    pci_conf[0x77] = 0x0c;
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    pci_conf[0x78] = 0x02;
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    pci_conf[0x79] = 0x00;
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    pci_conf[0x80] = 0x00;
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    pci_conf[0x82] = 0x00;
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    pci_conf[0xa0] = 0x08;
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    pci_conf[0xa2] = 0x00;
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    pci_conf[0xa3] = 0x00;
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    pci_conf[0xa4] = 0x00;
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    pci_conf[0xa5] = 0x00;
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    pci_conf[0xa6] = 0x00;
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    pci_conf[0xa7] = 0x00;
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    pci_conf[0xa8] = 0x0f;
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    pci_conf[0xaa] = 0x00;
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    pci_conf[0xab] = 0x00;
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    pci_conf[0xac] = 0x00;
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    pci_conf[0xae] = 0x00;
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    d->pic_levels = 0;
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    d->rcr = 0;
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}
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static int piix_post_load(void *opaque, int version_id)
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{
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    PIIXState *s = opaque;
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    int pirq;
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    /*
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     * Because the i8259 has not been deserialized yet, qemu_irq_raise
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     * might bring the system to a different state than the saved one;
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     * for example, the interrupt could be masked but the i8259 would
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     * not know that yet and would trigger an interrupt in the CPU.
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     *
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     * Here, we update irq levels without raising the interrupt.
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     * Interrupt state will be deserialized separately through the i8259.
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     */
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    s->pic_levels = 0;
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    for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
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        piix_set_pci_irq_level_internal(s, pirq,
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            pci_bus_get_irq_level(pci_get_bus(&s->dev), pirq));
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    }
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    return 0;
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}
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static int piix4_post_load(void *opaque, int version_id)
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{
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    PIIXState *s = opaque;
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    if (version_id == 2) {
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        s->rcr = 0;
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    }
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    return piix_post_load(opaque, version_id);
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}
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static int piix3_pre_save(void *opaque)
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{
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    int i;
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    PIIXState *piix3 = opaque;
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    for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
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        piix3->pci_irq_levels_vmstate[i] =
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            pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
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    }
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    return 0;
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}
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static bool piix3_rcr_needed(void *opaque)
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{
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    PIIXState *piix3 = opaque;
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    return (piix3->rcr != 0);
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}
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static const VMStateDescription vmstate_piix3_rcr = {
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    .name = "PIIX3/rcr",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .needed = piix3_rcr_needed,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT8(rcr, PIIXState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static const VMStateDescription vmstate_piix3 = {
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    .name = "PIIX3",
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    .version_id = 3,
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    .minimum_version_id = 2,
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    .post_load = piix_post_load,
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    .pre_save = piix3_pre_save,
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    .fields = (const VMStateField[]) {
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        VMSTATE_PCI_DEVICE(dev, PIIXState),
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        VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState,
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                              PIIX_NUM_PIRQS, 3),
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        VMSTATE_END_OF_LIST()
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    },
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    .subsections = (const VMStateDescription * const []) {
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        &vmstate_piix3_rcr,
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        NULL
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    }
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};
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static const VMStateDescription vmstate_piix4 = {
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    .name = "PIIX4",
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    .version_id = 3,
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    .minimum_version_id = 2,
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    .post_load = piix4_post_load,
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    .fields = (const VMStateField[]) {
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        VMSTATE_PCI_DEVICE(dev, PIIXState),
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        VMSTATE_UINT8_V(rcr, PIIXState, 3),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
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{
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    PIIXState *d = opaque;
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    if (val & 4) {
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        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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        return;
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    }
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    d->rcr = val & 2; /* keep System Reset type only */
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}
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static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
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{
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    PIIXState *d = opaque;
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    return d->rcr;
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}
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static const MemoryRegionOps rcr_ops = {
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    .read = rcr_read,
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    .write = rcr_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .impl = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    },
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};
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static void pci_piix_realize(PCIDevice *dev, const char *uhci_type,
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                             Error **errp)
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{
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    PIIXState *d = PIIX_PCI_DEVICE(dev);
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    PCIBus *pci_bus = pci_get_bus(dev);
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    ISABus *isa_bus;
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    uint32_t irq;
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    isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
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                          pci_address_space_io(dev), errp);
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    if (!isa_bus) {
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        return;
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    }
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    memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
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                          "piix-reset-control", 1);
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    memory_region_add_subregion_overlap(pci_address_space_io(dev),
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                                        PIIX_RCR_IOPORT, &d->rcr_mem, 1);
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    /* PIC */
317
    if (d->has_pic) {
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        qemu_irq *i8259_out_irq = qemu_allocate_irqs(piix_request_i8259_irq, d,
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                                                     1);
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        qemu_irq *i8259 = i8259_init(isa_bus, *i8259_out_irq);
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        size_t i;
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        for (i = 0; i < ISA_NUM_IRQS; i++) {
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            d->isa_irqs_in[i] = i8259[i];
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        }
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327
        g_free(i8259);
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        qdev_init_gpio_out_named(DEVICE(dev), &d->cpu_intr, "intr", 1);
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    }
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    isa_bus_register_input_irqs(isa_bus, d->isa_irqs_in);
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    /* PIT */
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    if (d->has_pit) {
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        i8254_pit_init(isa_bus, 0x40, 0, NULL);
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    }
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    i8257_dma_init(OBJECT(dev), isa_bus, 0);
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    /* RTC */
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    qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000);
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    if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
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        return;
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    }
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    irq = object_property_get_uint(OBJECT(&d->rtc), "irq", &error_fatal);
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    isa_connect_gpio_out(ISA_DEVICE(&d->rtc), 0, irq);
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    /* IDE */
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    qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1);
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    if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) {
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        return;
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    }
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    /* USB */
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    if (d->has_usb) {
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        object_initialize_child(OBJECT(dev), "uhci", &d->uhci, uhci_type);
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        qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
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        if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
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            return;
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        }
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    }
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    /* Power Management */
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    if (d->has_acpi) {
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        object_initialize_child(OBJECT(d), "pm", &d->pm, TYPE_PIIX4_PM);
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        qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3);
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        qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", d->smb_io_base);
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        qdev_prop_set_bit(DEVICE(&d->pm), "smm-enabled", d->smm_enabled);
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        if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) {
371
            return;
372
        }
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        qdev_connect_gpio_out(DEVICE(&d->pm), 0, d->isa_irqs_in[9]);
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    }
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    pci_bus_irqs(pci_bus, piix_set_pci_irq, d, PIIX_NUM_PIRQS);
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    pci_bus_set_route_irq_fn(pci_bus, piix_route_intx_pin_to_irq);
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}
379

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static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
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{
382
    Aml *field;
383
    Aml *sb_scope = aml_scope("\\_SB");
384
    BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
385

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    /* PIIX PCI to ISA irq remapping */
387
    aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG,
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                                           aml_int(0x60), 0x04));
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    /* Fields declarion has to happen *after* operation region */
390
    field = aml_field("PCI0.S08.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
391
    aml_append(field, aml_named_field("PRQ0", 8));
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    aml_append(field, aml_named_field("PRQ1", 8));
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    aml_append(field, aml_named_field("PRQ2", 8));
394
    aml_append(field, aml_named_field("PRQ3", 8));
395
    aml_append(sb_scope, field);
396
    aml_append(scope, sb_scope);
397

398
    qbus_build_aml(bus, scope);
399
}
400

401
static void pci_piix_init(Object *obj)
402
{
403
    PIIXState *d = PIIX_PCI_DEVICE(obj);
404

405
    qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs",
406
                             ISA_NUM_IRQS);
407

408
    object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
409
}
410

411
static Property pci_piix_props[] = {
412
    DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
413
    DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
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    DEFINE_PROP_BOOL("has-pic", PIIXState, has_pic, true),
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    DEFINE_PROP_BOOL("has-pit", PIIXState, has_pit, true),
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    DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
417
    DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
418
    DEFINE_PROP_END_OF_LIST(),
419
};
420

421
static void pci_piix_class_init(ObjectClass *klass, void *data)
422
{
423
    DeviceClass *dc = DEVICE_CLASS(klass);
424
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
425
    AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
426

427
    k->config_write = piix_write_config;
428
    dc->reset       = piix_reset;
429
    dc->desc        = "ISA bridge";
430
    dc->hotpluggable   = false;
431
    k->vendor_id    = PCI_VENDOR_ID_INTEL;
432
    k->class_id     = PCI_CLASS_BRIDGE_ISA;
433
    /*
434
     * Reason: part of PIIX southbridge, needs to be wired up by e.g.
435
     * pc_piix.c's pc_init1()
436
     */
437
    dc->user_creatable = false;
438
    device_class_set_props(dc, pci_piix_props);
439
    adevc->build_dev_aml = build_pci_isa_aml;
440
}
441

442
static const TypeInfo piix_pci_type_info = {
443
    .name = TYPE_PIIX_PCI_DEVICE,
444
    .parent = TYPE_PCI_DEVICE,
445
    .instance_size = sizeof(PIIXState),
446
    .instance_init = pci_piix_init,
447
    .abstract = true,
448
    .class_init = pci_piix_class_init,
449
    .interfaces = (InterfaceInfo[]) {
450
        { INTERFACE_CONVENTIONAL_PCI_DEVICE },
451
        { TYPE_ACPI_DEV_AML_IF },
452
        { },
453
    },
454
};
455

456
static void piix3_realize(PCIDevice *dev, Error **errp)
457
{
458
    pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp);
459
}
460

461
static void piix3_init(Object *obj)
462
{
463
    PIIXState *d = PIIX_PCI_DEVICE(obj);
464

465
    object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
466
}
467

468
static void piix3_class_init(ObjectClass *klass, void *data)
469
{
470
    DeviceClass *dc = DEVICE_CLASS(klass);
471
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
472

473
    k->realize = piix3_realize;
474
    /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
475
    k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
476
    dc->vmsd = &vmstate_piix3;
477
}
478

479
static const TypeInfo piix3_info = {
480
    .name          = TYPE_PIIX3_DEVICE,
481
    .parent        = TYPE_PIIX_PCI_DEVICE,
482
    .instance_init = piix3_init,
483
    .class_init    = piix3_class_init,
484
};
485

486
static void piix4_realize(PCIDevice *dev, Error **errp)
487
{
488
    pci_piix_realize(dev, TYPE_PIIX4_USB_UHCI, errp);
489
}
490

491
static void piix4_init(Object *obj)
492
{
493
    PIIXState *s = PIIX_PCI_DEVICE(obj);
494

495
    object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
496
}
497

498
static void piix4_class_init(ObjectClass *klass, void *data)
499
{
500
    DeviceClass *dc = DEVICE_CLASS(klass);
501
    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
502

503
    k->realize = piix4_realize;
504
    k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
505
    dc->vmsd = &vmstate_piix4;
506
}
507

508
static const TypeInfo piix4_info = {
509
    .name          = TYPE_PIIX4_PCI_DEVICE,
510
    .parent        = TYPE_PIIX_PCI_DEVICE,
511
    .instance_init = piix4_init,
512
    .class_init    = piix4_class_init,
513
};
514

515
static void piix3_register_types(void)
516
{
517
    type_register_static(&piix_pci_type_info);
518
    type_register_static(&piix3_info);
519
    type_register_static(&piix4_info);
520
}
521

522
type_init(piix3_register_types)
523