qemu

1
/*
2
 * QEMU IPMI BT emulation
3
 *
4
 * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
12
 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
15
 *
16
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
24
#include "qemu/osdep.h"
25
#include "migration/vmstate.h"
26
#include "qemu/log.h"
27
#include "qapi/error.h"
28
#include "hw/ipmi/ipmi_bt.h"
29

30
/* Control register */
31
#define IPMI_BT_CLR_WR_BIT         0
32
#define IPMI_BT_CLR_RD_BIT         1
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#define IPMI_BT_H2B_ATN_BIT        2
34
#define IPMI_BT_B2H_ATN_BIT        3
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#define IPMI_BT_SMS_ATN_BIT        4
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#define IPMI_BT_HBUSY_BIT          6
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#define IPMI_BT_BBUSY_BIT          7
38

39
#define IPMI_BT_GET_CLR_WR(d)      (((d) >> IPMI_BT_CLR_WR_BIT) & 0x1)
40

41
#define IPMI_BT_GET_CLR_RD(d)      (((d) >> IPMI_BT_CLR_RD_BIT) & 0x1)
42

43
#define IPMI_BT_GET_H2B_ATN(d)     (((d) >> IPMI_BT_H2B_ATN_BIT) & 0x1)
44

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#define IPMI_BT_B2H_ATN_MASK       (1 << IPMI_BT_B2H_ATN_BIT)
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#define IPMI_BT_GET_B2H_ATN(d)     (((d) >> IPMI_BT_B2H_ATN_BIT) & 0x1)
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#define IPMI_BT_SET_B2H_ATN(d, v)  ((d) = (((d) & ~IPMI_BT_B2H_ATN_MASK) | \
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                                        (!!(v) << IPMI_BT_B2H_ATN_BIT)))
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#define IPMI_BT_SMS_ATN_MASK       (1 << IPMI_BT_SMS_ATN_BIT)
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#define IPMI_BT_GET_SMS_ATN(d)     (((d) >> IPMI_BT_SMS_ATN_BIT) & 0x1)
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#define IPMI_BT_SET_SMS_ATN(d, v)  ((d) = (((d) & ~IPMI_BT_SMS_ATN_MASK) | \
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                                        (!!(v) << IPMI_BT_SMS_ATN_BIT)))
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#define IPMI_BT_HBUSY_MASK         (1 << IPMI_BT_HBUSY_BIT)
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#define IPMI_BT_GET_HBUSY(d)       (((d) >> IPMI_BT_HBUSY_BIT) & 0x1)
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#define IPMI_BT_SET_HBUSY(d, v)    ((d) = (((d) & ~IPMI_BT_HBUSY_MASK) | \
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                                       (!!(v) << IPMI_BT_HBUSY_BIT)))
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#define IPMI_BT_BBUSY_MASK         (1 << IPMI_BT_BBUSY_BIT)
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#define IPMI_BT_SET_BBUSY(d, v)    ((d) = (((d) & ~IPMI_BT_BBUSY_MASK) | \
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                                       (!!(v) << IPMI_BT_BBUSY_BIT)))
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64

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/* Mask register */
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#define IPMI_BT_B2H_IRQ_EN_BIT     0
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#define IPMI_BT_B2H_IRQ_BIT        1
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#define IPMI_BT_B2H_IRQ_EN_MASK      (1 << IPMI_BT_B2H_IRQ_EN_BIT)
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#define IPMI_BT_GET_B2H_IRQ_EN(d)    (((d) >> IPMI_BT_B2H_IRQ_EN_BIT) & 0x1)
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#define IPMI_BT_SET_B2H_IRQ_EN(d, v) ((d) = (((d) & ~IPMI_BT_B2H_IRQ_EN_MASK) |\
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                                        (!!(v) << IPMI_BT_B2H_IRQ_EN_BIT)))
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#define IPMI_BT_B2H_IRQ_MASK         (1 << IPMI_BT_B2H_IRQ_BIT)
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#define IPMI_BT_GET_B2H_IRQ(d)       (((d) >> IPMI_BT_B2H_IRQ_BIT) & 0x1)
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#define IPMI_BT_SET_B2H_IRQ(d, v)    ((d) = (((d) & ~IPMI_BT_B2H_IRQ_MASK) | \
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                                        (!!(v) << IPMI_BT_B2H_IRQ_BIT)))
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#define IPMI_CMD_GET_BT_INTF_CAP        0x36
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static void ipmi_bt_raise_irq(IPMIBT *ib)
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{
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    if (ib->use_irq && ib->irqs_enabled && ib->raise_irq) {
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        ib->raise_irq(ib);
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    }
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}
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static void ipmi_bt_lower_irq(IPMIBT *ib)
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{
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    if (ib->lower_irq) {
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        ib->lower_irq(ib);
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    }
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}
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static void ipmi_bt_handle_event(IPMIInterface *ii)
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{
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    IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
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    IPMIBT *ib = iic->get_backend_data(ii);
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    if (ib->inlen < 4) {
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        goto out;
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    }
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    /* Note that overruns are handled by handle_command */
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    if (ib->inmsg[0] != (ib->inlen - 1)) {
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        /* Length mismatch, just ignore. */
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        IPMI_BT_SET_BBUSY(ib->control_reg, 1);
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        ib->inlen = 0;
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        goto out;
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    }
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    if ((ib->inmsg[1] == (IPMI_NETFN_APP << 2)) &&
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                        (ib->inmsg[3] == IPMI_CMD_GET_BT_INTF_CAP)) {
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        /* We handle this one ourselves. */
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        ib->outmsg[0] = 9;
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        ib->outmsg[1] = ib->inmsg[1] | 0x04;
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        ib->outmsg[2] = ib->inmsg[2];
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        ib->outmsg[3] = ib->inmsg[3];
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        ib->outmsg[4] = 0;
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        ib->outmsg[5] = 1; /* Only support 1 outstanding request. */
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        if (sizeof(ib->inmsg) > 0xff) { /* Input buffer size */
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            ib->outmsg[6] = 0xff;
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        } else {
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            ib->outmsg[6] = (unsigned char) sizeof(ib->inmsg);
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        }
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        if (sizeof(ib->outmsg) > 0xff) { /* Output buffer size */
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            ib->outmsg[7] = 0xff;
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        } else {
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            ib->outmsg[7] = (unsigned char) sizeof(ib->outmsg);
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        }
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        ib->outmsg[8] = 10; /* Max request to response time */
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        ib->outmsg[9] = 0; /* Don't recommend retries */
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        ib->outlen = 10;
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        IPMI_BT_SET_BBUSY(ib->control_reg, 0);
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        IPMI_BT_SET_B2H_ATN(ib->control_reg, 1);
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        if (!IPMI_BT_GET_B2H_IRQ(ib->mask_reg) &&
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                IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) {
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            IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1);
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            ipmi_bt_raise_irq(ib);
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        }
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        goto out;
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    }
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    ib->waiting_seq = ib->inmsg[2];
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    ib->inmsg[2] = ib->inmsg[1];
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    {
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        IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(ib->bmc);
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        bk->handle_command(ib->bmc, ib->inmsg + 2, ib->inlen - 2,
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                           sizeof(ib->inmsg), ib->waiting_rsp);
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    }
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 out:
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    return;
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}
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static void ipmi_bt_handle_rsp(IPMIInterface *ii, uint8_t msg_id,
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                                unsigned char *rsp, unsigned int rsp_len)
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{
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    IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
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    IPMIBT *ib = iic->get_backend_data(ii);
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    if (ib->waiting_rsp == msg_id) {
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        ib->waiting_rsp++;
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        if (rsp_len > (sizeof(ib->outmsg) - 2)) {
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            ib->outmsg[0] = 4;
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            ib->outmsg[1] = rsp[0];
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            ib->outmsg[2] = ib->waiting_seq;
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            ib->outmsg[3] = rsp[1];
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            ib->outmsg[4] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES;
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            ib->outlen = 5;
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        } else {
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            ib->outmsg[0] = rsp_len + 1;
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            ib->outmsg[1] = rsp[0];
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            ib->outmsg[2] = ib->waiting_seq;
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            memcpy(ib->outmsg + 3, rsp + 1, rsp_len - 1);
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            ib->outlen = rsp_len + 2;
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        }
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        IPMI_BT_SET_BBUSY(ib->control_reg, 0);
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        IPMI_BT_SET_B2H_ATN(ib->control_reg, 1);
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        if (!IPMI_BT_GET_B2H_IRQ(ib->mask_reg) &&
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                IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) {
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            IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1);
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            ipmi_bt_raise_irq(ib);
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        }
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    }
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}
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static uint64_t ipmi_bt_ioport_read(void *opaque, hwaddr addr, unsigned size)
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{
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    IPMIInterface *ii = opaque;
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    IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
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    IPMIBT *ib = iic->get_backend_data(ii);
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    uint32_t ret = 0xff;
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    switch (addr & ib->size_mask) {
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    case 0:
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        ret = ib->control_reg;
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        break;
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    case 1:
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        if (ib->outpos < ib->outlen) {
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            ret = ib->outmsg[ib->outpos];
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            ib->outpos++;
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            if (ib->outpos == ib->outlen) {
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                ib->outpos = 0;
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                ib->outlen = 0;
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            }
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        } else {
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            ret = 0xff;
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        }
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        break;
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    case 2:
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        ret = ib->mask_reg;
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        break;
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    default:
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        ret = 0xff;
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        break;
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    }
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    return ret;
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}
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static void ipmi_bt_signal(IPMIBT *ib, IPMIInterface *ii)
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{
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    IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
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    ib->do_wake = 1;
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    while (ib->do_wake) {
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        ib->do_wake = 0;
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        iic->handle_if_event(ii);
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    }
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}
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static void ipmi_bt_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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                                 unsigned size)
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{
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    IPMIInterface *ii = opaque;
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    IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
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    IPMIBT *ib = iic->get_backend_data(ii);
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    switch (addr & ib->size_mask) {
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    case 0:
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        if (IPMI_BT_GET_CLR_WR(val)) {
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            ib->inlen = 0;
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        }
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        if (IPMI_BT_GET_CLR_RD(val)) {
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            ib->outpos = 0;
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        }
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        if (IPMI_BT_GET_B2H_ATN(val)) {
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            IPMI_BT_SET_B2H_ATN(ib->control_reg, 0);
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        }
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        if (IPMI_BT_GET_SMS_ATN(val)) {
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            IPMI_BT_SET_SMS_ATN(ib->control_reg, 0);
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        }
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        if (IPMI_BT_GET_HBUSY(val)) {
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            /* Toggle */
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            IPMI_BT_SET_HBUSY(ib->control_reg,
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                              !IPMI_BT_GET_HBUSY(ib->control_reg));
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        }
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        if (IPMI_BT_GET_H2B_ATN(val)) {
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            IPMI_BT_SET_BBUSY(ib->control_reg, 1);
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            ipmi_bt_signal(ib, ii);
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        }
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        break;
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    case 1:
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        if (ib->inlen < sizeof(ib->inmsg)) {
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            ib->inmsg[ib->inlen] = val;
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        }
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        ib->inlen++;
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        break;
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    case 2:
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        if (IPMI_BT_GET_B2H_IRQ_EN(val) !=
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                        IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) {
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            if (IPMI_BT_GET_B2H_IRQ_EN(val)) {
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                if (IPMI_BT_GET_B2H_ATN(ib->control_reg) ||
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                        IPMI_BT_GET_SMS_ATN(ib->control_reg)) {
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                    IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1);
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                    ipmi_bt_raise_irq(ib);
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                }
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                IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 1);
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            } else {
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                if (IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) {
280
                    IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0);
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                    ipmi_bt_lower_irq(ib);
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                }
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                IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 0);
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            }
285
        }
286
        if (IPMI_BT_GET_B2H_IRQ(val) && IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) {
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            IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0);
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            ipmi_bt_lower_irq(ib);
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        }
290
        break;
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    default:
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        /* Ignore. */
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        break;
294
    }
295
}
296

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static const MemoryRegionOps ipmi_bt_io_ops = {
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    .read = ipmi_bt_ioport_read,
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    .write = ipmi_bt_ioport_write,
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    .impl = {
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        .min_access_size = 1,
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        .max_access_size = 1,
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    },
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    .endianness = DEVICE_LITTLE_ENDIAN,
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};
306

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static void ipmi_bt_set_atn(IPMIInterface *ii, int val, int irq)
308
{
309
    IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
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    IPMIBT *ib = iic->get_backend_data(ii);
311

312
    if (!!val == IPMI_BT_GET_SMS_ATN(ib->control_reg)) {
313
        return;
314
    }
315

316
    IPMI_BT_SET_SMS_ATN(ib->control_reg, val);
317
    if (val) {
318
        if (irq && !IPMI_BT_GET_B2H_ATN(ib->control_reg) &&
319
                IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) {
320
            IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1);
321
            ipmi_bt_raise_irq(ib);
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        }
323
    } else {
324
        if (!IPMI_BT_GET_B2H_ATN(ib->control_reg) &&
325
                IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) {
326
            IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0);
327
            ipmi_bt_lower_irq(ib);
328
        }
329
    }
330
}
331

332
static void ipmi_bt_handle_reset(IPMIInterface *ii, bool is_cold)
333
{
334
    IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
335
    IPMIBT *ib = iic->get_backend_data(ii);
336

337
    if (is_cold) {
338
        /* Disable the BT interrupt on reset */
339
        if (IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) {
340
            IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0);
341
            ipmi_bt_lower_irq(ib);
342
        }
343
        IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 0);
344
    }
345
}
346

347
static void ipmi_bt_set_irq_enable(IPMIInterface *ii, int val)
348
{
349
    IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
350
    IPMIBT *ib = iic->get_backend_data(ii);
351

352
    ib->irqs_enabled = val;
353
}
354

355
static void ipmi_bt_init(IPMIInterface *ii, unsigned int min_size, Error **errp)
356
{
357
    IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
358
    IPMIBT *ib = iic->get_backend_data(ii);
359

360
    if (min_size == 0) {
361
        min_size = 4;
362
    }
363
    ib->size_mask = min_size - 1;
364
    ib->io_length = 3;
365

366
    memory_region_init_io(&ib->io, NULL, &ipmi_bt_io_ops, ii, "ipmi-bt",
367
                          min_size);
368
}
369

370
int ipmi_bt_vmstate_post_load(void *opaque, int version)
371
{
372
    IPMIBT *ib = opaque;
373

374
    /* Make sure all the values are sane. */
375
    if (ib->outpos >= MAX_IPMI_MSG_SIZE || ib->outlen >= MAX_IPMI_MSG_SIZE ||
376
        ib->outpos >= ib->outlen) {
377
        qemu_log_mask(LOG_GUEST_ERROR,
378
                      "ipmi:bt: vmstate transfer received bad out values: %d %d\n",
379
                      ib->outpos, ib->outlen);
380
        ib->outpos = 0;
381
        ib->outlen = 0;
382
    }
383

384
    if (ib->inlen >= MAX_IPMI_MSG_SIZE) {
385
        qemu_log_mask(LOG_GUEST_ERROR,
386
                      "ipmi:bt: vmstate transfer received bad in value: %d\n",
387
                      ib->inlen);
388
        ib->inlen = 0;
389
    }
390

391
    return 0;
392
}
393

394
const VMStateDescription vmstate_IPMIBT = {
395
    .name = TYPE_IPMI_INTERFACE_PREFIX "bt",
396
    .version_id = 1,
397
    .minimum_version_id = 1,
398
    .post_load = ipmi_bt_vmstate_post_load,
399
    .fields = (const VMStateField[]) {
400
        VMSTATE_BOOL(obf_irq_set, IPMIBT),
401
        VMSTATE_BOOL(atn_irq_set, IPMIBT),
402
        VMSTATE_BOOL(irqs_enabled, IPMIBT),
403
        VMSTATE_UINT32(outpos, IPMIBT),
404
        VMSTATE_UINT32(outlen, IPMIBT),
405
        VMSTATE_UINT8_ARRAY(outmsg, IPMIBT, MAX_IPMI_MSG_SIZE),
406
        VMSTATE_UINT32(inlen, IPMIBT),
407
        VMSTATE_UINT8_ARRAY(inmsg, IPMIBT, MAX_IPMI_MSG_SIZE),
408
        VMSTATE_UINT8(control_reg, IPMIBT),
409
        VMSTATE_UINT8(mask_reg, IPMIBT),
410
        VMSTATE_UINT8(waiting_rsp, IPMIBT),
411
        VMSTATE_UINT8(waiting_seq, IPMIBT),
412
        VMSTATE_END_OF_LIST()
413
    }
414
};
415

416
void ipmi_bt_get_fwinfo(struct IPMIBT *ib, IPMIFwInfo *info)
417
{
418
    info->interface_name = "bt";
419
    info->interface_type = IPMI_SMBIOS_BT;
420
    info->ipmi_spec_major_revision = 2;
421
    info->ipmi_spec_minor_revision = 0;
422
    info->base_address = ib->io_base;
423
    info->register_length = ib->io_length;
424
    info->register_spacing = 1;
425
    info->memspace = IPMI_MEMSPACE_IO;
426
    info->irq_type = IPMI_LEVEL_IRQ;
427
}
428

429
void ipmi_bt_class_init(IPMIInterfaceClass *iic)
430
{
431
    iic->init = ipmi_bt_init;
432
    iic->set_atn = ipmi_bt_set_atn;
433
    iic->handle_rsp = ipmi_bt_handle_rsp;
434
    iic->handle_if_event = ipmi_bt_handle_event;
435
    iic->set_irq_enable = ipmi_bt_set_irq_enable;
436
    iic->reset = ipmi_bt_handle_reset;
437
}
438