qemu

1
/*
2
 * PC SMBus implementation
3
 * split from acpi.c
4
 *
5
 * Copyright (c) 2006 Fabrice Bellard
6
 *
7
 * This library is free software; you can redistribute it and/or
8
 * modify it under the terms of the GNU Lesser General Public
9
 * License version 2.1 as published by the Free Software Foundation.
10
 *
11
 * This library is distributed in the hope that it will be useful,
12
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
15
 *
16
 * You should have received a copy of the GNU Lesser General Public
17
 * License along with this library; if not, see
18
 * <http://www.gnu.org/licenses/>.
19
 */
20

21
#include "qemu/osdep.h"
22
#include "hw/boards.h"
23
#include "hw/i2c/pm_smbus.h"
24
#include "hw/i2c/smbus_master.h"
25
#include "migration/vmstate.h"
26
#include "trace.h"
27

28
#define SMBHSTSTS       0x00
29
#define SMBHSTCNT       0x02
30
#define SMBHSTCMD       0x03
31
#define SMBHSTADD       0x04
32
#define SMBHSTDAT0      0x05
33
#define SMBHSTDAT1      0x06
34
#define SMBBLKDAT       0x07
35
#define SMBAUXCTL       0x0d
36

37
#define STS_HOST_BUSY   (1 << 0)
38
#define STS_INTR        (1 << 1)
39
#define STS_DEV_ERR     (1 << 2)
40
#define STS_BUS_ERR     (1 << 3)
41
#define STS_FAILED      (1 << 4)
42
#define STS_SMBALERT    (1 << 5)
43
#define STS_INUSE_STS   (1 << 6)
44
#define STS_BYTE_DONE   (1 << 7)
45
/* Signs of successfully transaction end :
46
*  ByteDoneStatus = 1 (STS_BYTE_DONE) and INTR = 1 (STS_INTR )
47
*/
48

49
#define CTL_INTREN      (1 << 0)
50
#define CTL_KILL        (1 << 1)
51
#define CTL_LAST_BYTE   (1 << 5)
52
#define CTL_START       (1 << 6)
53
#define CTL_PEC_EN      (1 << 7)
54
#define CTL_RETURN_MASK 0x1f
55

56
#define PROT_QUICK          0
57
#define PROT_BYTE           1
58
#define PROT_BYTE_DATA      2
59
#define PROT_WORD_DATA      3
60
#define PROT_PROC_CALL      4
61
#define PROT_BLOCK_DATA     5
62
#define PROT_I2C_BLOCK_READ 6
63

64
#define AUX_PEC       (1 << 0)
65
#define AUX_BLK       (1 << 1)
66
#define AUX_MASK      0x3
67

68
static void smb_transaction(PMSMBus *s)
69
{
70
    uint8_t prot = (s->smb_ctl >> 2) & 0x07;
71
    uint8_t read = s->smb_addr & 0x01;
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    uint8_t cmd = s->smb_cmd;
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    uint8_t addr = s->smb_addr >> 1;
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    I2CBus *bus = s->smbus;
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    int ret;
76

77
    trace_smbus_transaction(addr, prot);
78
    /* Transaction isn't exec if STS_DEV_ERR bit set */
79
    if ((s->smb_stat & STS_DEV_ERR) != 0)  {
80
        goto error;
81
    }
82

83
    switch(prot) {
84
    case PROT_QUICK:
85
        ret = smbus_quick_command(bus, addr, read);
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        goto done;
87
    case PROT_BYTE:
88
        if (read) {
89
            ret = smbus_receive_byte(bus, addr);
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            goto data8;
91
        } else {
92
            ret = smbus_send_byte(bus, addr, cmd);
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            goto done;
94
        }
95
    case PROT_BYTE_DATA:
96
        if (read) {
97
            ret = smbus_read_byte(bus, addr, cmd);
98
            goto data8;
99
        } else {
100
            ret = smbus_write_byte(bus, addr, cmd, s->smb_data0);
101
            goto done;
102
        }
103
        break;
104
    case PROT_WORD_DATA:
105
        if (read) {
106
            ret = smbus_read_word(bus, addr, cmd);
107
            goto data16;
108
        } else {
109
            ret = smbus_write_word(bus, addr, cmd,
110
                                   (s->smb_data1 << 8) | s->smb_data0);
111
            goto done;
112
        }
113
        break;
114
    case PROT_I2C_BLOCK_READ:
115
        /* According to the Linux i2c-i801 driver:
116
         *   NB: page 240 of ICH5 datasheet shows that the R/#W
117
         *   bit should be cleared here, even when reading.
118
         *   However if SPD Write Disable is set (Lynx Point and later),
119
         *   the read will fail if we don't set the R/#W bit.
120
         * So at least Linux may or may not set the read bit here.
121
         * So just ignore the read bit for this command.
122
         */
123
        if (i2c_start_send(bus, addr)) {
124
            goto error;
125
        }
126
        ret = i2c_send(bus, s->smb_data1);
127
        if (ret) {
128
            goto error;
129
        }
130
        if (i2c_start_recv(bus, addr)) {
131
            goto error;
132
        }
133
        s->in_i2c_block_read = true;
134
        s->smb_blkdata = i2c_recv(s->smbus);
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        s->op_done = false;
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        s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
137
        goto out;
138

139
    case PROT_BLOCK_DATA:
140
        if (read) {
141
            ret = smbus_read_block(bus, addr, cmd, s->smb_data,
142
                                   sizeof(s->smb_data), !s->i2c_enable,
143
                                   !s->i2c_enable);
144
            if (ret < 0) {
145
                goto error;
146
            }
147
            s->smb_index = 0;
148
            s->op_done = false;
149
            if (s->smb_auxctl & AUX_BLK) {
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                s->smb_stat |= STS_INTR;
151
            } else {
152
                s->smb_blkdata = s->smb_data[0];
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                s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
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            }
155
            s->smb_data0 = ret;
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            goto out;
157
        } else {
158
            if (s->smb_auxctl & AUX_BLK) {
159
                if (s->smb_index != s->smb_data0) {
160
                    s->smb_index = 0;
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                    goto error;
162
                }
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                /* Data is already all written to the queue, just do
164
                   the operation. */
165
                s->smb_index = 0;
166
                ret = smbus_write_block(bus, addr, cmd, s->smb_data,
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                                        s->smb_data0, !s->i2c_enable);
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                if (ret < 0) {
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                    goto error;
170
                }
171
                s->op_done = true;
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                s->smb_stat |= STS_INTR;
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                s->smb_stat &= ~STS_HOST_BUSY;
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            } else {
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                s->op_done = false;
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                s->smb_stat |= STS_HOST_BUSY | STS_BYTE_DONE;
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                s->smb_data[0] = s->smb_blkdata;
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                s->smb_index = 0;
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            }
180
            goto out;
181
        }
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        break;
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    default:
184
        goto error;
185
    }
186
    abort();
187

188
data16:
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    if (ret < 0) {
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        goto error;
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    }
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    s->smb_data1 = ret >> 8;
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data8:
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    if (ret < 0) {
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        goto error;
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    }
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    s->smb_data0 = ret;
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done:
199
    if (ret < 0) {
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        goto error;
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    }
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    s->smb_stat |= STS_INTR;
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out:
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    return;
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206
error:
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    s->smb_stat |= STS_DEV_ERR;
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    return;
209
}
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static void smb_transaction_start(PMSMBus *s)
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{
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    if (s->smb_ctl & CTL_INTREN) {
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        smb_transaction(s);
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        s->start_transaction_on_status_read = false;
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    } else {
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        /* Do not execute immediately the command; it will be
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         * executed when guest will read SMB_STAT register.  This
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         * is to work around a bug in AMIBIOS (that is working
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         * around another bug in some specific hardware) where
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         * it waits for STS_HOST_BUSY to be set before waiting
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         * checking for status.  If STS_HOST_BUSY doesn't get
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         * set, it gets stuck. */
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        s->smb_stat |= STS_HOST_BUSY;
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        s->start_transaction_on_status_read = true;
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    }
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}
228

229
static bool
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smb_irq_value(PMSMBus *s)
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{
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    return ((s->smb_stat & ~STS_HOST_BUSY) != 0) && (s->smb_ctl & CTL_INTREN);
233
}
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235
static bool
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smb_byte_by_byte(PMSMBus *s)
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{
238
    if (s->op_done) {
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        return false;
240
    }
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    if (s->in_i2c_block_read) {
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        return true;
243
    }
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    return !(s->smb_auxctl & AUX_BLK);
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}
246

247
static void smb_ioport_writeb(void *opaque, hwaddr addr, uint64_t val,
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                              unsigned width)
249
{
250
    PMSMBus *s = opaque;
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    uint8_t clear_byte_done;
252

253
    trace_smbus_ioport_writeb(addr, val);
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    switch(addr) {
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    case SMBHSTSTS:
256
        clear_byte_done = s->smb_stat & val & STS_BYTE_DONE;
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        s->smb_stat &= ~(val & ~STS_HOST_BUSY);
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        if (clear_byte_done && smb_byte_by_byte(s)) {
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            uint8_t read = s->smb_addr & 0x01;
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261
            if (s->in_i2c_block_read) {
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                /* See comment below PROT_I2C_BLOCK_READ above. */
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                read = 1;
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            }
265

266
            s->smb_index++;
267
            if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
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                s->smb_index = 0;
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            }
270
            if (!read && s->smb_index == s->smb_data0) {
271
                uint8_t prot = (s->smb_ctl >> 2) & 0x07;
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                uint8_t cmd = s->smb_cmd;
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                uint8_t smb_addr = s->smb_addr >> 1;
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                int ret;
275

276
                if (prot == PROT_I2C_BLOCK_READ) {
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                    s->smb_stat |= STS_DEV_ERR;
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                    goto out;
279
                }
280

281
                ret = smbus_write_block(s->smbus, smb_addr, cmd, s->smb_data,
282
                                        s->smb_data0, !s->i2c_enable);
283
                if (ret < 0) {
284
                    s->smb_stat |= STS_DEV_ERR;
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                    goto out;
286
                }
287
                s->op_done = true;
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                s->smb_stat |= STS_INTR;
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                s->smb_stat &= ~STS_HOST_BUSY;
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            } else if (!read) {
291
                s->smb_data[s->smb_index] = s->smb_blkdata;
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                s->smb_stat |= STS_BYTE_DONE;
293
            } else if (s->smb_ctl & CTL_LAST_BYTE) {
294
                s->op_done = true;
295
                if (s->in_i2c_block_read) {
296
                    s->in_i2c_block_read = false;
297
                    s->smb_blkdata = i2c_recv(s->smbus);
298
                    i2c_nack(s->smbus);
299
                    i2c_end_transfer(s->smbus);
300
                } else {
301
                    s->smb_blkdata = s->smb_data[s->smb_index];
302
                }
303
                s->smb_index = 0;
304
                s->smb_stat |= STS_INTR;
305
                s->smb_stat &= ~STS_HOST_BUSY;
306
            } else {
307
                if (s->in_i2c_block_read) {
308
                    s->smb_blkdata = i2c_recv(s->smbus);
309
                } else {
310
                    s->smb_blkdata = s->smb_data[s->smb_index];
311
                }
312
                s->smb_stat |= STS_BYTE_DONE;
313
            }
314
        }
315
        break;
316
    case SMBHSTCNT:
317
        s->smb_ctl = val & ~CTL_START; /* CTL_START always reads 0 */
318
        if (val & CTL_START) {
319
            if (!s->op_done) {
320
                s->smb_index = 0;
321
                s->op_done = true;
322
                if (s->in_i2c_block_read) {
323
                    s->in_i2c_block_read = false;
324
                    i2c_end_transfer(s->smbus);
325
                }
326
            }
327
            smb_transaction_start(s);
328
        }
329
        if (s->smb_ctl & CTL_KILL) {
330
            s->op_done = true;
331
            s->smb_index = 0;
332
            s->smb_stat |= STS_FAILED;
333
            s->smb_stat &= ~STS_HOST_BUSY;
334
        }
335
        break;
336
    case SMBHSTCMD:
337
        s->smb_cmd = val;
338
        break;
339
    case SMBHSTADD:
340
        s->smb_addr = val;
341
        break;
342
    case SMBHSTDAT0:
343
        s->smb_data0 = val;
344
        break;
345
    case SMBHSTDAT1:
346
        s->smb_data1 = val;
347
        break;
348
    case SMBBLKDAT:
349
        if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
350
            s->smb_index = 0;
351
        }
352
        if (s->smb_auxctl & AUX_BLK) {
353
            s->smb_data[s->smb_index++] = val;
354
        } else {
355
            s->smb_blkdata = val;
356
        }
357
        break;
358
    case SMBAUXCTL:
359
        s->smb_auxctl = val & AUX_MASK;
360
        break;
361
    default:
362
        break;
363
    }
364

365
 out:
366
    if (s->set_irq) {
367
        s->set_irq(s, smb_irq_value(s));
368
    }
369
}
370

371
static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width)
372
{
373
    PMSMBus *s = opaque;
374
    uint32_t val;
375

376
    switch(addr) {
377
    case SMBHSTSTS:
378
        val = s->smb_stat;
379
        if (s->start_transaction_on_status_read) {
380
            /* execute command now */
381
            s->start_transaction_on_status_read = false;
382
            s->smb_stat &= ~STS_HOST_BUSY;
383
            smb_transaction(s);
384
        }
385
        break;
386
    case SMBHSTCNT:
387
        val = s->smb_ctl & CTL_RETURN_MASK;
388
        break;
389
    case SMBHSTCMD:
390
        val = s->smb_cmd;
391
        break;
392
    case SMBHSTADD:
393
        val = s->smb_addr;
394
        break;
395
    case SMBHSTDAT0:
396
        val = s->smb_data0;
397
        break;
398
    case SMBHSTDAT1:
399
        val = s->smb_data1;
400
        break;
401
    case SMBBLKDAT:
402
        if (s->smb_auxctl & AUX_BLK && !s->in_i2c_block_read) {
403
            if (s->smb_index >= PM_SMBUS_MAX_MSG_SIZE) {
404
                s->smb_index = 0;
405
            }
406
            val = s->smb_data[s->smb_index++];
407
            if (!s->op_done && s->smb_index == s->smb_data0) {
408
                s->op_done = true;
409
                s->smb_index = 0;
410
                s->smb_stat &= ~STS_HOST_BUSY;
411
            }
412
        } else {
413
            val = s->smb_blkdata;
414
        }
415
        break;
416
    case SMBAUXCTL:
417
        val = s->smb_auxctl;
418
        break;
419
    default:
420
        val = 0;
421
        break;
422
    }
423
    trace_smbus_ioport_readb(addr, val);
424

425
    if (s->set_irq) {
426
        s->set_irq(s, smb_irq_value(s));
427
    }
428

429
    return val;
430
}
431

432
static void pm_smbus_reset(PMSMBus *s)
433
{
434
    s->op_done = true;
435
    s->smb_index = 0;
436
    s->smb_stat = 0;
437
}
438

439
static const MemoryRegionOps pm_smbus_ops = {
440
    .read = smb_ioport_readb,
441
    .write = smb_ioport_writeb,
442
    .valid.min_access_size = 1,
443
    .valid.max_access_size = 1,
444
    .endianness = DEVICE_LITTLE_ENDIAN,
445
};
446

447
bool pm_smbus_vmstate_needed(void)
448
{
449
    MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
450

451
    return !mc->smbus_no_migration_support;
452
}
453

454
const VMStateDescription pmsmb_vmstate = {
455
    .name = "pmsmb",
456
    .version_id = 1,
457
    .minimum_version_id = 1,
458
    .fields = (const VMStateField[]) {
459
        VMSTATE_UINT8(smb_stat, PMSMBus),
460
        VMSTATE_UINT8(smb_ctl, PMSMBus),
461
        VMSTATE_UINT8(smb_cmd, PMSMBus),
462
        VMSTATE_UINT8(smb_addr, PMSMBus),
463
        VMSTATE_UINT8(smb_data0, PMSMBus),
464
        VMSTATE_UINT8(smb_data1, PMSMBus),
465
        VMSTATE_UINT32(smb_index, PMSMBus),
466
        VMSTATE_UINT8_ARRAY(smb_data, PMSMBus, PM_SMBUS_MAX_MSG_SIZE),
467
        VMSTATE_UINT8(smb_auxctl, PMSMBus),
468
        VMSTATE_UINT8(smb_blkdata, PMSMBus),
469
        VMSTATE_BOOL(i2c_enable, PMSMBus),
470
        VMSTATE_BOOL(op_done, PMSMBus),
471
        VMSTATE_BOOL(in_i2c_block_read, PMSMBus),
472
        VMSTATE_BOOL(start_transaction_on_status_read, PMSMBus),
473
        VMSTATE_END_OF_LIST()
474
    }
475
};
476

477
void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk)
478
{
479
    smb->op_done = true;
480
    smb->reset = pm_smbus_reset;
481
    smb->smbus = i2c_init_bus(parent, "i2c");
482
    if (force_aux_blk) {
483
        smb->smb_auxctl |= AUX_BLK;
484
    }
485
    memory_region_init_io(&smb->io, OBJECT(parent), &pm_smbus_ops, smb,
486
                          "pm-smbus", 64);
487
}
488