qemu

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/*
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 *  Exynos4210 I2C Bus Serial Interface Emulation
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 *
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 *  Copyright (C) 2012 Samsung Electronics Co Ltd.
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 *    Maksim Kozlov, <m.kozlov@samsung.com>
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 *    Igor Mitsyanko, <i.mitsyanko@samsung.com>
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 *
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 *  This program is free software; you can redistribute it and/or modify it
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 *  under the terms of the GNU General Public License as published by the
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 *  Free Software Foundation; either version 2 of the License, or
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 *  (at your option) any later version.
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 *
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 *  This program is distributed in the hope that it will be useful, but WITHOUT
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 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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 *  for more details.
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 *
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 *  You should have received a copy of the GNU General Public License along
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 *  with this program; if not, see <http://www.gnu.org/licenses/>.
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 *
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 */
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#include "qemu/osdep.h"
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#include "qemu/module.h"
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#include "qemu/timer.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/i2c/i2c.h"
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#include "hw/irq.h"
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#include "qom/object.h"
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#ifndef EXYNOS4_I2C_DEBUG
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#define EXYNOS4_I2C_DEBUG                 0
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#endif
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#define TYPE_EXYNOS4_I2C                  "exynos4210.i2c"
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OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210I2CState, EXYNOS4_I2C)
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/* Exynos4210 I2C memory map */
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#define EXYNOS4_I2C_MEM_SIZE              0x14
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#define I2CCON_ADDR                       0x00  /* control register */
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#define I2CSTAT_ADDR                      0x04  /* control/status register */
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#define I2CADD_ADDR                       0x08  /* address register */
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#define I2CDS_ADDR                        0x0c  /* data shift register */
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#define I2CLC_ADDR                        0x10  /* line control register */
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#define I2CCON_ACK_GEN                    (1 << 7)
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#define I2CCON_INTRS_EN                   (1 << 5)
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#define I2CCON_INT_PEND                   (1 << 4)
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#define EXYNOS4_I2C_MODE(reg)             (((reg) >> 6) & 3)
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#define I2C_IN_MASTER_MODE(reg)           (((reg) >> 6) & 2)
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#define I2CMODE_MASTER_Rx                 0x2
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#define I2CMODE_MASTER_Tx                 0x3
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#define I2CSTAT_LAST_BIT                  (1 << 0)
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#define I2CSTAT_OUTPUT_EN                 (1 << 4)
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#define I2CSTAT_START_BUSY                (1 << 5)
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#if EXYNOS4_I2C_DEBUG
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#define DPRINT(fmt, args...)              \
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    do { fprintf(stderr, "QEMU I2C: "fmt, ## args); } while (0)
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static const char *exynos4_i2c_get_regname(unsigned offset)
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{
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    switch (offset) {
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    case I2CCON_ADDR:
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        return "I2CCON";
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    case I2CSTAT_ADDR:
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        return "I2CSTAT";
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    case I2CADD_ADDR:
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        return "I2CADD";
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    case I2CDS_ADDR:
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        return "I2CDS";
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    case I2CLC_ADDR:
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        return "I2CLC";
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    default:
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        return "[?]";
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    }
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}
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#else
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#define DPRINT(fmt, args...)              do { } while (0)
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#endif
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struct Exynos4210I2CState {
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    SysBusDevice parent_obj;
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    MemoryRegion iomem;
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    I2CBus *bus;
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    qemu_irq irq;
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    uint8_t i2ccon;
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    uint8_t i2cstat;
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    uint8_t i2cadd;
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    uint8_t i2cds;
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    uint8_t i2clc;
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    bool scl_free;
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};
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static inline void exynos4210_i2c_raise_interrupt(Exynos4210I2CState *s)
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{
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    if (s->i2ccon & I2CCON_INTRS_EN) {
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        s->i2ccon |= I2CCON_INT_PEND;
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        qemu_irq_raise(s->irq);
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    }
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}
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static void exynos4210_i2c_data_receive(void *opaque)
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{
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    Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
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    s->i2cstat &= ~I2CSTAT_LAST_BIT;
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    s->scl_free = false;
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    s->i2cds = i2c_recv(s->bus);
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    exynos4210_i2c_raise_interrupt(s);
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}
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static void exynos4210_i2c_data_send(void *opaque)
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{
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    Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
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    s->i2cstat &= ~I2CSTAT_LAST_BIT;
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    s->scl_free = false;
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    if (i2c_send(s->bus, s->i2cds) < 0 && (s->i2ccon & I2CCON_ACK_GEN)) {
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        s->i2cstat |= I2CSTAT_LAST_BIT;
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    }
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    exynos4210_i2c_raise_interrupt(s);
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}
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static uint64_t exynos4210_i2c_read(void *opaque, hwaddr offset,
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                                 unsigned size)
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{
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    Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
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    uint8_t value;
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    switch (offset) {
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    case I2CCON_ADDR:
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        value = s->i2ccon;
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        break;
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    case I2CSTAT_ADDR:
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        value = s->i2cstat;
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        break;
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    case I2CADD_ADDR:
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        value = s->i2cadd;
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        break;
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    case I2CDS_ADDR:
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        value = s->i2cds;
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        s->scl_free = true;
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        if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Rx &&
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               (s->i2cstat & I2CSTAT_START_BUSY) &&
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               !(s->i2ccon & I2CCON_INT_PEND)) {
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            exynos4210_i2c_data_receive(s);
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        }
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        break;
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    case I2CLC_ADDR:
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        value = s->i2clc;
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        break;
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    default:
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        value = 0;
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        DPRINT("ERROR: Bad read offset 0x%x\n", (unsigned int)offset);
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        break;
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    }
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    DPRINT("read %s [0x%02x] -> 0x%02x\n", exynos4_i2c_get_regname(offset),
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            (unsigned int)offset, value);
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    return value;
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}
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static void exynos4210_i2c_write(void *opaque, hwaddr offset,
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                              uint64_t value, unsigned size)
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{
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    Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
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    uint8_t v = value & 0xff;
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    DPRINT("write %s [0x%02x] <- 0x%02x\n", exynos4_i2c_get_regname(offset),
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            (unsigned int)offset, v);
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    switch (offset) {
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    case I2CCON_ADDR:
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        s->i2ccon = (v & ~I2CCON_INT_PEND) | (s->i2ccon & I2CCON_INT_PEND);
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        if ((s->i2ccon & I2CCON_INT_PEND) && !(v & I2CCON_INT_PEND)) {
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            s->i2ccon &= ~I2CCON_INT_PEND;
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            qemu_irq_lower(s->irq);
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            if (!(s->i2ccon & I2CCON_INTRS_EN)) {
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                s->i2cstat &= ~I2CSTAT_START_BUSY;
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            }
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            if (s->i2cstat & I2CSTAT_START_BUSY) {
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                if (s->scl_free) {
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                    if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Tx) {
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                        exynos4210_i2c_data_send(s);
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                    } else if (EXYNOS4_I2C_MODE(s->i2cstat) ==
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                            I2CMODE_MASTER_Rx) {
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                        exynos4210_i2c_data_receive(s);
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                    }
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                } else {
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                    s->i2ccon |= I2CCON_INT_PEND;
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                    qemu_irq_raise(s->irq);
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                }
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            }
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        }
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        break;
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    case I2CSTAT_ADDR:
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        s->i2cstat =
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                (s->i2cstat & I2CSTAT_START_BUSY) | (v & ~I2CSTAT_START_BUSY);
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        if (!(s->i2cstat & I2CSTAT_OUTPUT_EN)) {
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            s->i2cstat &= ~I2CSTAT_START_BUSY;
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            s->scl_free = true;
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            qemu_irq_lower(s->irq);
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            break;
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        }
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        /* Nothing to do if in i2c slave mode */
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        if (!I2C_IN_MASTER_MODE(s->i2cstat)) {
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            break;
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        }
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        if (v & I2CSTAT_START_BUSY) {
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            s->i2cstat &= ~I2CSTAT_LAST_BIT;
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            s->i2cstat |= I2CSTAT_START_BUSY;    /* Line is busy */
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            s->scl_free = false;
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            /* Generate start bit and send slave address */
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            if (i2c_start_transfer(s->bus, s->i2cds >> 1, s->i2cds & 0x1) &&
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                    (s->i2ccon & I2CCON_ACK_GEN)) {
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                s->i2cstat |= I2CSTAT_LAST_BIT;
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            } else if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Rx) {
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                exynos4210_i2c_data_receive(s);
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            }
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            exynos4210_i2c_raise_interrupt(s);
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        } else {
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            i2c_end_transfer(s->bus);
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            if (!(s->i2ccon & I2CCON_INT_PEND)) {
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                s->i2cstat &= ~I2CSTAT_START_BUSY;
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            }
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            s->scl_free = true;
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        }
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        break;
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    case I2CADD_ADDR:
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        if ((s->i2cstat & I2CSTAT_OUTPUT_EN) == 0) {
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            s->i2cadd = v;
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        }
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        break;
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    case I2CDS_ADDR:
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        if (s->i2cstat & I2CSTAT_OUTPUT_EN) {
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            s->i2cds = v;
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            s->scl_free = true;
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            if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Tx &&
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                    (s->i2cstat & I2CSTAT_START_BUSY) &&
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                    !(s->i2ccon & I2CCON_INT_PEND)) {
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                exynos4210_i2c_data_send(s);
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            }
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        }
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        break;
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    case I2CLC_ADDR:
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        s->i2clc = v;
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        break;
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    default:
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        DPRINT("ERROR: Bad write offset 0x%x\n", (unsigned int)offset);
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        break;
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    }
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}
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static const MemoryRegionOps exynos4210_i2c_ops = {
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    .read = exynos4210_i2c_read,
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    .write = exynos4210_i2c_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription exynos4210_i2c_vmstate = {
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    .name = "exynos4210.i2c",
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT8(i2ccon, Exynos4210I2CState),
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        VMSTATE_UINT8(i2cstat, Exynos4210I2CState),
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        VMSTATE_UINT8(i2cds, Exynos4210I2CState),
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        VMSTATE_UINT8(i2cadd, Exynos4210I2CState),
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        VMSTATE_UINT8(i2clc, Exynos4210I2CState),
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        VMSTATE_BOOL(scl_free, Exynos4210I2CState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static void exynos4210_i2c_reset(DeviceState *d)
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{
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    Exynos4210I2CState *s = EXYNOS4_I2C(d);
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    s->i2ccon  = 0x00;
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    s->i2cstat = 0x00;
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    s->i2cds   = 0xFF;
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    s->i2clc   = 0x00;
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    s->i2cadd  = 0xFF;
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    s->scl_free = true;
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}
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static void exynos4210_i2c_init(Object *obj)
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{
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    DeviceState *dev = DEVICE(obj);
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    Exynos4210I2CState *s = EXYNOS4_I2C(obj);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    memory_region_init_io(&s->iomem, obj, &exynos4210_i2c_ops, s,
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                          TYPE_EXYNOS4_I2C, EXYNOS4_I2C_MEM_SIZE);
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    sysbus_init_mmio(sbd, &s->iomem);
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    sysbus_init_irq(sbd, &s->irq);
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    s->bus = i2c_init_bus(dev, "i2c");
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}
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static void exynos4210_i2c_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->vmsd = &exynos4210_i2c_vmstate;
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    dc->reset = exynos4210_i2c_reset;
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}
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static const TypeInfo exynos4210_i2c_type_info = {
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    .name = TYPE_EXYNOS4_I2C,
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    .parent = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(Exynos4210I2CState),
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    .instance_init = exynos4210_i2c_init,
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    .class_init = exynos4210_i2c_class_init,
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};
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static void exynos4210_i2c_register_types(void)
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{
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    type_register_static(&exynos4210_i2c_type_info);
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}
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type_init(exynos4210_i2c_register_types)
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