qemu

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/*
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 * Copyright (c) 2006-2008 Openedhand Ltd.
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 * Written by Andrzej Zaborowski <balrog@zabor.org>
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 *
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 * This program is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU General Public License as
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 * published by the Free Software Foundation; either version 2 or
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 * (at your option) version 3 of the License.
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 *
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 * This program is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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 * GNU General Public License for more details.
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 *
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 * You should have received a copy of the GNU General Public License along
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 * with this program; if not, see <http://www.gnu.org/licenses/>.
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 */
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/arm/sharpsl.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#include "qom/object.h"
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/* SCOOP devices */
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#define TYPE_SCOOP "scoop"
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OBJECT_DECLARE_SIMPLE_TYPE(ScoopInfo, SCOOP)
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struct ScoopInfo {
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    SysBusDevice parent_obj;
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    qemu_irq handler[16];
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    MemoryRegion iomem;
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    uint16_t status;
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    uint16_t power;
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    uint32_t gpio_level;
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    uint32_t gpio_dir;
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    uint32_t prev_level;
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    uint16_t mcr;
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    uint16_t cdr;
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    uint16_t ccr;
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    uint16_t irr;
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    uint16_t imr;
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    uint16_t isr;
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};
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#define SCOOP_MCR       0x00
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#define SCOOP_CDR       0x04
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#define SCOOP_CSR       0x08
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#define SCOOP_CPR       0x0c
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#define SCOOP_CCR       0x10
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#define SCOOP_IRR_IRM   0x14
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#define SCOOP_IMR       0x18
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#define SCOOP_ISR       0x1c
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#define SCOOP_GPCR      0x20
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#define SCOOP_GPWR      0x24
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#define SCOOP_GPRR      0x28
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static inline void scoop_gpio_handler_update(ScoopInfo *s)
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{
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    uint32_t level, diff;
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    int bit;
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    level = s->gpio_level & s->gpio_dir;
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    for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
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        bit = ctz32(diff);
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        qemu_set_irq(s->handler[bit], (level >> bit) & 1);
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    }
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    s->prev_level = level;
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}
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static uint64_t scoop_read(void *opaque, hwaddr addr,
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                           unsigned size)
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{
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    ScoopInfo *s = (ScoopInfo *) opaque;
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    switch (addr & 0x3f) {
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    case SCOOP_MCR:
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        return s->mcr;
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    case SCOOP_CDR:
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        return s->cdr;
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    case SCOOP_CSR:
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        return s->status;
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    case SCOOP_CPR:
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        return s->power;
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    case SCOOP_CCR:
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        return s->ccr;
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    case SCOOP_IRR_IRM:
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        return s->irr;
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    case SCOOP_IMR:
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        return s->imr;
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    case SCOOP_ISR:
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        return s->isr;
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    case SCOOP_GPCR:
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        return s->gpio_dir;
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    case SCOOP_GPWR:
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    case SCOOP_GPRR:
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        return s->gpio_level;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n",
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                      addr);
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    }
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    return 0;
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}
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static void scoop_write(void *opaque, hwaddr addr,
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                        uint64_t value, unsigned size)
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{
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    ScoopInfo *s = (ScoopInfo *) opaque;
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    value &= 0xffff;
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    switch (addr & 0x3f) {
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    case SCOOP_MCR:
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        s->mcr = value;
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        break;
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    case SCOOP_CDR:
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        s->cdr = value;
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        break;
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    case SCOOP_CPR:
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        s->power = value;
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        if (value & 0x80) {
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            s->power |= 0x8040;
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        }
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        break;
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    case SCOOP_CCR:
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        s->ccr = value;
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        break;
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    case SCOOP_IRR_IRM:
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        s->irr = value;
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        break;
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    case SCOOP_IMR:
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        s->imr = value;
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        break;
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    case SCOOP_ISR:
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        s->isr = value;
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        break;
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    case SCOOP_GPCR:
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        s->gpio_dir = value;
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        scoop_gpio_handler_update(s);
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        break;
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    case SCOOP_GPWR:
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    case SCOOP_GPRR:    /* GPRR is probably R/O in real HW */
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        s->gpio_level = value & s->gpio_dir;
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        scoop_gpio_handler_update(s);
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n",
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                      addr);
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    }
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}
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static const MemoryRegionOps scoop_ops = {
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    .read = scoop_read,
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    .write = scoop_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void scoop_gpio_set(void *opaque, int line, int level)
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{
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    ScoopInfo *s = (ScoopInfo *) opaque;
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    if (level) {
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        s->gpio_level |= (1 << line);
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    } else {
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        s->gpio_level &= ~(1 << line);
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    }
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}
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static void scoop_init(Object *obj)
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{
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    DeviceState *dev = DEVICE(obj);
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    ScoopInfo *s = SCOOP(obj);
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    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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    s->status = 0x02;
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    qdev_init_gpio_out(dev, s->handler, 16);
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    qdev_init_gpio_in(dev, scoop_gpio_set, 16);
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    memory_region_init_io(&s->iomem, obj, &scoop_ops, s, "scoop", 0x1000);
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    sysbus_init_mmio(sbd, &s->iomem);
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}
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static int scoop_post_load(void *opaque, int version_id)
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{
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    ScoopInfo *s = (ScoopInfo *) opaque;
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    int i;
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    uint32_t level;
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    level = s->gpio_level & s->gpio_dir;
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    for (i = 0; i < 16; i++) {
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        qemu_set_irq(s->handler[i], (level >> i) & 1);
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    }
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    s->prev_level = level;
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    return 0;
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}
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static bool is_version_0(void *opaque, int version_id)
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{
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    return version_id == 0;
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}
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static bool vmstate_scoop_validate(void *opaque, int version_id)
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{
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    ScoopInfo *s = opaque;
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    return !(s->prev_level & 0xffff0000) &&
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        !(s->gpio_level & 0xffff0000) &&
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        !(s->gpio_dir & 0xffff0000);
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}
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static const VMStateDescription vmstate_scoop_regs = {
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    .name = "scoop",
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    .version_id = 1,
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    .minimum_version_id = 0,
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    .post_load = scoop_post_load,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT16(status, ScoopInfo),
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        VMSTATE_UINT16(power, ScoopInfo),
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        VMSTATE_UINT32(gpio_level, ScoopInfo),
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        VMSTATE_UINT32(gpio_dir, ScoopInfo),
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        VMSTATE_UINT32(prev_level, ScoopInfo),
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        VMSTATE_VALIDATE("irq levels are 16 bit", vmstate_scoop_validate),
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        VMSTATE_UINT16(mcr, ScoopInfo),
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        VMSTATE_UINT16(cdr, ScoopInfo),
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        VMSTATE_UINT16(ccr, ScoopInfo),
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        VMSTATE_UINT16(irr, ScoopInfo),
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        VMSTATE_UINT16(imr, ScoopInfo),
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        VMSTATE_UINT16(isr, ScoopInfo),
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        VMSTATE_UNUSED_TEST(is_version_0, 2),
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        VMSTATE_END_OF_LIST(),
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    },
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};
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static void scoop_sysbus_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    dc->desc = "Scoop2 Sharp custom ASIC";
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    dc->vmsd = &vmstate_scoop_regs;
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}
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static const TypeInfo scoop_sysbus_info = {
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    .name          = TYPE_SCOOP,
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    .parent        = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(ScoopInfo),
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    .instance_init = scoop_init,
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    .class_init    = scoop_sysbus_class_init,
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};
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static void scoop_register_types(void)
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{
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    type_register_static(&scoop_sysbus_info);
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}
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type_init(scoop_register_types)
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/* Write the bootloader parameters memory area.  */
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#define MAGIC_CHG(a, b, c, d)   ((d << 24) | (c << 16) | (b << 8) | a)
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static struct QEMU_PACKED sl_param_info {
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    uint32_t comadj_keyword;
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    int32_t comadj;
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    uint32_t uuid_keyword;
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    char uuid[16];
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    uint32_t touch_keyword;
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    int32_t touch_xp;
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    int32_t touch_yp;
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    int32_t touch_xd;
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    int32_t touch_yd;
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    uint32_t adadj_keyword;
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    int32_t adadj;
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    uint32_t phad_keyword;
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    int32_t phadadj;
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} zaurus_bootparam = {
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    .comadj_keyword     = MAGIC_CHG('C', 'M', 'A', 'D'),
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    .comadj             = 125,
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    .uuid_keyword       = MAGIC_CHG('U', 'U', 'I', 'D'),
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    .uuid               = { -1 },
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    .touch_keyword      = MAGIC_CHG('T', 'U', 'C', 'H'),
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    .touch_xp           = -1,
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    .adadj_keyword      = MAGIC_CHG('B', 'V', 'A', 'D'),
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    .adadj              = -1,
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    .phad_keyword       = MAGIC_CHG('P', 'H', 'A', 'D'),
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    .phadadj            = 0x01,
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};
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void sl_bootparam_write(hwaddr ptr)
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{
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    cpu_physical_memory_write(ptr, &zaurus_bootparam,
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                              sizeof(struct sl_param_info));
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}
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