qemu

1
/*
2
 * STM32L4x5 GPIO (General Purpose Input/Ouput)
3
 *
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 * Copyright (c) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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 * Copyright (c) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>
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 *
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 * SPDX-License-Identifier: GPL-2.0-or-later
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 *
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 * This work is licensed under the terms of the GNU GPL, version 2 or later.
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 * See the COPYING file in the top-level directory.
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 */
12

13
/*
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 * The reference used is the STMicroElectronics RM0351 Reference manual
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 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
17
 */
18

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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/gpio/stm32l4x5_gpio.h"
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#include "hw/irq.h"
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#include "hw/clock.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "qapi/visitor.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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#define GPIO_MODER 0x00
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#define GPIO_OTYPER 0x04
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#define GPIO_OSPEEDR 0x08
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#define GPIO_PUPDR 0x0C
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#define GPIO_IDR 0x10
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#define GPIO_ODR 0x14
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#define GPIO_BSRR 0x18
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#define GPIO_LCKR 0x1C
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#define GPIO_AFRL 0x20
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#define GPIO_AFRH 0x24
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#define GPIO_BRR 0x28
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#define GPIO_ASCR 0x2C
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/* 0b11111111_11111111_00000000_00000000 */
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#define RESERVED_BITS_MASK 0xFFFF0000
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static void update_gpio_idr(Stm32l4x5GpioState *s);
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static bool is_pull_up(Stm32l4x5GpioState *s, unsigned pin)
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{
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    return extract32(s->pupdr, 2 * pin, 2) == 1;
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}
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static bool is_pull_down(Stm32l4x5GpioState *s, unsigned pin)
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{
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    return extract32(s->pupdr, 2 * pin, 2) == 2;
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}
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static bool is_output(Stm32l4x5GpioState *s, unsigned pin)
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{
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    return extract32(s->moder, 2 * pin, 2) == 1;
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}
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static bool is_open_drain(Stm32l4x5GpioState *s, unsigned pin)
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{
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    return extract32(s->otyper, pin, 1) == 1;
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}
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static bool is_push_pull(Stm32l4x5GpioState *s, unsigned pin)
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{
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    return extract32(s->otyper, pin, 1) == 0;
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}
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static void stm32l4x5_gpio_reset_hold(Object *obj, ResetType type)
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{
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    Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
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    s->moder = s->moder_reset;
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    s->otyper = 0x00000000;
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    s->ospeedr = s->ospeedr_reset;
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    s->pupdr = s->pupdr_reset;
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    s->idr = 0x00000000;
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    s->odr = 0x00000000;
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    s->lckr = 0x00000000;
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    s->afrl = 0x00000000;
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    s->afrh = 0x00000000;
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    s->ascr = 0x00000000;
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    s->disconnected_pins = 0xFFFF;
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    s->pins_connected_high = 0x0000;
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    update_gpio_idr(s);
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}
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static void stm32l4x5_gpio_set(void *opaque, int line, int level)
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{
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    Stm32l4x5GpioState *s = opaque;
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    /*
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     * The pin isn't set if line is configured in output mode
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     * except if level is 0 and the output is open-drain.
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     * This way there will be no short-circuit prone situations.
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     */
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    if (is_output(s, line) && !(is_open_drain(s, line) && (level == 0))) {
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        qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",
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                      line);
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        return;
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    }
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    s->disconnected_pins &= ~(1 << line);
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    if (level) {
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        s->pins_connected_high |= (1 << line);
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    } else {
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        s->pins_connected_high &= ~(1 << line);
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    }
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    trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
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                              s->pins_connected_high);
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    update_gpio_idr(s);
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}
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static void update_gpio_idr(Stm32l4x5GpioState *s)
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{
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    uint32_t new_idr_mask = 0;
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    uint32_t new_idr = s->odr;
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    uint32_t old_idr = s->idr;
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    int new_pin_state, old_pin_state;
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    for (int i = 0; i < GPIO_NUM_PINS; i++) {
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        if (is_output(s, i)) {
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            if (is_push_pull(s, i)) {
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                new_idr_mask |= (1 << i);
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            } else if (!(s->odr & (1 << i))) {
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                /* open-drain ODR 0 */
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                new_idr_mask |= (1 << i);
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            /* open-drain ODR 1 */
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            } else if (!(s->disconnected_pins & (1 << i)) &&
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                       !(s->pins_connected_high & (1 << i))) {
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                /* open-drain ODR 1 with pin connected low */
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                new_idr_mask |= (1 << i);
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                new_idr &= ~(1 << i);
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            /* open-drain ODR 1 with unactive pin */
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            } else if (is_pull_up(s, i)) {
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                new_idr_mask |= (1 << i);
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            } else if (is_pull_down(s, i)) {
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                new_idr_mask |= (1 << i);
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                new_idr &= ~(1 << i);
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            }
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            /*
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             * The only case left is for open-drain ODR 1
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             * with unactive pin without pull-up or pull-down :
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             * the value is floating.
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             */
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        /* input or analog mode with connected pin */
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        } else if (!(s->disconnected_pins & (1 << i))) {
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            if (s->pins_connected_high & (1 << i)) {
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                /* pin high */
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                new_idr_mask |= (1 << i);
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                new_idr |= (1 << i);
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            } else {
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                /* pin low */
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                new_idr_mask |= (1 << i);
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                new_idr &= ~(1 << i);
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            }
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        /* input or analog mode with disconnected pin */
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        } else {
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            if (is_pull_up(s, i)) {
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                /* pull-up */
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                new_idr_mask |= (1 << i);
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                new_idr |= (1 << i);
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            } else if (is_pull_down(s, i)) {
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                /* pull-down */
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                new_idr_mask |= (1 << i);
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                new_idr &= ~(1 << i);
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            }
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            /*
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             * The only case left is for a disconnected pin
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             * without pull-up or pull-down :
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             * the value is floating.
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             */
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        }
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    }
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    s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);
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    trace_stm32l4x5_gpio_update_idr(s->name, old_idr, s->idr);
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    for (int i = 0; i < GPIO_NUM_PINS; i++) {
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        if (new_idr_mask & (1 << i)) {
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            new_pin_state = (new_idr & (1 << i)) > 0;
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            old_pin_state = (old_idr & (1 << i)) > 0;
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            if (new_pin_state > old_pin_state) {
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                qemu_irq_raise(s->pin[i]);
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            } else if (new_pin_state < old_pin_state) {
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                qemu_irq_lower(s->pin[i]);
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            }
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        }
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    }
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}
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/*
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 * Return mask of pins that are both configured in output
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 * mode and externally driven (except pins in open-drain
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 * mode externally set to 0).
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 */
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static uint32_t get_gpio_pinmask_to_disconnect(Stm32l4x5GpioState *s)
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{
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    uint32_t pins_to_disconnect = 0;
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    for (int i = 0; i < GPIO_NUM_PINS; i++) {
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        /* for each connected pin in output mode */
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        if (!(s->disconnected_pins & (1 << i)) && is_output(s, i)) {
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            /* if either push-pull or high level */
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            if (is_push_pull(s, i) || s->pins_connected_high & (1 << i)) {
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                pins_to_disconnect |= (1 << i);
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                qemu_log_mask(LOG_GUEST_ERROR,
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                              "Line %d can't be driven externally\n",
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                              i);
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            }
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        }
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    }
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    return pins_to_disconnect;
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}
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/*
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 * Set field `disconnected_pins` and call `update_gpio_idr()`
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 */
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static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)
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{
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    s->disconnected_pins |= lines;
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    trace_stm32l4x5_gpio_pins(s->name, s->disconnected_pins,
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                              s->pins_connected_high);
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    update_gpio_idr(s);
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}
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static void disconnected_pins_set(Object *obj, Visitor *v,
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    const char *name, void *opaque, Error **errp)
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{
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    Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
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    uint16_t value;
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    if (!visit_type_uint16(v, name, &value, errp)) {
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        return;
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    }
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    disconnect_gpio_pins(s, value);
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}
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static void disconnected_pins_get(Object *obj, Visitor *v,
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    const char *name, void *opaque, Error **errp)
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{
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    visit_type_uint16(v, name, (uint16_t *)opaque, errp);
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}
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static void clock_freq_get(Object *obj, Visitor *v,
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    const char *name, void *opaque, Error **errp)
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{
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    Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
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    uint32_t clock_freq_hz = clock_get_hz(s->clk);
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    visit_type_uint32(v, name, &clock_freq_hz, errp);
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}
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static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,
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                                 uint64_t val64, unsigned int size)
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{
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    Stm32l4x5GpioState *s = opaque;
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    uint32_t value = val64;
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    trace_stm32l4x5_gpio_write(s->name, addr, val64);
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    switch (addr) {
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    case GPIO_MODER:
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        s->moder = value;
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        disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: Analog and AF modes aren't supported\n\
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                       Analog and AF mode behave like input mode\n",
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                      __func__);
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        return;
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    case GPIO_OTYPER:
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        s->otyper = value & ~RESERVED_BITS_MASK;
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        disconnect_gpio_pins(s, get_gpio_pinmask_to_disconnect(s));
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        return;
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    case GPIO_OSPEEDR:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: Changing I/O output speed isn't supported\n\
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                       I/O speed is already maximal\n",
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                      __func__);
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        s->ospeedr = value;
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        return;
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    case GPIO_PUPDR:
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        s->pupdr = value;
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        update_gpio_idr(s);
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        return;
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    case GPIO_IDR:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: GPIO->IDR is read-only\n",
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                      __func__);
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        return;
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    case GPIO_ODR:
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        s->odr = value & ~RESERVED_BITS_MASK;
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        update_gpio_idr(s);
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        return;
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    case GPIO_BSRR: {
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        uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> GPIO_NUM_PINS;
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        uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;
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        /* If both BSx and BRx are set, BSx has priority.*/
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        s->odr &= ~bits_to_reset;
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        s->odr |= bits_to_set;
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        update_gpio_idr(s);
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        return;
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    }
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    case GPIO_LCKR:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: Locking port bits configuration isn't supported\n",
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                      __func__);
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        s->lckr = value & ~RESERVED_BITS_MASK;
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        return;
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    case GPIO_AFRL:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: Alternate functions aren't supported\n",
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                      __func__);
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        s->afrl = value;
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        return;
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    case GPIO_AFRH:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: Alternate functions aren't supported\n",
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                      __func__);
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        s->afrh = value;
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        return;
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    case GPIO_BRR: {
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        uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;
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        s->odr &= ~bits_to_reset;
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        update_gpio_idr(s);
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        return;
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    }
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    case GPIO_ASCR:
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        qemu_log_mask(LOG_UNIMP,
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                      "%s: ADC function isn't supported\n",
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                      __func__);
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        s->ascr = value & ~RESERVED_BITS_MASK;
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        return;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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    }
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}
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static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,
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                                    unsigned int size)
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{
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    Stm32l4x5GpioState *s = opaque;
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    trace_stm32l4x5_gpio_read(s->name, addr);
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    switch (addr) {
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    case GPIO_MODER:
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        return s->moder;
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    case GPIO_OTYPER:
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        return s->otyper;
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    case GPIO_OSPEEDR:
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        return s->ospeedr;
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    case GPIO_PUPDR:
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        return s->pupdr;
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    case GPIO_IDR:
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        return s->idr;
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    case GPIO_ODR:
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        return s->odr;
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    case GPIO_BSRR:
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        return 0;
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    case GPIO_LCKR:
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        return s->lckr;
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    case GPIO_AFRL:
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        return s->afrl;
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    case GPIO_AFRH:
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        return s->afrh;
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    case GPIO_BRR:
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        return 0;
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    case GPIO_ASCR:
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        return s->ascr;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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        return 0;
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    }
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}
381

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static const MemoryRegionOps stm32l4x5_gpio_ops = {
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    .read = stm32l4x5_gpio_read,
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    .write = stm32l4x5_gpio_write,
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    .endianness = DEVICE_NATIVE_ENDIAN,
386
    .impl = {
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        .min_access_size = 4,
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        .max_access_size = 4,
389
        .unaligned = false,
390
    },
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    .valid = {
392
        .min_access_size = 4,
393
        .max_access_size = 4,
394
        .unaligned = false,
395
    },
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};
397

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static void stm32l4x5_gpio_init(Object *obj)
399
{
400
    Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
401

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    memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,
403
                          TYPE_STM32L4X5_GPIO, 0x400);
404

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    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
406

407
    qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);
408
    qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);
409

410
    s->clk = qdev_init_clock_in(DEVICE(s), "clk", NULL, s, 0);
411

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    object_property_add(obj, "disconnected-pins", "uint16",
413
                        disconnected_pins_get, disconnected_pins_set,
414
                        NULL, &s->disconnected_pins);
415
    object_property_add(obj, "clock-freq-hz", "uint32",
416
                        clock_freq_get, NULL, NULL, NULL);
417
}
418

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static void stm32l4x5_gpio_realize(DeviceState *dev, Error **errp)
420
{
421
    Stm32l4x5GpioState *s = STM32L4X5_GPIO(dev);
422
    if (!clock_has_source(s->clk)) {
423
        error_setg(errp, "GPIO: clk input must be connected");
424
        return;
425
    }
426
}
427

428
static const VMStateDescription vmstate_stm32l4x5_gpio = {
429
    .name = TYPE_STM32L4X5_GPIO,
430
    .version_id = 2,
431
    .minimum_version_id = 2,
432
    .fields = (VMStateField[]){
433
        VMSTATE_UINT32(moder, Stm32l4x5GpioState),
434
        VMSTATE_UINT32(otyper, Stm32l4x5GpioState),
435
        VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),
436
        VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),
437
        VMSTATE_UINT32(idr, Stm32l4x5GpioState),
438
        VMSTATE_UINT32(odr, Stm32l4x5GpioState),
439
        VMSTATE_UINT32(lckr, Stm32l4x5GpioState),
440
        VMSTATE_UINT32(afrl, Stm32l4x5GpioState),
441
        VMSTATE_UINT32(afrh, Stm32l4x5GpioState),
442
        VMSTATE_UINT32(ascr, Stm32l4x5GpioState),
443
        VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),
444
        VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),
445
        VMSTATE_CLOCK(clk, Stm32l4x5GpioState),
446
        VMSTATE_END_OF_LIST()
447
    }
448
};
449

450
static Property stm32l4x5_gpio_properties[] = {
451
    DEFINE_PROP_STRING("name", Stm32l4x5GpioState, name),
452
    DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0),
453
    DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0),
454
    DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0),
455
    DEFINE_PROP_END_OF_LIST(),
456
};
457

458
static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)
459
{
460
    DeviceClass *dc = DEVICE_CLASS(klass);
461
    ResettableClass *rc = RESETTABLE_CLASS(klass);
462

463
    device_class_set_props(dc, stm32l4x5_gpio_properties);
464
    dc->vmsd = &vmstate_stm32l4x5_gpio;
465
    dc->realize = stm32l4x5_gpio_realize;
466
    rc->phases.hold = stm32l4x5_gpio_reset_hold;
467
}
468

469
static const TypeInfo stm32l4x5_gpio_types[] = {
470
    {
471
        .name = TYPE_STM32L4X5_GPIO,
472
        .parent = TYPE_SYS_BUS_DEVICE,
473
        .instance_size = sizeof(Stm32l4x5GpioState),
474
        .instance_init = stm32l4x5_gpio_init,
475
        .class_init = stm32l4x5_gpio_class_init,
476
    },
477
};
478

479
DEFINE_TYPES(stm32l4x5_gpio_types)
480