qemu

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/*
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 * SiFive System-on-Chip general purpose input/output register definition
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 *
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 * Copyright 2019 AdaCore
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 *
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 * Base on nrf51_gpio.c:
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 *
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 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
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 *
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 * This code is licensed under the GPL version 2 or later.  See
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 * the COPYING file in the top-level directory.
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 */
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/gpio/sifive_gpio.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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static void update_output_irq(SIFIVEGPIOState *s)
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{
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    uint32_t pending;
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    uint32_t pin;
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    pending = s->high_ip & s->high_ie;
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    pending |= s->low_ip & s->low_ie;
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    pending |= s->rise_ip & s->rise_ie;
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    pending |= s->fall_ip & s->fall_ie;
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    for (int i = 0; i < s->ngpio; i++) {
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        pin = 1 << i;
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        qemu_set_irq(s->irq[i], (pending & pin) != 0);
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        trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0);
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    }
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}
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static void update_state(SIFIVEGPIOState *s)
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{
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    size_t i;
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    bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en,
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        rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival;
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    for (i = 0; i < s->ngpio; i++) {
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        prev_ival = extract32(s->value, i, 1);
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        in        = extract32(s->in, i, 1);
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        in_mask   = extract32(s->in_mask, i, 1);
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        port      = extract32(s->port, i, 1);
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        out_xor   = extract32(s->out_xor, i, 1);
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        pull      = extract32(s->pue, i, 1);
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        output_en = extract32(s->output_en, i, 1);
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        input_en  = extract32(s->input_en, i, 1);
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        rise_ip   = extract32(s->rise_ip, i, 1);
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        fall_ip   = extract32(s->fall_ip, i, 1);
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        low_ip    = extract32(s->low_ip, i, 1);
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        high_ip   = extract32(s->high_ip, i, 1);
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        /* Output value (IOF not supported) */
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        oval = output_en && (port ^ out_xor);
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        /* Pin both driven externally and internally */
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        if (output_en && in_mask) {
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            qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i);
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        }
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        if (in_mask) {
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            /* The pin is driven by external device */
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            actual_value = in;
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        } else if (output_en) {
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            /* The pin is driven by internal circuit */
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            actual_value = oval;
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        } else {
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            /* Floating? Apply pull-up resistor */
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            actual_value = pull;
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        }
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        if (output_en) {
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            qemu_set_irq(s->output[i], actual_value);
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        }
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        /* Input value */
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        ival = input_en && actual_value;
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        /* Interrupts */
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        high_ip = high_ip || ival;
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        s->high_ip = deposit32(s->high_ip, i, 1, high_ip);
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        low_ip = low_ip || !ival;
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        s->low_ip = deposit32(s->low_ip,  i, 1, low_ip);
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        rise_ip = rise_ip || (ival && !prev_ival);
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        s->rise_ip = deposit32(s->rise_ip, i, 1, rise_ip);
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        fall_ip = fall_ip || (!ival && prev_ival);
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        s->fall_ip = deposit32(s->fall_ip, i, 1, fall_ip);
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        /* Update value */
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        s->value = deposit32(s->value, i, 1, ival);
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    }
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    update_output_irq(s);
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}
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static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
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{
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    SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
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    uint64_t r = 0;
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    switch (offset) {
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    case SIFIVE_GPIO_REG_VALUE:
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        r = s->value;
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        break;
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    case SIFIVE_GPIO_REG_INPUT_EN:
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        r = s->input_en;
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        break;
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    case SIFIVE_GPIO_REG_OUTPUT_EN:
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        r = s->output_en;
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        break;
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    case SIFIVE_GPIO_REG_PORT:
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        r = s->port;
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        break;
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    case SIFIVE_GPIO_REG_PUE:
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        r = s->pue;
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        break;
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    case SIFIVE_GPIO_REG_DS:
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        r = s->ds;
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        break;
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    case SIFIVE_GPIO_REG_RISE_IE:
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        r = s->rise_ie;
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        break;
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    case SIFIVE_GPIO_REG_RISE_IP:
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        r = s->rise_ip;
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        break;
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    case SIFIVE_GPIO_REG_FALL_IE:
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        r = s->fall_ie;
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        break;
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    case SIFIVE_GPIO_REG_FALL_IP:
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        r = s->fall_ip;
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        break;
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    case SIFIVE_GPIO_REG_HIGH_IE:
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        r = s->high_ie;
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        break;
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    case SIFIVE_GPIO_REG_HIGH_IP:
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        r = s->high_ip;
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        break;
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    case SIFIVE_GPIO_REG_LOW_IE:
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        r = s->low_ie;
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        break;
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    case SIFIVE_GPIO_REG_LOW_IP:
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        r = s->low_ip;
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        break;
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    case SIFIVE_GPIO_REG_IOF_EN:
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        r = s->iof_en;
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        break;
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    case SIFIVE_GPIO_REG_IOF_SEL:
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        r = s->iof_sel;
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        break;
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    case SIFIVE_GPIO_REG_OUT_XOR:
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        r = s->out_xor;
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                "%s: bad read offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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    }
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    trace_sifive_gpio_read(offset, r);
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    return r;
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}
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static void sifive_gpio_write(void *opaque, hwaddr offset,
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                              uint64_t value, unsigned int size)
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{
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    SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
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    trace_sifive_gpio_write(offset, value);
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    switch (offset) {
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    case SIFIVE_GPIO_REG_INPUT_EN:
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        s->input_en = value;
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        break;
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    case SIFIVE_GPIO_REG_OUTPUT_EN:
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        s->output_en = value;
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        break;
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    case SIFIVE_GPIO_REG_PORT:
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        s->port = value;
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        break;
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    case SIFIVE_GPIO_REG_PUE:
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        s->pue = value;
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        break;
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    case SIFIVE_GPIO_REG_DS:
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        s->ds = value;
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        break;
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    case SIFIVE_GPIO_REG_RISE_IE:
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        s->rise_ie = value;
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        break;
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    case SIFIVE_GPIO_REG_RISE_IP:
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         /* Write 1 to clear */
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        s->rise_ip &= ~value;
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        break;
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    case SIFIVE_GPIO_REG_FALL_IE:
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        s->fall_ie = value;
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        break;
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    case SIFIVE_GPIO_REG_FALL_IP:
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         /* Write 1 to clear */
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        s->fall_ip &= ~value;
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        break;
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    case SIFIVE_GPIO_REG_HIGH_IE:
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        s->high_ie = value;
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        break;
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    case SIFIVE_GPIO_REG_HIGH_IP:
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         /* Write 1 to clear */
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        s->high_ip &= ~value;
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        break;
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    case SIFIVE_GPIO_REG_LOW_IE:
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        s->low_ie = value;
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        break;
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    case SIFIVE_GPIO_REG_LOW_IP:
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         /* Write 1 to clear */
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        s->low_ip &= ~value;
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        break;
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    case SIFIVE_GPIO_REG_IOF_EN:
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        s->iof_en = value;
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        break;
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    case SIFIVE_GPIO_REG_IOF_SEL:
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        s->iof_sel = value;
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        break;
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    case SIFIVE_GPIO_REG_OUT_XOR:
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        s->out_xor = value;
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        break;
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    default:
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        qemu_log_mask(LOG_GUEST_ERROR,
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                      "%s: bad write offset 0x%" HWADDR_PRIx "\n",
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                      __func__, offset);
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    }
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    update_state(s);
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}
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static const MemoryRegionOps gpio_ops = {
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    .read =  sifive_gpio_read,
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    .write = sifive_gpio_write,
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    .endianness = DEVICE_LITTLE_ENDIAN,
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    .impl.min_access_size = 4,
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    .impl.max_access_size = 4,
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};
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static void sifive_gpio_set(void *opaque, int line, int value)
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{
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    SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
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    trace_sifive_gpio_set(line, value);
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    assert(line >= 0 && line < SIFIVE_GPIO_PINS);
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    s->in_mask = deposit32(s->in_mask, line, 1, value >= 0);
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    if (value >= 0) {
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        s->in = deposit32(s->in, line, 1, value != 0);
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    }
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    update_state(s);
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}
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static void sifive_gpio_reset(DeviceState *dev)
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{
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    SIFIVEGPIOState *s = SIFIVE_GPIO(dev);
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    s->value = 0;
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    s->input_en = 0;
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    s->output_en = 0;
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    s->port = 0;
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    s->pue = 0;
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    s->ds = 0;
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    s->rise_ie = 0;
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    s->rise_ip = 0;
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    s->fall_ie = 0;
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    s->fall_ip = 0;
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    s->high_ie = 0;
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    s->high_ip = 0;
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    s->low_ie = 0;
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    s->low_ip = 0;
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    s->iof_en = 0;
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    s->iof_sel = 0;
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    s->out_xor = 0;
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    s->in = 0;
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    s->in_mask = 0;
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}
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static const VMStateDescription vmstate_sifive_gpio = {
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    .name = TYPE_SIFIVE_GPIO,
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    .version_id = 1,
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    .minimum_version_id = 1,
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    .fields = (const VMStateField[]) {
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        VMSTATE_UINT32(value,     SIFIVEGPIOState),
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        VMSTATE_UINT32(input_en,  SIFIVEGPIOState),
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        VMSTATE_UINT32(output_en, SIFIVEGPIOState),
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        VMSTATE_UINT32(port,      SIFIVEGPIOState),
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        VMSTATE_UINT32(pue,       SIFIVEGPIOState),
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        VMSTATE_UINT32(rise_ie,   SIFIVEGPIOState),
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        VMSTATE_UINT32(rise_ip,   SIFIVEGPIOState),
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        VMSTATE_UINT32(fall_ie,   SIFIVEGPIOState),
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        VMSTATE_UINT32(fall_ip,   SIFIVEGPIOState),
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        VMSTATE_UINT32(high_ie,   SIFIVEGPIOState),
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        VMSTATE_UINT32(high_ip,   SIFIVEGPIOState),
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        VMSTATE_UINT32(low_ie,    SIFIVEGPIOState),
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        VMSTATE_UINT32(low_ip,    SIFIVEGPIOState),
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        VMSTATE_UINT32(iof_en,    SIFIVEGPIOState),
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        VMSTATE_UINT32(iof_sel,   SIFIVEGPIOState),
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        VMSTATE_UINT32(out_xor,   SIFIVEGPIOState),
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        VMSTATE_UINT32(in,        SIFIVEGPIOState),
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        VMSTATE_UINT32(in_mask,   SIFIVEGPIOState),
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        VMSTATE_END_OF_LIST()
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    }
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};
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static Property sifive_gpio_properties[] = {
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    DEFINE_PROP_UINT32("ngpio", SIFIVEGPIOState, ngpio, SIFIVE_GPIO_PINS),
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    DEFINE_PROP_END_OF_LIST(),
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};
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static void sifive_gpio_realize(DeviceState *dev, Error **errp)
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{
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    SIFIVEGPIOState *s = SIFIVE_GPIO(dev);
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    memory_region_init_io(&s->mmio, OBJECT(dev), &gpio_ops, s,
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            TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
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    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
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    for (int i = 0; i < s->ngpio; i++) {
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        sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
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    }
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    qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, s->ngpio);
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    qdev_init_gpio_out(DEVICE(s), s->output, s->ngpio);
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}
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static void sifive_gpio_class_init(ObjectClass *klass, void *data)
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{
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    DeviceClass *dc = DEVICE_CLASS(klass);
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    device_class_set_props(dc, sifive_gpio_properties);
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    dc->vmsd = &vmstate_sifive_gpio;
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    dc->realize = sifive_gpio_realize;
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    dc->reset = sifive_gpio_reset;
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    dc->desc = "SiFive GPIO";
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}
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static const TypeInfo sifive_gpio_info = {
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    .name = TYPE_SIFIVE_GPIO,
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    .parent = TYPE_SYS_BUS_DEVICE,
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    .instance_size = sizeof(SIFIVEGPIOState),
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    .class_init = sifive_gpio_class_init
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};
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static void sifive_gpio_register_types(void)
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{
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    type_register_static(&sifive_gpio_info);
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}
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type_init(sifive_gpio_register_types)
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